[PATCH, V8] Fix PR 118541, do not generate unordered fp compares

fmr 1,3 blr normal_compare: xscmpgtdp 1,1,2 xxsel 1,4,3,1 blr 2025-07-30 Michael Meissner gcc/ PR target/118541 * config/rs6000/predicates.md (fpmask_comparison_operator): Add NE

[PATCH, V4] Add -mcpu=future to the PowerPC

This patch adds the support that can be used in developing GCC support for future PowerPC processors. This support is done by adding support for CPU ISA bits that are set directly via the -mcpu= option, without having a -m bit. 2025-07-23 Michael Meissner gcc/ * config.gcc (powerpc

Re: [PATCH, V3] Add -mcpu=future to the PowerPC

On Tue, Jul 15, 2025 at 08:11:05AM -0500, Segher Boessenkool wrote: > Hi! > > On Tue, Jul 01, 2025 at 12:14:32PM -0400, Michael Meissner wrote: > > This patch adds the support that can be used in developing GCC support > > for potential future PowerPC processors. > >

Ping: [PATCH, V3] Add -mcpu=future to the PowerPC

Ping patch: | Date: Tue, 1 Jul 2025 12:14:32 -0400 | From: Michael Meissner | Subject: [PATCH, V3] Add -mcpu=future to the PowerPC | Message-ID: https://gcc.gnu.org/pipermail/gcc-patches/2025-July/688251.html -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: meiss

[PATCH, V3] Add -mcpu=future to the PowerPC

d new tuning rules a potential future processor, we will add the support for the new processor. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-07-01 Michael Meissner gcc/ * config/r

Re: [PATCH, V2, 1 of 3] Add -mcpu=future support.

On Fri, Jun 27, 2025 at 12:29:06PM -0500, Segher Boessenkool wrote: > Hi! > > On Wed, Jun 25, 2025 at 02:50:14PM -0400, Michael Meissner wrote: > > This is patch #1 of 3 that adds the support that can be used in developing > > GCC > > support for potential future Powe

[PATCH, V2, 3 of 3] Add -mcpu=future tests.

little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-25 Michael Meissner gcc/testsuite/ * gcc.target/powerpc/future-1.c: New test. * gcc.target/powerpc/future-2.c: Likewise. --- gcc/testsuite/gcc.target/powerpc/future-1.c | 13

[PATCH, V2, 2 of 3] Add Add -mcpu=future tuning support.

or we can easily remove processors. For example, we might want to modify the -mtune=future rules in the future. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-24 Michael Meissner gcc/

[PATCH, V2, 1 of 3] Add -mcpu=future support.

e trunk? 2025-06-25 Michael Meissner gcc/ * config.guess (powerpc*-*-*): Add support for using --with-cpu=future. * config/rs6000/aix71.h (ASM_CPU_SPEC): Pass -mfuture to the assembler if -mcpu=future was used on the command line. * config/rs6000/aix72.h (ASM

Re: [PATCH, 1 of 4] Add -mcpu=future support for PowerPC

On Mon, Jun 23, 2025 at 07:30:51PM +0530, Surya Kumari Jangala wrote: > Hi Mike, > > On 14/06/25 2:07 pm, Michael Meissner wrote: > > This is patch #1 of 4 that adds the support that can be used in developing > > GCC > > support for future PowerPC processors. &g

Re: [PATCH, 1 of 4] Add -mcpu=future support for PowerPC

On Mon, Jun 23, 2025 at 07:30:51PM +0530, Surya Kumari Jangala wrote: > Hi Mike, > > On 14/06/25 2:07 pm, Michael Meissner wrote: > > This is patch #1 of 4 that adds the support that can be used in developing > > GCC > > support for future PowerPC processors. &g

Re: [PATCH, 4 of 4] Use vector pair for memory operations with -mcpu=future

On Fri, Jun 20, 2025 at 01:19:45PM -0500, Segher Boessenkool wrote: > Hi! > > On Fri, Jun 20, 2025 at 10:38:30PM +0530, Surya Kumari Jangala wrote: > > On 14/06/25 2:13 pm, Michael Meissner wrote: > > > This is patch #4 of 4 to add -mcpu=future support to the PowerPC. >

Ping: [PATCH V4 5/5] Change TARGET_MODULO to TARGET_POWER9.

TARGET_POWER7): https://gcc.gnu.org/pipermail/gcc-patches/2024-November/669071.html Patch 5 of 5 (change TARGET_MODULO to TARGET_POWER9): https://gcc.gnu.org/pipermail/gcc-patches/2024-November/669072.html -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: meiss...@linux.ibm.com

Ping: [PATCH V4 4/5] Change TARGET_POPCNTD to TARGET_POWER7.

TARGET_POWER7): https://gcc.gnu.org/pipermail/gcc-patches/2024-November/669071.html Patch 5 of 5 (change TARGET_MODULO to TARGET_POWER9): https://gcc.gnu.org/pipermail/gcc-patches/2024-November/669072.html -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: meiss...@linux.ibm.com

Ping: [PATCH V4 3/5] Change TARGET_CMPB to TARGET_POWER6.

TARGET_POWER7): https://gcc.gnu.org/pipermail/gcc-patches/2024-November/669071.html Patch 5 of 5 (change TARGET_MODULO to TARGET_POWER9): https://gcc.gnu.org/pipermail/gcc-patches/2024-November/669072.html -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: meiss...@linux.ibm.com

Ping: [PATCH V4 2/5] Change TARGET_FPRND to TARGET_POWER5X.

TARGET_POWER7): https://gcc.gnu.org/pipermail/gcc-patches/2024-November/669071.html Patch 5 of 5 (change TARGET_MODULO to TARGET_POWER9): https://gcc.gnu.org/pipermail/gcc-patches/2024-November/669072.html -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: meiss...@linux.ibm.com

Ping: [PATCH V4 1/5] Change TARGET_POPCNTB to TARGET_POWER5.

://gcc.gnu.org/pipermail/gcc-patches/2024-November/669071.html Patch 5 of 5 (change TARGET_MODULO to TARGET_POWER9): https://gcc.gnu.org/pipermail/gcc-patches/2024-November/669072.html -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: meiss...@linux.ibm.com

Ping: [PATCH V4 0/5] Add more user friendly TARGET_ names for PowerPC

TARGET_POPCNTD to TARGET_POWER7): https://gcc.gnu.org/pipermail/gcc-patches/2024-November/669071.html Patch 5 of 5 (change TARGET_MODULO to TARGET_POWER9): https://gcc.gnu.org/pipermail/gcc-patches/2024-November/669072.html -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: meiss

[PATCH] PR target/120681 - allow -mcmodel=large with PC relative addressing

code generation using BOOT_CLFAGS='-g -O2 -mcmodel=large' to make sure there were no regressions. Can I check this patch into the master GCC branch? After an appropriate burn-in time, can I check this patch into the active branches also? 2025-06-17 Michael Meissner gcc/ P

[PATCH, 4 of 4] Use vector pair for memory operations with -mcpu=future

used. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-13 Michael Meissner gcc/ * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Enable using load vector pair and

[PATCH, 3 of 4] Add -mcpu=future tests

This is patch #3 of 4 to add -mcpu=future support to the PowerPC. This patch adds simple tests for -mcpu=future. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-13 Michael Meissner gcc

[PATCH, 2 of 4] Add tuning support for -mcpu=future

the trunk? 2025-06-13 Michael Meissner gcc/ * config/rs6000/power10.md (all reservations): Add future as an alterntive to power10 and power11. --- gcc/config/rs6000/power10.md | 145 ++- 1 file changed, 73 insertions(+), 72 deletions(-) diff

[PATCH, 1 of 4] Add -mcpu=future support for PowerPC

This is patch #1 of 4 that adds the support that can be used in developing GCC support for future PowerPC processors. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-13 Michael Meissner

[PATCH 7/45, V2] PR target/117251: Improve vector orc to vector and fusion

a prefixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michael Meissner gc

[PATCH 45/45, V2] PR target/117251: Add tests

PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michael Meissner gcc/testsuite/ PR target/117251 * gcc.target/powerpc/p10-vector-fused-1.c: New test. * gcc.target/powerpc/p10-vector-fused-2.c: Likewise. --- .

[PATCH 42/45, V2] PR target/117251: Improve vector xor to vector nand fusion

; is a prefixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michael Me

[PATCH 29/45, V2] PR target/117251: Improve vector eqv to vector or fusion

refixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michael Meissn

[PATCH 24/45, V2] PR target/117251: Improve vector or to vector nor fusion

refixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michael Meissn

[PATCH 44/45, V2] PR target/117251: Improve vector and to vector nand fusion

#x27; is a prefixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michae

[PATCH 31/45, V2] PR target/117251: Improve vector orc to vector or fusion

refixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michael Meissn

[PATCH 14/45, V2] PR target/117251: Improve vector andc to vector or fusion

a prefixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michael Me

[PATCH 38/45, V2] PR target/117251: Improve vector orc to vector nand fusion

; is a prefixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michael Me

[PATCH 41/45, V2] PR target/117251: Improve vector or to vector nand fusion

; is a prefixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michael Me

[PATCH 43/45, V2] PR target/117251: Improve vector andc to vector nand fusion

XEVAL' is a prefixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michae

[PATCH 5/45, V2] PR target/117251: Improve vector nor to vector and fusion

a prefixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michael Me

[PATCH 18/45, V2] PR target/117251: Improve vector eqv to vector nor fusion

a prefixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michael Meissn

[PATCH 30/45, V2] PR target/117251: Improve vector orc to vector xor fusion

refixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michael Meissn

[PATCH 12/45, V2] PR target/117251: Improve vector and to vector or fusion

a prefixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michael Meissner gc

[PATCH 28/45, V2] PR target/117251: Improve vector eqv to vector xor fusion

a prefixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michael Meissn

[PATCH 40/45, V2] PR target/117251: Improve vector nor to vector nand fusion

L' is a prefixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michael Me

[PATCH 16/45, V2] PR target/117251: Improve vector orc to vector eqv fusion

a prefixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michael Meissn

[PATCH 26/45, V2] PR target/117251: Improve vector nor to vector or fusion

refixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michael Meissn

[PATCH 21/45, V2] PR target/117251: Improve vector nor to vector nor fusion

27; is a prefixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michael Meissn

[PATCH 3/45, V2] PR target/117251: Improve vector xor to vector and fusion

a prefixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michael Meissner gc

[PATCH 22/45, V2] PR target/117251: Improve vector or to vector xor fusion

refixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michael Meissner gcc/

[PATCH 25/45, V2] PR target/117251: Improve vector nor to vector xor fusion

a prefixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michael Meissn

[PATCH 37/45, V2] PR target/117251: Improve vector nand to vector nand fusion

XEVAL' is a prefixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michae

[PATCH 39/45, V2] PR target/117251: Improve vector eqv to vector nand fusion

L' is a prefixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michael Me

[PATCH 20/45, V2] PR target/117251: Improve vector xor to vector or fusion

refixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michael Meissner gcc/

[PATCH 33/45, V2] PR target/117251: Improve vector andc to vector eqv fusion

; is a prefixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michael Me

[PATCH 32/45, V2] PR target/117251: Improve vector andc to vector nor fusion

; is a prefixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michael Me

[PATCH 17/45, V2] PR target/117251: Improve vector orc to vector orc fusion

refixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michael Meissn

[PATCH 34/45, V2] PR target/117251: Improve vector and to vector nor fusion

; is a prefixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michael Me

[PATCH 27/45, V2] PR target/117251: Improve vector xor to vector nor fusion

a prefixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michael Meissn

[PATCH 13/45, V2] PR target/117251: Improve vector andc to vector xor fusion

a prefixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michael Me

[PATCH 8/45, V2] PR target/117251: Improve vector andc to vector andc fusion

#x27; is a prefixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michae

[PATCH 36/45, V2] PR target/117251: Improve vector nand to vector or fusion

; is a prefixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michael Me

[PATCH 23/45, V2] PR target/117251: Improve vector or to vector or fusion

refixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michael Meissner gcc/

[PATCH 6/45, V2] PR target/117251: Improve vector eqv to vector and fusion

a prefixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michael Me

[PATCH 9/45, V2] PR target/117251: Improve vector nand to vector and fusion

; is a prefixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michae

[PATCH 35/45, V2] PR target/117251: Improve vector nand to vector xor fusion

; is a prefixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michael Me

[PATCH 15/45, V2] PR target/117251: Improve vector orc to vector nor fusion

a prefixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michael Meissn

[PATCH 2/45, V2] PR target/117251: Improve vector andc to vector and fusion

; is a prefixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michael Meissner

[PATCH 4/45, V2] PR target/117251: Improve vector or to vector and fusion

a prefixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michael Meissner gc

[PATCH 10/45, V2] PR target/117251: Improve vector nand to vector nor fusion

L' is a prefixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michael Me

[PATCH 11/45, V2] PR target/117251: Improve vector and to vector xor fusion

a prefixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michael Meissner gc

[PATCH 1/45, V2] PR target/117251: Improve vector and to vector and fusion

; is a prefixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michael Meissner

[PATCH 19/45, V2] PR target/117251: Improve vector xor to vector xor fusion

refixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2025-06-11 Michael Meissner gcc/

[PATCH 0/45, V2] PR target/117251: Add PowerPC XXEVAL support to speed up SHA3 calculations

or xxlnand => xxlor xxlnand => xxlnand xxlorc => xxlnand xxleqv => xxlnand xxlnor => xxlnand xxlor => xxlnand xxlxor => xxlnand xxlandc => xxlnand xxland => xxlnand -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: meiss...@linux.ibm.com

Ping: PR 99293: Optimize splat of a V2DF/V2DI extract with constant element

Ping patch for PR target/99293 https://gcc.gnu.org/pipermail/gcc-patches/2025-May/683038.html -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: meiss...@linux.ibm.com

[PATCH] PR target/120528 -- Simplify zero extend from memory to VSX register on power10

the patches in this patch set applied on both little and big endian PowerPC systems and there were no regressions. Can I apply this patch to GCC 16? 2025-06-05 Michael Meissner gcc/ PR target/120528 * config/rs6000/rs6000.md (zero_extend??ti2 peephole2): Add a peephole2

[PATCH, V3] PR target/108958 -- simplify mtvsrdd to zero extend GPR DImode to VSX TImode

s. Can I apply this patch to GCC 16? 2025-06-05 Michael Meissner gcc/ PR target/108958 * config/rs6000/rs6000.md (UNSPEC_ZERO_EXTEND): New unspec. (zero_extendsiti2 peephole2): Add a peephole2 to simplify zero extend between DImode value in a GPR to a TImod

Re: Fix PR 118541 (V3), do not generate unordered fp cmoves for IEEE compares

On Thu, May 22, 2025 at 02:17:41PM +0530, Surya Kumari Jangala wrote: > Hi Mike, > The source code changes are missing. Whoops. I just posted a completely new patch. https://gcc.gnu.org/pipermail/gcc-patches/2025-May/685233.html -- Michael Meissner, IBM PO Box 98, Ayer, Massachusett

[PATCH, V7] Fix PR 118541, do not generate unordered fp cmoves for IEEE compares

Now if I compare my original patches to the original code, only one benchmark is faster: 526.blender_r: 1.0% faster I have done bootstrap builds on both little endian and big endian power servers. Can I check this patch into the GCC trunk? 2025-05-29 Michael Meissner gcc/ P

Re: Fix PR 118541, do not generate unordered fp cmoves for IEEE compares

I have posted a new version of the patch at: https://gcc.gnu.org/pipermail/gcc-patches/2025-May/684473.html -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: meiss...@linux.ibm.com

Re: Fix PR 118541 (V6 not V3), do not generate unordered fp cmoves for IEEE compares

I got the version number of the patch wrong. This patch is something like V6 of the patch, not V3. -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: meiss...@linux.ibm.com

Fix PR 118541 (V3), do not generate unordered fp cmoves for IEEE compares

here were no regressions. Can I check this patch into the GCC trunk, and after a waiting period, can I check this into the active older branches? 2025-05-21 Michael Meissner gcc/ PR target/118541 * config/rs6000/predicates.md (invert_fpmask_comparison_operator):

Re: Fix PR 118541, do not generate unordered fp cmoves for IEEE compares

her desires, I remove the test for Ofast. -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: meiss...@linux.ibm.com

PR 99293: Optimize splat of a V2DF/V2DI extract with constant element

endian power9): splat_dup_l_0: mfvsrld 9,34 mtvsrdd 34,9,9 blr Now it generates: splat_dup_l_0: xxpermdi 34,34,34,3 blr 2025-04-30 Michael Meissner gcc/ PR target/99293 * config

PR target/117251: Add PowerPC XXEVAL support to speed up SHA3 calculations

xxlnand => xxlnand xxlorc => xxlnand xxleqv => xxlnand xxlnor => xxlnand xxlor => xxlnand xxlxor => xxlnand xxlandc => xxlnand xxland => xxlnand 2025-04-30 Michael Meissner gcc/ PR target/117251 * confi

PR target/108958 -- use mtvsrdd to zero extend GPR DImode to VSX TImode

both little and big endian PowerPC systems and there were no regressions. Can I apply this patch to GCC 15? 2025-04-30 Michael Meissner gcc/ PR target/108598 * gcc/config/rs6000/rs6000.md (zero_extendditi2): New insn. gcc/testsuite/ PR target/108598 * gcc.t

Fix PR 118541, do not generate unordered fp cmoves for IEEE compares

power9/power10 systems and there were no regressions. Can I check this patch into the GCC trunk, and after a waiting period, can I check this into the active older branches? 2025-04-30 Michael Meissner gcc/ PR target/118541 * config/rs6000/predica

[PATCH, V5] PR target/118541 - Do not generate unordered fp cmoves for IEEE compares on PowerPC

built bootstrap compilers on big endian power9 systems and little endian power9/power10 systems and there were no regressions. Can I check this patch into the GCC trunk, and after a waiting period, can I check this into the active older branches? 2025-03-28 Michael Meissner gcc/

[PATCH, V6] PR target/118541 - Do not generate unordered fp cmoves for IEEE compares on PowerPC

ower10 systems and there were no regressions. Can I check this patch into the GCC trunk, and after a waiting period, can I check this into the active older branches? 2025-04-01 Michael Meissner gcc/ PR target/118541 * config/rs6000/predicates.md (invert_fpmask_comparison_operato

Re: [PATCH, V3] PR target/118541 - Do not generate unordered fp cmoves for IEEE compares on PowerPC

On Mon, Mar 24, 2025 at 09:15:26PM +0100, Florian Weimer wrote: > * Michael Meissner: > > > +enum reverse_cond_t { > > + REVERSE_COND_ORDERED_OK, > > + REVERSE_COND_NO_ORDERED > > +}; > > This should probably be something > like > > enum re

[PATCH, V4] PR target/118541 - Do not generate unordered fp cmoves for IEEE compares on PowerPC

ers on big endian power9 systems and little endian power9/power10 systems and there were no regressions. Can I check this patch into the GCC trunk, and after a waiting period, can I check this into the active older branches? 2025-03-26 Michael Meissner gcc/ PR target/118541 *

Re: [PATCH v2] rs6000: Adding missed ISA 3.0 atomic memory operation instructions.

amo6.c: Likewise. > * gcc.target/powerpc/amo7.c: Likewise. > > Co-authored-by: Jeevitha Palanisamy It looks reasonable to me. Hopefully Segher will approve. -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: meiss...@linux.ibm.com

Ping #4: [PATCH repost] PR target/117251 Add PowerPC XXEVAL support for fusion optimization in power10

. Message-ID https://gcc.gnu.org/pipermail/gcc-patches/2024-November/669138.html -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: meiss...@linux.ibm.com

Ping #2: [PATCH V2], Add PowerPC Dense Match Support for future cpus

.html Patch 3 of 3, add support for 1,024 bit dense math registers: https://gcc.gnu.org/pipermail/gcc-patches/2024-December/670792.html -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: meiss...@linux.ibm.com

Ping #2: [PATCH, V2] Add Vector pair support

.html -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: meiss...@linux.ibm.com

Ping #4: [PATCH report] PR target/99293 Optimize splat of a V2DF/V2DI extract with constant element

. Message-ID https://gcc.gnu.org/pipermail/gcc-patches/2024-November/669136.html -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: meiss...@linux.ibm.com

Ping #4: [PATCH V4 0/2] Separate PowerPC ISA bits from architecture bits set by -mcpu=

/gcc-patches/2024-November/669110.html -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: meiss...@linux.ibm.com

Ping #4: [PATCH] PR target/108958: Use mtvsrdd to zero extend GPR DImode to VSX TImode

https://gcc.gnu.org/pipermail/gcc-patches/2024-November/669242.html -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: meiss...@linux.ibm.com

Ping #4: [PATCH V4 0/5] Add more user friendly TARGET_ names for PowerPC

: https://gcc.gnu.org/pipermail/gcc-patches/2024-November/669072.html -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: meiss...@linux.ibm.com

Ping #4: [PATCH] PR target/117487 Add power9/power10 float to logical operations

://gcc.gnu.org/pipermail/gcc-patches/2024-November/669137.html -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: meiss...@linux.ibm.com

[PATCH, V3] PR target/118541 - Do not generate unordered fp cmoves for IEEE compares on PowerPC

fter a waiting period, can I check this into the active older branches? 2025-02-12 Michael Meissner gcc/ PR target/118541 * config/rs6000/predicates.md (invert_fpmask_comparison_operator): Do not allow UNLT and UNLE unless -ffast-math. * config/rs6000/rs6000-pr

Re: [PATCH, V2] Fix PR 118541, do not generate unordered fp cmoves for IEEE compares.

On Fri, Feb 07, 2025 at 05:51:19PM -0600, Peter Bergner wrote: > On 2/7/25 4:02 PM, Michael Meissner wrote: > > (define_predicate "invert_fpmask_comparison_operator" > > - (match_code "ne,unlt,unle")) > > + (ior (match_code "ne") > > +

Re: [PATCH, V2] Fix PR 118541, do not generate unordered fp cmoves for IEEE compares.

On Fri, Feb 07, 2025 at 05:51:19PM -0600, Peter Bergner wrote: > On 2/7/25 4:02 PM, Michael Meissner wrote: > > (define_predicate "invert_fpmask_comparison_operator" > > - (match_code "ne,unlt,unle")) > > + (ior (match_code "ne") > > +

[PATCH, V2] Fix PR 118541, do not generate unordered fp cmoves for IEEE compares.

red_compare: fcmpu 0,1,2 fmr 1,4 bnglr 0 fmr 1,3 blr normal_compare: xscmpgtdp 1,1,2 xxsel 1,4,3,1 blr 2025-02-06 Michael Meissner gcc/ PR target/118541 * co

Re: [PATCH] Fix PR 118541, do not generate unordered fp cmoves for IEEE compares.

s unless they use -fsignaling-nans, but if the user explicitly uses isgreater which says it does not trap, we should generate code that will trap in some case. Normal code using '>', etc. will only generate GT, GE, etc. and it will generate the cmove. -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: meiss...@linux.ibm.com

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