This patch fix the wrong condition for RVVMF2BF. It should be
TARGET_VECTOR_ELEN_BF_16.
gcc/ChangeLog:
PR target/117669
* config/riscv/vector-iterators.md:
Signed-off-by: Feng Wang
---
gcc/config/riscv/vector-iterators.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion
This patch fix the wrong condition for RVVMF2BF. It should be
TARGET_VECTOR_ELEN_BF_16.
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Modify condition.
Signed-off-by: Feng Wang
---
gcc/config/riscv/vector-iterators.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
/ChangeLog:
* gcc.target/riscv/rvv/autovec/vfncvt-auto-vect.c: New test.
* gcc.target/riscv/rvv/autovec/vfwcvt-auto-vect.c: New test.
* gcc.target/riscv/rvv/autovec/vfwmacc-auto-vect.c: New test.
Signed-off-by: Feng Wang
---
gcc/config/riscv/autovec-opt.md
-vect.c: New test.
Signed-off-by: Feng Wang
---
gcc/config/riscv/vector-bfloat16.md | 144 --
.../riscv/rvv/autovec/vfncvt-auto-vect.c | 19 +++
.../riscv/rvv/autovec/vfwcvt-auto-vect.c | 19 +++
.../riscv/rvv/autovec/vfwmacc-auto-vect.c | 14 ++
4 files
/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vrolr-1.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vrolr-run.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vrolr-template.h: New test.
Signed-off-by: Feng Wang
---
gcc/config/riscv/autovec.md | 16
This patch add the vector rotate shift pattern for auto-vect.
With this patch, the scalar rotate shift can be automatically
vectorized into vector rotate shift.
signed-off-by: Feng Wang
gcc/ChangeLog:
* config/riscv/autovec-opt.md (v3):
Add define_expand for vector
V3: Add Bfloat16 vector insn in generic-vector-ooo.md
v2: Rebase
Accroding to the BFloat16 spec, some vector iterators and new pattern
are added in md files.
Signed-off-by: Feng Wang
gcc/ChangeLog:
* config/riscv/generic-vector-ooo.md: Add def_insn_reservation for
vector BFloat16
v3: Modify warning message in riscv.cc
v2: Rebase
Accroding to the intrinsic doc, the 'Zvfbfmin' and 'Zvfbfwma' intrinsic
functions are added by this patch.
Signed-off-by: Feng Wang
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc (class vfncvtbf16
v3: Rebase
v2: Rebase
The vector type of BFloat16 format is added in this patch,
subsequent extensions to zvfbfmin and zvfwma need to be based
on this patch.
Signed-off-by: Feng Wang
gcc/ChangeLog:
* config/riscv/genrvv-type-indexer.cc (bfloat16_type):
Generate bf16
v2: Rebase.
The vector type of BFloat16 format is added in this patch,
subsequent extensions to zvfbfmin and zvfwma need to be based
on this patch.
gcc/ChangeLog:
* config/riscv/genrvv-type-indexer.cc (bfloat16_type):
Generate bf16 vector_type and scalar_type in DEF_RVV_TYPE_I
v2:Rebase.
Accroding to the BFloat16 spec, some vector iterators and new pattern
are added in md files.
gcc/ChangeLog:
* config/riscv/riscv.md: Add new insn name for vector BFloat16.
* config/riscv/vector-iterators.md: Add some iterators for vector
BFloat16.
* config/risc
v2: Rebase.
Accroding to the intrinsic doc, the 'Zvfbfmin' and 'Zvfbfwma' intrinsic
functions are added by this patch.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc (class vfncvtbf16_f):
Add 'Zvfbfmin' intrinsic in bases.
(class vfwcvtbf16_f): Ditto.
The vector type of BFloat16 format is added in this patch,
subsequent extensions to zvfbfmin and zvfwma need to be based
on this patch.
gcc/ChangeLog:
* config/riscv/genrvv-type-indexer.cc (bfloat16_type):
Generate bf16 vector_type and scalar_type in DEF_RVV_TYPE_INDEX.
Accroding to the BFloat16 spec, some vector iterators and new pattern
are added in md files.
All these changes passed the rvv test and rvv-intrinsic test for bfloat16.
gcc/ChangeLog:
* config/riscv/riscv.md: Add new insn name for vector BFloat16.
* config/riscv/vector-iterators.m
Accroding to the intrinsic doc, the 'Zvfbfmin' and 'Zvfbfwma' intrinsic
functions are added by this patch.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc (class vfncvtbf16_f):
Add 'Zvfbfmin' intrinsic in bases.
(class vfwcvtbf16_f): Ditto.
(class
Committed, thanks.
From: juzhe.zh...@rivai.ai
Date: 2024-01-12 09:38
To: wangfeng; gcc-patches
CC: kito.cheng; jeffreyalaw; wangfeng
Subject: Re: [PATCH] RISC-V: Modify ABI-name length of vfloat16m8_t
Good catch. LGTM.
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2024-01-12 09:35
To: gcc
The length of vfloat16m8_t ABI-name should be 17.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.def (vfloat16m8_t):Modify ABI-name
length of vfloat16m8_t
---
gcc/config/riscv/riscv-vector-builtins.def | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/r
Committed, thanks Juzhe.
发件人： 钟居哲
发送时间： 2024-01-09 07:02
收件人： wangfeng; gcc-patches
抄送： kito.cheng; Jeff Law; wangfeng
主题： Re: [PATCH v7 1/2] RISC-V: Add crypto vector builtin function.
LGTM.
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2024-01-08 17:12
To: gcc-patches
CC: kito.cheng
Committed, thanks Juzhe.
发件人： 钟居哲
发送时间： 2024-01-09 07:02
收件人： wangfeng; gcc-patches
抄送： kito.cheng; Jeff Law; wangfeng
主题： Re: [PATCH v8 2/2] RISC-V: Add crypto vector api-testing cases.
LGTM.
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2024-01-08 17:12
To: gcc-patches
CC: kito.cheng
Patch v7:Resubmit after fix trl-checking issue. Passed all the riscv regression
test.
Patch v6:Remove unused code.
Patch v5:Rebase.
Patch v4:Merge crypto vector function.def into vector.
Patch v3:Define a shape for vaesz and merge vector-crypto-types.def
into riscv-vector-builtins-types.d
Patch v8: Resubmit after fix the rtl-checking issue. Passed all the riscv
regression test.
Patch v7: Add newline at the end of file.
Patch v6: Move intrinsic tests into rvv/base.
Patch v5: Rebase
Patch v4: Add some RV32 vx constraint testcase.
Patch v3: Refine crypto vector api-testing cases.
Patc
This patch fix the rtl-checking error for crypto vector. The root
cause is the avl-type index of zvbc ins is error,it should be operand[8]
not operand[5].
gcc/ChangeLog:
* config/riscv/vector.md: Modify avl_type operand index of zvbc ins.
---
gcc/config/riscv/vector.md | 4 ++--
1 file ch
This patch fix the rtl-checking error for crypto vector. The root
cause is the avl-type index of zvbc ins is error,it should be operand[8]
not operand[5].
gcc/ChangeLog:
* config/riscv/vector.md: Modify avl_type operand index of zvbc ins.
---
gcc/config/riscv/vector.md | 4 ++--
1 file ch
s
>of vclmul and vclmulh instructions".
>
>
>
>juzhe.zh...@rivai.ai
>
OK. Will separate it.
>From: Feng Wang
>Date: 2024-01-05 16:51
>To: gcc-patches
>CC: kito.cheng; jeffreyalaw; juzhe.zhong; Feng Wang
>Subject: [PATCH v7 1/2] RISC-
Patch v7:Fix avl_type operand index of zvbc ins.
Patch v6:Remove unused code.
Patch v5:Rebase.
Patch v4:Merge crypto vector function.def into vector.
Patch v3:Define a shape for vaesz and merge vector-crypto-types.def
into riscv-vector-builtins-types.def.
Patch v2:Optimize function_shape c
Yes, as Juzhe said I had run all the riscv regression, but without RTL check.
I will fix it.
Sorry for forgetting to enable RTL checking for testing.
Thanks Juzhe for helping me reverse this commit.
From: juzhe.zh...@rivai.ai
Date: 2024-01-05 11:28
To: palmer
CC: gcc-patches; kito.cheng; Kito.c
This patch add crypto vector api-testing cases based on
https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/eopc/vector-crypto/auto-generated/vector-crypto
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvbb-intrinsic.c: New test.
* gcc.target/riscv/rvv/base/zvbb_vandn_vx
This patch add the intrinsic funtions of crypto vector based on the
intrinsic doc(https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob
/eopc/vector-crypto/auto-generated/vector-crypto/intrinsic_funcs.md).
Co-Authored by: Songhe Zhu
Co-Authored by: Ciyan Pan
gcc/ChangeLog:
* config/ri
Patch v7: Add newline at the end of file.
Patch v6: Move intrinsic tests into rvv/base.
Patch v5: Rebase
Patch v4: Add some RV32 vx constraint testcase.
Patch v3: Refine crypto vector api-testing cases.
Patch v2: Update march info according to the change of riscv-common.c
This patch add crypto vec
Patch v6: Move intrinsic tests into rvv/base.
Patch v5: Rebase
Patch v4: Add some RV32 vx constraint testcase.
Patch v3: Refine crypto vector api-testing cases.
Patch v2: Update march info according to the change of riscv-common.c
This patch add crypto vector api-testing cases based on
https://git
2024-01-03 00:32 Jeff Law wrote:
>
>
>On 1/1/24 19:25, Feng Wang wrote:
>> gcc/ChangeLog:
>> * config/riscv/vector-crypto.md: Modify copyright year.
>> ---
>> gcc/config/riscv/vector-crypto.md | 2 +-
>> 1 file changed, 1 insertion(+),
Patch v6:Remove unused code.
Patch v5:Rebase.
Patch v4:Merge crypto vector function.def into vector.
Patch v3:Define a shape for vaesz and merge vector-crypto-types.def
into riscv-vector-builtins-types.def.
Patch v2:Optimize function_shape class for crypto_vector.
This patch add the intri
int (*avail) (void);
>+};
>
>What is this used for ?
Will delete it.
>
>
>juzhe.zh...@rivai.ai
>
>From: Feng Wang
>Date: 2024-01-02 15:47
>To: gcc-patches
>CC: kito.cheng; jeffreyalaw; juzhe.zhong; Feng Wang
>Subject: [PATCH v5 1/2] RISC-V: Add crypto vector
Patch v5: Rebase.
Patch v4: Add some RV32 vx constraint testcase.
Patch v3: Refine crypto vector api-testing case s.
Patch v2: Update march info according to the change of riscv-common.c
This patch add crypto vector api-testing cases based on
https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob
Patch v5:Rebase.
Patch v4:Merge crypto vector function.def into vector.
Patch v3:Define a shape for vaesz and merge vector-crypto-types.def
into riscv-vector-builtins-types.def.
Patch v2:Optimize function_shape class for crypto_vector.
This patch add the intrinsic funtions of crypto vecto
gcc/ChangeLog:
* config/riscv/vector-crypto.md: Modify copyright year.
---
gcc/config/riscv/vector-crypto.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/riscv/vector-crypto.md
b/gcc/config/riscv/vector-crypto.md
index e40b1543954..9625014e45e 100755
---
Co-Authored by: Songhe Zhu
Co-Authored by: Ciyan Pan
gcc/ChangeLog:
* config/riscv/iterators.md: Add rotate insn name.
* config/riscv/riscv.md: Add new insns name for crypto vector.
* config/riscv/vector-iterators.md: Add new iterators for crypto vector.
* config/
2023-12-22 09:59 Feng Wang wrote:
Sorry for forgetting to add the patch version number. It should be [PATCH v8
2/3]
>Patch v8: Remove unused iterator and add newline at the end.
>Patch v7: Remove mode of const_int_operand and typo. Add
> newline at the end and comme
Patch v8: Remove unused iterator and add newline at the end.
Patch v7: Remove mode of const_int_operand and typo. Add
newline at the end and comment at the beginning.
Patch v6: Swap the operator order of vandn.vv
Patch v5: Add vec_duplicate operator.
Patch v4: Add process of SEW=64 in RV3
Patch v7: Remove mode of const_int_operand and typo. Add
newline at the end and comment at the beginning.
Patch v6: Swap the operator order of vandn.vv
Patch v5: Add vec_duplicate operator.
Patch v4: Add process of SEW=64 in RV32 system.
Patch v3: Moidfy constrains for crypto vector.
Patc
Patch v6: Swap the operator order of vandn.vv.Make report riscv.exp with
"riscv-sim/-march=rv64gc/-mabi=lp64d/-mcmodel=medlow" is passed.
Patch v5: Add vec_duplicate operator.
Patch v4: Add process of SEW=64 in RV32 system.
Patch v3: Moidfy constrains for crypto vector.
Patch v2: Add crypto vecto
Patch v5: Add vec_duplicate operator. Make report riscv.exp with
"riscv-sim/-march=rv64gc/-mabi=lp64d/-mcmodel=medlow" is passed.
Patch v4: Add process of SEW=64 in RV32 system.
Patch v3: Moidfy constrains for crypto vector.
Patch v2: Add crypto vector ins into RATIO attr and use vr as
destinatio
2023-12-20 15:12 juzhe.zhong wrote:
>+ (and:VI
>+ (match_operand:VI 3 "register_operand" "vr, vr, vr, vr")
>+ (not:VI (match_operand:VI 4 "register_operand" "vr, vr, vr, vr")))
>Swap the order:
>
>(not:VI (match_operand:VI 4 "register_operand" "vr, vr, vr, vr")
>
Patch v4: Add some RV32 vx constraint testcase.
Patch v3: Refine crypto vector api-testing cases.
Patch v2: Update march info according to the change of riscv-common.c
This patch add crypto vector api-testing cases based on
https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/eopc/vector-crypto
Patch v4: Add process of SEW=64 in RV32 system.
Patch v3: Moidfy constrains for crypto vector.
Patch v2: Add crypto vector ins into RATIO attr and use vr as
destination register.
This patch add the crypto machine descriptions(vector-crypto.md) and
some new iterators which are used by crypto vector
Patch v4:Merge crypto vector function.def into vector.
Patch v3:Define a shape for vaesz and merge vector-crypto-types.def
into riscv-vector-builtins-types.def.
Patch v2:Optimize function_shape class for crypto_vector.
This patch add the intrinsic funtions of crypto vector based on the
in
In order to add other vector related extensions in the future, this
patch add one more parameter in the function_group_info, it will be
used to determine whether intrinsic registration processing is required.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-functions.def
(REQUIRED_EXT
In order to add other vector related extensions in the future, this
patch add one more parameter in the function_group_info, it will be
used to determine whether intrinsic registration processing is required.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-functions.def
(REQUIRED_EXT
This reverts commit ce7e66787b5b4ad385b21756da5a89171d233ddc.
Will refactor this part in the same way as aarch64 sve.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-functions.def (DEF_RVV_FUNCTION):
Revert changes.
This reverts commit ce7e66787b5b4ad385b21756da5a89171d233ddc.
Will refactor this part in the same way as aarch64 sve.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-functions.def (DEF_RVV_FUNCTION):
Revert changes.
Due to the crypto vector entension is depend on the Vector extension,
so add the implied ISA info with the corresponding crypto vector extension.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Modify implied ISA info.
* config/riscv/arch-canonicalize: Add crypto vector impl
tions.def"
>+};
>Why do you add this ? I think it should belong to function_groups.
The original intention of this modification was to make the processing flow of
the crypto vector more clearer.
If you think it should merge into V extension, I will do it.
Thanks.
Feng Wang
>
>+ /*
Patch v3: Refine crypto vector api-testing cases.
Patch v2: Update march info according to the change of riscv-common.c
This patch add crypto vector api-testing cases based on
https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/eopc/vector-crypto/auto-generated/vector-crypto
gcc/testsuite/Cha
Patch v3: Moidfy constrains for crypto vector.
Patch v2: Add crypto vector ins into RATIO attr and use vr as
destination register.
This patch add the crypto machine descriptions(vector-crypto.md) and
some new iterators which are used by crypto vector ext.
Co-Authored by: Songhe Zhu
Co-Authored b
Patch v3:Define a shape for vaesz and merge vector-crypto-types.def
into riscv-vector-builtins-types.def.
Patch v2:Optimize function_shape class for crypto_vector.
This patch add the intrinsic funtions of crypto vector based on the
intrinsic doc(https://github.com/riscv-non-isa/rvv-intrin
Patch v2: Change the implied ISA info using the minimum set and add
dependencies info into the python script.
Due to the crypto vector entension is depend on the Vector extension,
so the "v" info is added into implied ISA info with the corresponding
crypto vector extension.
gcc/ChangeLog:
Ville Voutilainen
Nenad Vukicevic
Feng Wang
-Feng Wang s
+Feng Wang
Hongyu Wang
Patch v3: Fix typo and remove the modification of rvv.exp.
Patch v2: Using variadic macro and add the dependency into t-riscv.
In order to add other extension about vector,this patch add
unsigned int (*avail) (void) into function_group_info to determine
whether to register the intrinsic based on I
Ville Voutilainen
Nenad Vukicevic
Feng Wang
+Feng Wang s
Hongyu Wang
Jiong Wang
2023-12-11 13:05 Kito Cheng wrote:
>I am happy with this change now, however I didn't see any place call avail
>function yet? Do I miss something? Are you planning to send follow up
>patches to add that?
>If so, LGTM.
Yes, the crypto vector will determine whether to register the corre
Patch v3: Fix typo and remove the modification of rvv.exp.
Patch v2: Using variadic macro and add the dependency into t-riscv.
In order to add other extension about vector,this patch add
unsigned int (*avail) (void) into function_group_info to determine
whether to register the intrinsic based on I
2023-12-08 11:35 Kito Cheng wrote:
>> Without comma, there is a warning "warning: ISO C++11 requires at least one
>> argument for the "..." in a variadic macro".
>> So I add the comma.
>
>Oh, thanks, I wasn't aware that, maybe take one more argument to '...'
>
>#define DEF_RVV_FUNCTION(NAME, S
2023-12-08 11:18 Kito Cheng wrote:
>> @@ -31,624 +31,627 @@ along with GCC; see the file COPYING3. If not see
>> - OPS_INFO describes all information of return type and each
>> argument type.
>>
>> + - AVAIL this argument is the optional for AVAIL.Determin the enab
2023-12-08 10:44 Feng Wang wrote:
Have run all the vector api-testing.
>Patch v2: Using variadic macro and add the dependency into t-riscv
>
>In order to add other extension about vector,this patch add
>unsigned int (*avail) (void) into function_group_info to determine
Patch v2: Using variadic macro and add the dependency into t-riscv
In order to add other extension about vector,this patch add
unsigned int (*avail) (void) into function_group_info to determine
whether to register the intrinsic based on ISA info.
gcc/ChangeLog:
* config/riscv/riscv-vecto
gt;Btw, we have full coverage rvv -intrinsic API testing generator for GNU .
>https://github.com/riscv-non-isa/rvv-intrinsic-doc/
>Could you run it ? Your colleague Lixu knows it.
>
OK. got it, I will run it. Thanks.
>
>
>
>juzhe.zh...@rivai.ai
>
In order to add other extension about vector,this patch add
unsigned int (*avail) (void) into function_group_info to determine
whether to register the intrinsic based on ISA info.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-functions.def (DEF_RVV_FUNCTION):
Add AVAIL def.
.
For current vector intrinsics:
DEF_RVV_FUNCTION (vlsegff, seg_fault_load, full_preds,
tuple_v_scalar_const_ptr_size_ptr_ops)
change it into:
DEF_RVV_FUNCTION (vlsegff, seg_fault_load, full_preds,
tuple_v_scalar_const_ptr_size_ptr_ops, true)
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2023
Patch v2:Optimize function_shape class for crypto_vector.
This patch add the intrinsic funtions of crypto vector based on the
intrinsic doc(https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob
/eopc/vector-crypto/auto-generated/vector-crypto/intrinsic_funcs.md).
Co-Authored by: Songhe Zhu
Co-
Patch v2: Add crypto vector ins into RATIO attr and use vr as
destination register.
This patch add the crypto machine descriptions(vector-crypto.md) and
some new iterators which are used by crypto vector ext.
Co-Authored by: Songhe Zhu
Co-Authored by: Ciyan Pan
gcc/ChangeLog:
* config
Patch v2: Change the implied ISA info using the minimum set and add
dependencies info into the python script.
Due to the crypto vector entension is depend on the Vector extension,
so the "v" info is added into implied ISA info with the corresponding
crypto vector extension.
gcc/ChangeLog:
2023-12-06 11:33 Tsukasa OI wrote:
>On 2023/12/06 11:45, Feng Wang wrote:
>> Due to the crypto vector entension is depend on the Vector extension,
>> so the "v" info is added into implied ISA info with the corresponding
>> crypto vector extension.
&g
destination EEW is greater than the source EEW, the source
>EMUL is at least 1,
> ;; and the overlap is in the highest-numbered part of the destination
>register group
> ;; (e.g., when LMUL=8, vzext.vf4 v0, v6 is legal, but a source of v0,
>v2, or v4 is no
This patch add the crypto machine descriptions(vector-crypto.md) and
some new iterators which are used by crypto vector ext.
Co-Authored by: Songhe Zhu
Co-Authored by: Ciyan Pan
gcc/ChangeLog:
* config/riscv/iterators.md: Add rotate insn name.
* config/riscv/riscv.md: Add new i
This patch add the intrinsic funtions of crypto vector based on the
intrinsic doc(https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob
/eopc/vector-crypto/auto-generated/vector-crypto/intrinsic_funcs.md).
Co-Authored by: Songhe Zhu
Co-Authored by: Ciyan Pan
gcc/ChangeLog:
* config/r
Due to the crypto vector entension is depend on the Vector extension,
so the "v" info is added into implied ISA info with the corresponding
crypto vector extension.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add "v" into implied ISA info.
---
gcc/common/config/riscv/riscv-comm
nspec" [
>> + ;; Zvbb unspecs
>> + UNSPEC_VANDN
>> + UNSPEC_VBREV
>> + UNSPEC_VBREV8
>> + UNSPEC_VREV8
>> + UNSPEC_VCLZ
>> + UNSPEC_VCTZ
>> + UNSPEC_VROL
>> + UNSPEC_VROR
>> + UNSPEC_VWSLL
>> +])
>
>Could you use generic RTL code for andn, clz, ctl, rol, ror and wsll
>rather than unspec?
Got it! will optimize it., thanks!
Feng Wang
Rebase and resend this patch due to it was not added into patchwork
before. Kito had already reviewed it. Please refer to
https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg327499.html
This patch add the Zvkb subset of crypto vector extension. The
corresponding test cases have aslo been modif
2023-12-04 11:37 juzhe.zhong wrote:
Will split again as you mentioned. Thanks.
Feng Wang
>Hi, eswin.
>
>Thanks for contributing vector crypto support.
>
>It seems patches mess up. Could you rebase your patch to the trunk GCC cleanly
>and send it again.
>
This patch add the intrinsic functions(according to https://github.com/
riscv-non-isa/rvv-intrinsic-doc/blob/eopc/vector-crypto/auto-generated/
vector-crypto/intrinsic_funcs.md) for crypto vector Zvksh extension. And all
the test cases are added for api-testing.
Co-Authored by: Songhe Zhu
gcc/Ch
This patch add the intrinsic functions(according to https://github.com/
riscv-non-isa/rvv-intrinsic-doc/blob/eopc/vector-crypto/auto-generated/
vector-crypto/intrinsic_funcs.md) for crypto vector Zvknh[ab] extension. And all
the test cases are added for api-testing.
Co-Authored by: Songhe Zhu
gc
This patch add the intrinsic functions(according to https://github.com/
riscv-non-isa/rvv-intrinsic-doc/blob/eopc/vector-crypto/auto-generated/
vector-crypto/intrinsic_funcs.md) for crypto vector Zvksed extension. And all
the test cases are added for api-testing.
gcc/ChangeLog:
* common/c
This patch add the intrinsic functions(according to https://github.com/
riscv-non-isa/rvv-intrinsic-doc/blob/eopc/vector-crypto/auto-generated/
vector-crypto/intrinsic_funcs.md) for crypto vector Zvkned extension. And all
the test cases are added for api-testing.
gcc/ChangeLog:
* common/c
This patch add the intrinsic functions(according to https://github.com/
riscv-non-isa/rvv-intrinsic-doc/blob/eopc/vector-crypto/auto-generated/
vector-crypto/intrinsic_funcs.md) for crypto vector Zvkg extension. And all
the test cases are added for api-testing.
Co-Authored by: Songhe Zhu
Co-Autho
This patch add the intrinsic functions(according to https://github.com/
riscv-non-isa/rvv-intrinsic-doc/blob/eopc/vector-crypto/auto-generated/
vector-crypto/intrinsic_funcs.md) for crypto vector Zvbc extension. And all
the test cases are added for api-testing.
Co-Authored by: Songhe Zhu
gcc/Cha
This patch add the Zvkb subset of crypto vector extension. The
corresponding test cases have aslo been modified.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add zvkb ISA info.
* config/riscv/riscv.opt: Add Mask(ZVKB)
gcc/testsuite/ChangeLog:
* gcc.target/riscv/
On 2023-11-28 11:06 Andrew Pinski wrote:
>On Mon, Nov 27, 2023 at 6:56 PM Feng Wang wrote:
>>
>> The link of PATCH v1:
>> https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg326661.html
>> This patch add another condition for gimple-cond optimization. Refer to
The link of PATCH v1:
https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg326661.html
This patch add another condition for gimple-cond optimization. Refer to
the following test case.
int foo1 (int data, int res)
{
res = data & 0xf;
res |= res << 4;
if (res < 0x22)
return 0x22;
retu
On 2023-11-23 14:34 Andrew Pinski wrote:
>
>On Wed, Nov 22, 2023 at 10:07 PM Feng Wang wrote:
>>
>> This patch add another condition for gimple-cond optimization. Refer to
>> the following test case.
>> int foo1 (int data, int res)
>> {
This patch add another condition for gimple-cond optimization. Refer to
the following test case.
int foo1 (int data, int res)
{
res = data & 0xf;
res |= res << 4;
if (res < 0x22)
return 0x22;
return res;
}
with the compilation flag "-march=rv64gc_zba_zbb -mabi=lp64d -O2",
before this pa
lems.
Thank you again!
------
Feng Wang
>Proposed fix, and verified with "mawk" and "gawk -P" (gawk with posix
>mode) on my linux also some other report it work on freebsd, just wait
>review :)
>
>https://gcc.gnu.org/pipermail/gcc-patches/2023-October/631785
New patch add some comments and update docs for this new usage.
---
Accoring to Kito's advice, using "MASK(name) Var(other_flag_name)"
to generate MASK and TARGET MACRO automatically.
This patch improve the MACRO generation of MASK_* and TARGET_*.
Due to the more and more riscv extensions are added
Accoring to Kito's advice, using "MASK(name) Var(other_flag_name)"
to generate MASK and TARGET MACRO automatically.
This patch improve the MACRO generation of MASK_* and TARGET_*.
Due to the more and more riscv extensions are added, the default target_flag
is full.
Before this patch,if you want to
This patch rebases the change of "[PATCH] RISC-V: Optimize the MASK opt
generation" and add the new explanation in the options.texi.
gcc/ChangeLog:
* config/riscv/riscv-opts.h (MASK_ZICSR):
(MASK_ZIFENCEI): Delete;
(MASK_ZIHINTNTL):Ditto;
(MASK_ZIHINTPAUSE):
Thanks reminder, I should rebase again.
--
Feng Wang
>Hi,
>
>I will need to notify you that x_riscv_xventana_subext,
>MASK_XVENTANACONDOPS and TARGET_XVENTANACONDOPS are added (I think you
>want to rewrite those definitions like the rest). Also, be careful
nd
TARGET Macro?
I think it will change a lot of code and the original meaning is changed.
--
Feng Wang
>Reading the manual again, it seems I missed something in the manual
>before, the MASK syntax already says we can specify Var to select the
>variable other than target_flags, b
This patch rebases the change of "[PATCH] RISC-V: Optimize the MASK opt
generation" and add the new explanation in the options.texi.
Please check the detail info on the
"https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg302295.html";
gcc/ChangeLog:
* config/riscv/riscv-opts.h (MASK_Z
This patch rebases the change of "[PATCH] RISC-V: Optimize the MASK opt
generation". Please check the detail info on the
"https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg302295.html";
gcc/ChangeLog:
* config/riscv/riscv-opts.h (MASK_ZICSR):
(MASK_ZIFENCEI): Delete;
Ping, I will rebase if the change is fine to you, thanks!
On 2023-03-01 09:46 Feng Wang wrote:
>
>The Mask flag in the single TargetVariable is not enough due to more
>and more extensions were added.So I optimize the defination of Mask
>flag, please refer to the below case:
>The
On 2023-03-01 09:46 Feng Wang wrote:
>
>The Mask flag in the single TargetVariable is not enough due to more
>and more extensions were added.So I optimize the defination of Mask
>flag, please refer to the below case:
>There are some new MASK flags for 'v' extension(ZV
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