When there are enough registers, the register pressure cost is
unnecessarily bumped by adding another n_cands.
This behavior may result in register pressure costs for the case
when there are enough registers being higher than for other cases.
When there are enough registers, the register pressure
Architectures like Mips are very limited when it comes to addressing modes.
Therefore, the expected
behavior would be that, for the BASE + OFFSET addressing mode, complexity is
lower, while, for more
complex addressing modes (e.g. BASE + INDEX << SCALE), which are not supported,
complexity is
hi
After f9f69dd, complexity is calculated using the
valid_mem_ref_p target hook. Architectures like Mips only
allow BASE + OFFSET addressing modes, which in turn prevents
the calculation of complexity for other addressing modes,
resulting in non-optimal candidate selection.
There still is code that