On Mon, 2025-09-08 at 14:52 +0530, Avinash Jayakar wrote:
> Hi,
>
> This is the third version of the patch proposed for master aiming to
> fix
> PR119702. Requesting review of this patch.
>
> The following sequence of assembly in powerpc64le
> vspltisw 0,1
>
patch, or should I follow it up with this patch like
[PATCH v2 1/3] and so on.
Thanks and regards,
Avinash Jayakar
Changes from v1:
- Added new tests for checking vectorization of FLOOR_{DIV.MOD}
for multiple paths.
- Incorporated review comments to use proper vector masks
Hi,
Below is a patch for fixing PR121700 proposed for master. Kindly review.
Regtesting on powerpc64le is still running. Will update the status soon in this
thread.
Thank you,
Avinash Jayakar
rs6000: Update scalar cost of {TRUNC,FLOOR}_MOD_EXPR[PR121700]
The default cost model with O2 flag is
Hi,
Following is version 5 of the patch proposed for master to fix PR119702.
This patch has been bootstrapped and regtested on powerpc64le-linux.
Kindly review the patch.
Thanks and regards,
Avinash Jayakar
Changes from v4:
1. Added comments for the new predicate "vector_const
Hi Surya,
Apologies for the late response. This patch has been bootstrapped and
regtested for powerpc64le with no new failures.
Thanks and regards,
Avinash Jayakar
On Mon, 2025-09-15 at 22:22 +0530, Surya Kumari Jangala wrote:
> Hi Avinash,
> Patches should be posted for review only
Hello Richard,
Thank you for reviewing the patch! I have made changes based on your
comments, but I have some doubts for a few comments as mentioned below.
On Thu, 2025-09-11 at 13:08 +0200, Richard Biener wrote:
> On Wed, 10 Sep 2025, Avinash Jayakar wrote:
> > + bool unsignedp = TYPE
Hi,
Following is version 4 of the patch proposed for master to fix PR119702.
This patch has been bootstrapped and regtested on powerpc64le-linux.
Kindly review the patch.
Thanks and regards,
Avinash Jayakar
Changes from v3:
1. Add author information before changelog.
2. Right
Hi,
The following patch implements the vectorization logic for FLOOR_MOD_EXPR and
FLOOR_DIV_EXPR. According to the logic mentioned in the PR, we have
For signed operands,
r = x %[fl] y;
FYI, this patch has been bootstrapped and regtested on powerpc64le-
linux.
Hi,
This is the third version of the patch proposed for master aiming to fix
PR119702. Requesting review of this patch.
The following sequence of assembly in powerpc64le
vspltisw 0,1
vsld 2,2,0
is replaced by this
vaddudm 2,2,2
whenever there is a vector left shift by a c
Hi,
This is the third version of the patch proposed for master aiming to fix
PR119702. Requesting review of this patch.
The following sequence of assembly in powerpc64le
vspltisw 0,1
vsld 2,2,0
is replaced by this
vaddudm 2,2,2
whenever there is a vector left shift by a c
Hello,
This is the second version of the patch proposed for master aiming to fix
PR119702. I request the review of this patch.
The following sequence of assembly in powerpc64le
vspltisw 0,1
vsld 2,2,0
is replaced by this
vaddudm 2,2,2
whenever there is a vector left shi
a vector operand of all 1's in
predicate.md
+(define_predicate "shift_constant_1"
+ (match_code "const_vector")
+{
+ unsigned nunits = GET_MODE_NUNITS (mode), i;
+ for (i = 1; i < nunits; i++) {
+if (INTVAL (CONST_VECTOR_ELT(op, i)) != 1)
+ return 0;
+ }
+ return 1;
+})
+
Actually this particular node is a vector constant, so we need to check
if all its elements are 1. Please correct me if I am wrong, but I
believe the const1_rtx does not work for vectors?
Thanks and regards,
Avinash Jayakar
; is
initialized with "default_target_expmed", where these costs are
defined.
Ideally in case of powerpc and in vector mode, the shift_cost should be
more than add_cost right, since we need to first splat the constant
operand into a register and then do the shift. I think this cost is not
accounted for.
Thank you,
Avinash Jayakar
operands[1],
+operands[2])));
+DONE;
+ }
+})
This way it is easy to recognize in define_insn as follows
diff --git a/gcc/config/rs6000/altivec.md
b/gcc/config/rs6000/altivec.md
index 7edc288a656..3f678f2e666 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -2107,6 +2107,17 @@
"vsrv %0,%1,%2"
[(set_attr "type" "vecsimple")])
+
+(define_insn ""
+ [(set (match_operand:VI2 0 "register_operand" "=v")
+ (ashift:VI2 (match_operand:VI2 1 "register_operand" "v")
+ (const_vector:V2DI [(const_int 1) (const_int
1)])))]
+ ""
+ {
+return "vaddum %0,%1,%1";
+ }
+)
+
As you mentioned I will have to add patterns for various sizes as well.
Regards,
Avinash Jayakar
Ping. Requesting review of this patch.
Thank you,
Avinash Jayakar
On Thu, 2025-08-21 at 19:54 +0530, Avinash Jayakar wrote:
> On Thu, 2025-08-14 at 11:27 +0530, Avinash Jayakar wrote:
> > PR119702
> Ping 1. Request review of this patch.
>
> Thanks and regards,
> Avinash
On Thu, 2025-08-14 at 11:27 +0530, Avinash Jayakar wrote:
> PR119702
Ping 1. Request review of this patch.
Thanks and regards,
Avinash
2025-08-12 Avinash Jayakar
* MAINTAINERS: Add myself to write after approval.
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index dd31eed0251..07359c5d7ee 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -566,6 +566,7 @@ Fariborz Jahanian
generate ashift op.
2025-08-13 Avinash Jayakar
PR target/119702
gcc:
* config/rs6000/vector.md (vashl3): Generate add when
operand 2 is a constant with value 1.
gcc/testsuite:
* gcc.target/powerpc/pr119702-1.c: New test (for
checking generation of add for
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