On Tue, 2024-12-31 at 17:00 +, Jiaxun Yang wrote:
>
> 在2024年12月31日十二月 下午4:56，Jiaxun Yang写道：
> > As per architecture, SuperH has a reversed NaN signalling bit
> > vs IEEE754-2008, it also has a NaN propgation rule similar to
> > MIPS style.
>
> Oops, please don't apply this version, it seems l
gcc/fortran/ChangeLog
* gfortran.texi (Function ABI Documentation): Make menu ordering
consistent with subsection ordering.
---
gcc/fortran/gfortran.texi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/fortran/gfortran.texi b/gcc/fortran/gfortran.texi
index
In English usage, "that" introduces a restrictive clause while "which"
introduces a non-restrictive or descriptive clause. "That" is almost
never preceded by a comma while "which" often is. The Fortran manual
had many instances where these uses were reversed, or where a comma
was used with "that"
Continuing a series of patches to tidy the Fortran manual, this
installment fixes problems with inappropriate use of future tense and
adds some missing markup I noticed in passing.
gcc/fortran/ChangeLog
* intrinsic.texi: Grammar and markup fixes throughout
the file.
---
gcc/fortra
Per comments in invoke.texi, target option groups in the Option
Summary section are supposed to be alphabetized and in the same order
as the documentation sections they refer to. "M32C Options" was
misordered in the Option Summary. "Cygwin and MinGW Options" was
ordered incorrectly in both places
This patch contains the changes to files in the GCC top-level
directory to introduce the Algol 68 front-end.
---
MAINTAINERS |2 +
Makefile.def |3 +
Makefile.in | 1341 +-
Makefile.tpl | 14 +
SECURITY.txt |1 +
confi
---
libgac/Makefile.am| 113 +
libgac/Makefile.in| 860 ++
libgac/README | 2 +
libgac/aclocal.m4 | 1180 +++
libgac/config.h.in|97 +
libgac/configure | 19552
libgac/configure.ac | 403 +
libgac/libgac.c
---
gcc/Makefile.in| 34 -
gcc/common.opt | 3 +++
gcc/config.gcc | 47 ++
gcc/configure | 41 ++--
gcc/configure.ac | 14 ++
gcc/doc/tm.texi| 18
Hello people, happy GNU year!
This WIP is a GCC front-end for Algol 68, the fascinating, generally
poorly understood and often vilified programming language. It is
common knowledge that Algol 68 was well ahead of its time back when it
was introduced, and anyone who knows the language well will su
Ping!
please review.
Thanks & Regards
Jeevitha
On 15/10/24 12:49 pm, jeevitha wrote:
> Hi All,
>
> Removed powerpc*-*-* from the target test as it is always true. Simplified
> options by removing -mpower9-misc and -mvsx, which are enabled by default with
> -mdejagnu-cpu=power9. The has_arch_pwr
so that
`gcc -c a.cc --coverage -fprofile-prefix-map=$PWD=.`
does not emit $PWD in the generated a.gcno file.
PR gcov-profile/96092
---
gcc/coverage.cc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/coverage.cc b/gcc/coverage.cc
index 1ed55fed547..c6e9aced6fe 1006
在2024年12月31日十二月 下午4:56，Jiaxun Yang写道：
> As per architecture, SuperH has a reversed NaN signalling bit
> vs IEEE754-2008, it also has a NaN propgation rule similar to
> MIPS style.
Oops, please don't apply this version, it seems like auto style fixes
messed up building, sorry for the noise.
Fee
\
+ _FP_FRAC_COPY_##wc (R,X); \
+ }\
+R##_c = FP_CLS_NAN;\
} while (0)
#define _FP_TININESS_AFTER_ROUNDING 1
---
base-commit: 3672194ad2b594027311789bab9c067b7791fabd
On 12/30/24 5:53 AM, Andrew Carlotti wrote:
On Sun, Dec 29, 2024 at 10:54:03AM -0700, Jeff Law wrote:
On 12/5/24 8:45 AM, Andrew Carlotti wrote:
So at a 30k foot level, one thing to be very leery of is extending the
lifetime of any hard register. It's probably not a big deal on aarch, but
i
The following avoids applying TER to direct internal functions that
are tailcall since the involved expansion code path doesn't honor
TER constraints.
Bootstrap and regtest running on x86_64-unknown-linux-gnu.
PR middle-end/118174
* tree-outof-ssa.cc (ssa_is_replaceable_p): Exclud
Hi,
> -Original Message-
> From: Jiahao Xu
> Sent: Wednesday, December 25, 2024 10:00 AM
> To: gcc-patches@gcc.gnu.org
> Cc: xry...@xry111.site; i...@xen0n.name; chengl...@loongson.cn;
> xucheng...@loongson.cn; dengjia...@loongson.cn; Jiahao Xu
>
> Subject: [PATCH v3] LoongArch: Implemen
> -Original Message-
> From: Richard Biener
> Sent: Wednesday, November 20, 2024 11:28 AM
> To: Andrew Pinski
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH v2 2/3] cfgexpand: Rewrite add_scope_conflicts_2 to use
> cache and look back further [PR111422]
>
> On Sat, Nov 16, 2024 at 5
In LoongArch, currently uses instruction movgr2fr.{d|w} to move zero
from fixed-point register to floating-pointer regsiter for initializing
fp register to zero. When LSX or LASX is enabled, we can use instruction
vxor.v which has lower latency than instruction movgr2fr.{d|w} to set fp
register to
> Thanks, the expr.cc change looks good to me. I'd like sign-off from a
> RISC-V maintainer on the testsuite changes before pushing to trunk though.
The test change is OK but I'd prefer an extra test case. As the PR is not
really related and the patch impacts vector code gen a separate test seem
Pushed to r15-6477.
在 2024/12/25 下午5:59, Jiahao Xu 写道:
In order to support vectorization of loops with multiple exits, this
patch adds the implementation of the conditional branch optab for
LoongArch LSX/LASX instructions.
This patch causes the gen-vect-{2,25}.c tests to fail. This is because
Tsung Chun Lin writes:
> Address Richard's comment.
>
> Thanks
> Jim
>
> Richard Sandiford 於 2024年12月30日 週一 下午7:50寫道：
>>
>> Tsung Chun Lin writes:
>> > From ddb7852c92dc0222af9eeec1deafce753b3a7067 Mon Sep 17 00:00:00 2001
>> > From: Jim Tsung-Chun Lin
>> > Date: Mon, 30 Dec 2024 15:32:12 +0800
From: kelefth
`(A * B) + (-C) to (B - C/A) * A` fails to match on ILP32 targets due to
the upper bits of CST0 being zeros in some cases.
This patch adds the following pattern in match.pd:
(A + CST0) * CST1 -> (A + CST0') * CST1, where CST1 is a power of 2
constant and CST0' is CST0 with the log2
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