[committed] libstdc++: Fix some test failures with -fno-char8_t

Testewd x86_64-linux. Pushed to trunk. -- >8 -- libstdc++-v3/ChangeLog: * testsuite/20_util/duration/io.cc [!__cpp_lib_char8_t]: Define char8_t as a typedef for unsigned char. * testsuite/std/format/parse_ctx_neg.cc: Skip for -fno-char8_t. --- libstdc++-v3/testsuite/20_u

Re: [PATCH][PR113816] AArch64: Use SIMD+GPR for logical vector reductions

On Thu, 10 Oct 2024, Richard Sandiford wrote: > Jennifer Schmitz writes: > > This patch implements the optabs reduc_and_scal_, > > reduc_ior_scal_, and reduc_xor_scal_ for ASIMD modes V8QI, > > V16QI, V4HI, and V8HI for TARGET_SIMD to improve codegen for bitwise logical > > vector reduction opera

[PATCH] libstdc++: Rearrange std::move_iterator helpers in stl_iterator.h

Tested x86_64-linux. -- >8 -- The __niter_base(move_iterator) overload and __is_move_iterator trait were originally immediately after the definition of move_iterator. The addition of C++20 features after move_iterator meant that those helpers were no longer anywhere near move_iterator. This chan

[PATCH 2/2] libstdc++: Enable memset optimizations for distinct character types [PR93059]

Tested x86_64-linux. -- >8 -- Currently we only optimize std::fill to memset when the source and destination types are the same byte-sized type. This means that we fail to optimize when the fill character is another integer (e.g. a literal int value), even though assigning an int to a char would

[PATCH 1/2] libstdc++: Enable memcpy optimizations for distinct integral types [PR93059]

Tested x86_64-linux. -- >8 -- Currently we only optimize std::copy, std::copy_n etc. to memmove when the source and destination types are the same. This means that we fail to optimize copying between distinct 1-byte types, e.g. copying from a buffer of std::byte to a buffer of unsigned char. Thi

[PATCH] This is a test, please ignore

This is a test patch, please ignore. --- ci-tag: skip --- README | 2 ++ 1 file changed, 2 insertions(+) diff --git a/README b/README index be15bc2b44e..7a3d7cfeb74 100644 --- a/README +++ b/README @@ -1,3 +1,5 @@ +THIS IS A TEST -- IGNORE + This directory contains the GNU Compiler Collection (

[PATCH] This is a test2, please ignore

ci-tag: skip -- >8 -- This is a test patch, please ignore. --- README | 2 ++ 1 file changed, 2 insertions(+) diff --git a/README b/README index be15bc2b44e..7a3d7cfeb74 100644 --- a/README +++ b/README @@ -1,3 +1,5 @@ +THIS IS A TEST -- IGNORE + This directory contains the GNU Compiler Collec

[PATCH] [RFC] This is a test, please ignore

This is a test patch, please ignore. --- README | 2 ++ 1 file changed, 2 insertions(+) diff --git a/README b/README index be15bc2b44e..7a3d7cfeb74 100644 --- a/README +++ b/README @@ -1,3 +1,5 @@ +THIS IS A TEST -- IGNORE + This directory contains the GNU Compiler Collection (GCC). The GNU C

[PATCH] [RFC] This is a test, please ignore

This is a test patch, please ignore. --- README | 2 ++ 1 file changed, 2 insertions(+) diff --git a/README b/README index be15bc2b44e..7a3d7cfeb74 100644 --- a/README +++ b/README @@ -1,3 +1,5 @@ +THIS IS A TEST -- IGNORE + This directory contains the GNU Compiler Collection (GCC). The GNU C

[PATCH] tree-optimization/117050 - fix ICE with non-grouped .MASK_LOAD SLP

The following temporarily reverts the support of permuted .MASK_LOAD for the case of non-grouped accesses. Bootstrap and regtest running on x86_64-unknown-linux-gnu. PR tree-optimization/117050 * tree-vect-slp.cc (vect_build_slp_tree_2): Do not support permutes of non-grou

[PATCH v1 4/4] RISC-V: Add testcases for form 1 of vector signed SAT_SUB

From: Pan Li Form 1: #define DEF_VEC_SAT_S_SUB_FMT_1(T, UT, MIN, MAX) \ void __attribute__((noinline)) \ vec_sat_s_add_##T##_fmt_1 (T *out, T *op_1, T *op_2, unsigned limit) \ {

[PATCH v1 3/4] RISC-V: Implement vector SAT_SUB for signed integer

From: Pan Li This patch would like to implement the sssub for vector signed integer. Form 1: #define DEF_VEC_SAT_S_SUB_FMT_1(T, UT, MIN, MAX) \ void __attribute__((noinline)) \ vec_sat_s_add_##T##_fmt_1 (T *out, T *op_1, T *op_2, un

[PATCH v1 2/4] Vect: Try the pattern of vector signed integer SAT_SUB

From: Pan Li Almost the same as vector unsigned integer SAT_SUB, try to match the signed version during the vector pattern matching. The below test suites are passed for this patch. * The rv64gcv fully regression test. * The x86 bootstrap test. * The x86 fully regression test. gcc/ChangeLog:

[PATCH v1 1/4] Match: Support form 1 for vector signed integer SAT_SUB

From: Pan Li This patch would like to support the form 1 of the vector signed integer SAT_SUB. Aka below example: Form 1: #define DEF_VEC_SAT_S_SUB_FMT_1(T, UT, MIN, MAX) \ void __attribute__((noinline)) \ vec_sat_s_add_##T##_fmt_1

Re: [PATCH] RISC-V: Enable builtin __riscv_mul with Zmmul extension.

Hi Jeff, Thanks for reviewing and sorry for the testsuite without any update in my patch to cause regression failures.. I will re-submit the patches with the updated testsuite. Tsung chun Patrick O'Neill 於 2024年10月10日 週四 上午7:35寫道： > > > On 10/9/24 14:50, Jeff Law wrote: > > > > > > On 10/9/24

Re: [PATCH v6] c++: Fix overeager Woverloaded-virtual with conversion operators [PR109918]

On 10/7/24 3:35 PM, Simon Martin wrote: On 7 Oct 2024, at 18:58, Jason Merrill wrote: On 10/7/24 11:27 AM, Simon Martin wrote: /* Now give a warning for all base functions without overriders, as they are hidden. */ for (tree base_fndecl : base_fndecls) + {

Re: [PATCH 4/4] c++: enable modules by default in c++20

On 10/9/24 7:06 PM, Patrick Palka wrote: On Wed, 9 Oct 2024, Jason Merrill wrote: Tested x86_64-pc-linux-gnu, will apply to trunk with the rest of the patch series. -- 8< -- At this point there doesn't seem to be much reason not to have modules support enabled by default in C++20, and it's go

Re: [PATCH][PR113816] AArch64: Use SIMD+GPR for logical vector reductions

Tamar Christina writes: >> -Original Message- >> From: Richard Sandiford >> Sent: Thursday, October 10, 2024 8:08 PM >> To: Jennifer Schmitz >> Cc: gcc-patches@gcc.gnu.org; Richard Earnshaw ; >> Kyrylo Tkachov ; Tamar Christina >> ; rguent...@suse.de >> Subject: Re: [PATCH][PR113816] AAr

Re: [PATCH 3/3] aarch64: libgcc: Add -Werror support

Eric Gallager writes: > On Wed, Oct 9, 2024 at 4:54 AM Christophe Lyon > wrote: >> >> On Wed, 9 Oct 2024 at 03:05, Eric Gallager wrote: >> > >> > On Tue, Oct 8, 2024 at 6:25 AM Richard Sandiford >> > wrote: >> > > >> > > Christophe Lyon writes: >> > > > When --enable-werror is enabled when run

Re: [PATCH v2] Add -ftime-report-wall

On Mon, Oct 7, 2024 at 6:27 AM Richard Biener wrote: > > On Sat, Oct 5, 2024 at 10:17 AM Andi Kleen wrote: > > > > From: Andi Kleen > > > > Time vars normally use times(2) to get the user/sys/wall time, which is > > always a > > system call. I don't think the system time is very useful because

Re: [PATCH 3/3] aarch64: libgcc: Add -Werror support

On Wed, Oct 9, 2024 at 4:54 AM Christophe Lyon wrote: > > On Wed, 9 Oct 2024 at 03:05, Eric Gallager wrote: > > > > On Tue, Oct 8, 2024 at 6:25 AM Richard Sandiford > > wrote: > > > > > > Christophe Lyon writes: > > > > When --enable-werror is enabled when running the top-level configure, > > >

Re: [PATCH v2] aarch64: Improve scalar mode popcount expansion by using SVE [PR113860]

Pengxuan Zheng writes: > This is similar to the recent improvements to the Advanced SIMD popcount > expansion by using SVE. We can utilize SVE to generate more efficient code for > scalar mode popcount too. > > Changes since v1: > * v2: Add a new VNx1BI mode and a new test case for V1DI. Sorry fo

RE: [PATCH][PR113816] AArch64: Use SIMD+GPR for logical vector reductions

> -Original Message- > From: Richard Sandiford > Sent: Thursday, October 10, 2024 8:08 PM > To: Jennifer Schmitz > Cc: gcc-patches@gcc.gnu.org; Richard Earnshaw ; > Kyrylo Tkachov ; Tamar Christina > ; rguent...@suse.de > Subject: Re: [PATCH][PR113816] AArch64: Use SIMD+GPR for logical ve

Re: [PATCH][PR113816] AArch64: Use SIMD+GPR for logical vector reductions

Jennifer Schmitz writes: > This patch implements the optabs reduc_and_scal_, > reduc_ior_scal_, and reduc_xor_scal_ for ASIMD modes V8QI, > V16QI, V4HI, and V8HI for TARGET_SIMD to improve codegen for bitwise logical > vector reduction operations. > Previously, either only vector registers or only

[PATCH] Add 'cobol' to Makefile.def

Hello, I just joined the list to begin contributing patches for the COBOL front end we've been touting for the last 4 years. It's my first attempt. Please tell me if you'd like to see something different. What follows mimics to some degree the output of "git format-patch". I don't think I c

[PATCH] Always set SECTION_RELRO for or .data.rel.ro{, .local} [PR116887]

At least two ports (hppa and loongarch) need to set SECTION_RELRO for .data.rel.ro{,.local} in section_type_flags (PR52999 and PR116887), and I cannot see a reason not to just set it in the generic code. With this applied we can also remove the hppa-specific pa_section_type_flags in a future patch

[PATCH][LRA][PR116550] Reuse scratch registers generated by LRA

The detailed explanation from PR116550: Test file: udivmoddi.c problem insn: 484 Before LRA pass we have: (insn 484 483 485 72 (parallel [ (set (reg/v:SI 143 [ __q1 ]) (plus:SI (reg/v:SI 143 [ __q1 ]) (const_int -2 [0xfffe])))

RE: [PATCH][PR113816] AArch64: Use SIMD+GPR for logical vector reductions

Hi Jennifer, > -Original Message- > From: Jennifer Schmitz > Sent: Thursday, October 10, 2024 9:27 AM > To: gcc-patches@gcc.gnu.org > Cc: Richard Sandiford ; Richard Earnshaw > ; Kyrylo Tkachov ; Tamar > Christina > Subject: [PATCH][PR113816] AArch64: Use SIMD+GPR for logical vector > re

Re: [PATCH v6 1/2] aarch64: Add SVE2 faminmax intrinsics

writes: > +/* > +** amax_0_f16_z_tied1: > +** ... > +** movprfx z0, z31 > +** famax z0\.h, p0/m, z0\.h, z[0-9]+\.h > +** ret > +*/ > +TEST_UNIFORM_Z (amax_0_f16_z_tied1, svfloat16_t, > + z0 = svamax_n_f16_z (p0, z0, 0), > + z0 = svamax_z (p0, z0, 0)) We shouldn't

Re: [RFC/RFA] [PATCH v4 01/12] Implement internal functions for efficient CRC computation

On Wed, Oct 9, 2024 at 7:45 AM Jeff Law wrote: > > > On 10/8/24 4:52 AM, Mariam Arutunian wrote: > > > > > > On Sun, Sep 29, 2024 at 9:08 PM Jeff Law > > wrote: > > > > > > > > On 9/13/24 5:05 AM, Mariam Arutunian wrote: > > > Add two new internal functions

[PATCH v4 2/2] arm: [MVE intrinsics] Improve vdupq_n implementation

Hi, v4 of patch 2/2 fixes a small mistake in 3 testcases, by relaxing the expected q0 as result register into q[0-9]+ to account for codegen differences depending on if the test is compiled with -mfloat-abi=softfp or -mfloat-abi=hard. I repost patch 1/2 (already approved) so that Linaro CI can ap

[PATCH v4 1/2] arm: [MVE intrinsics] fix vdup iterator

[Reposting these 2 patches as patchwork didn't pick them.] This patch fixes a bug where the mode iterator for mve_vdup should be MVE_VLD_ST instead of MVE_vecs: V2DI and V2DF (thus vdup.64) are not supported by MVE. 2024-07-02 Jolen Li Christophe Lyon gcc/ * conf

Re: [PATCH] aarch64: Alter pr116258.c test to correct for big endian.

Richard Ball writes: > The test at pr116258.c fails on big endian targets, > this is because the test checks that the index of a floating > point multiply is 0, which is correct only for little endian. > > gcc/testsuite/ChangeLog: > > PR tree-optimization/116258 > * gcc.target/aarch64/

Re: Fix PR116650: check all regs in regrename targets

Hello again, On Thu, 10 Oct 2024, Michael Matz wrote: > > Can you please open a bugreport tracking this? > > PR116850. Gah, too many tabs :) PR117064 I meant. Ciao, Michael.

Re: Fix PR116650: check all regs in regrename targets

Hi, On Thu, 10 Oct 2024, Richard Biener wrote: > > This also shows a general confusion in that function and the target hook > > interface here: > > > > for (i = nregs - 1; i >= 0; --) > >... > >|| ! HARD_REGNO_RENAME_OK (reg + i, new_reg + i)) > > Can you please open a bugreport tracki

[PATCH] aarch64: Alter pr116258.c test to correct for big endian.

The test at pr116258.c fails on big endian targets, this is because the test checks that the index of a floating point multiply is 0, which is correct only for little endian. gcc/testsuite/ChangeLog: PR tree-optimization/116258 * gcc.target/aarch64/pr116258.c: Alter test t

Re: [PATCH] phiopt: Remove candorest variable return instead

> Am 10.10.2024 um 17:23 schrieb Andrew Pinski : > > After r15-3560-gb081e6c860eb9688d24365d39, the setting of candorest > with the break can just change to a return since this is inside a lambda now. > > Bootstrapped and tested on x86_64-linux-gnu. Ok Richard > gcc/ChangeLog: > >* t

Re: Fix PR116650: check all regs in regrename targets

> Am 10.10.2024 um 16:56 schrieb Michael Matz : > > (this came up for m68k vs. LRA, but is a generic problem) > > Regrename wants to use new registers for certain def-use chains. > For validity of replacements it needs to check that the selected > candidates are unused up to then. That's don

[PATCH] middle-end: [PR middle-end/116926] Allow widening optabs for vec-mode -> scalar-mode

The recent refactoring of the dot_prod optab to convert-type exposed a limitation in how `find_widening_optab_handler_and_mode' is currently implemented, owing to the fact that, while the function expects the GET_MODE_CLASS (from_mode) == GET_MODE_CLASS (to_mode) condition to hold, the c6x back

[PATCH] phiopt: Remove candorest variable return instead

After r15-3560-gb081e6c860eb9688d24365d39, the setting of candorest with the break can just change to a return since this is inside a lambda now. Bootstrapped and tested on x86_64-linux-gnu. gcc/ChangeLog: * tree-ssa-phiopt.cc (pass_phiopt::execute): Remove candorest and return i

Fix PR116650: check all regs in regrename targets

(this came up for m68k vs. LRA, but is a generic problem) Regrename wants to use new registers for certain def-use chains. For validity of replacements it needs to check that the selected candidates are unused up to then. That's done in check_new_reg_p. But if it so happens that the new register

Re: [PATCH] RISC-V:Bugfix for C++ code compilation failure with rv32imafc_zve32f[pr116883]

On 10/10/24 12:24 AM, Li Xu wrote: From: xuli Example as follows: int main() { unsigned long arraya[128], arrayb[128], arrayc[128]; for (int i = 0; i < 128; i++) { arraya[i] = arrayb[i] + arrayc[i]; } return 0; } Compiled with -march=rv32imafc_zve32f -mabi=ilp32f, it

[pushed] libiberty: Restore build with CP_DEMANGLE_DEBUG defined

cp-demangle.c does not build when CP_DEMANGLE_DEBUG is defined since r13-2887-gb04208895fed34. This trivial patch fixes the issue. Tested on x86_64-apple-darwin19.6.0 with "make && make check" in libiberty with CP_DEMANGLE_DEBUG defined. I'm applying this as obvious. libiberty/ChangeLog:

[PATCH] tree-optimization/117060 - fix oversight in vect_build_slp_tree_1

We are failing to match call vs. non-call when dealing with matching loads or stores. Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed. PR tree-optimization/117060 * tree-vect-slp.cc (vect_build_slp_tree_1): When comparing calls also fail if the first isn't a ca

RE: [PATCH]middle-end: support SLP early break

> > e.g. if (a != 0) where a is loop invariant. For instance test_memcmp_1_1 > > in /gcc.dg/memcmp-1.c is such loop. Technically we should be able to > > vectorize such loops, but while we can represent externals in the SLP tree, > > we can't start discovery at them, as no stmt_info for them. >

Re: [PATCH] vect: Avoid divide by zero for permutes of extern VLA vectors

On Thu, 10 Oct 2024, Richard Sandiford wrote: > My recent VLA SLP patches caused a regression with cross compilers > in gcc.dg/torture/neon-sve-bridge.c. There we have a VEC_PERM_EXPR > created from two BIT_FIELD_REFs, with the child node being an > external VLA vector: > > note: node 0x3704a7

[PATCH] vect: Avoid divide by zero for permutes of extern VLA vectors

My recent VLA SLP patches caused a regression with cross compilers in gcc.dg/torture/neon-sve-bridge.c. There we have a VEC_PERM_EXPR created from two BIT_FIELD_REFs, with the child node being an external VLA vector: note: node 0x3704a70 (max_nunits=1, refcnt=2) vector(2) long int note: op: V

[PATCH] Fix possible wrong-code with masked store-lanes

When we're doing masked store-lanes one mask element applies to all loads of one struct element. This requires uniform masks for all of the SLP lanes, something we already compute into STMT_VINFO_SLP_VECT_ONLY but fail to check when doing SLP store-lanes. The following corrects this. The followi

[PATCH v6 1/2] aarch64: Add SVE2 faminmax intrinsics

The AArch64 FEAT_FAMINMAX extension introduces instructions for computing the floating point absolute maximum and minimum of the two vectors element-wise. This patch introduces SVE2 faminmax intrinsics. The intrinsics of this extension are implemented as the following builtin functions: * sva[max

[PATCH v6 2/2] aarch64: Add codegen support for SVE2 faminmax

The AArch64 FEAT_FAMINMAX extension introduces instructions for computing the floating point absolute maximum and minimum of the two vectors element-wise. This patch adds code generation for famax and famin in terms of existing unspecs. With this patch: 1. famax can be expressed as taking UNSPEC_

[PATCH v6 0/2] Add support for SVE2 faminmax

From: Saurabh Jha This patch series is a revised version of: https://gcc.gnu.org/pipermail/gcc-patches/2024-October/664912.html In particular, the only changes are in the first patch, where in the test cases of intrinsics, we removed unnecessary capture of regular expression of operands. The sec

[Patch] Fortran/OpenMP: Warn when mapping polymorphic variables

GCC does not really handle mapping of polymorphic variables - and OpenMP 6 will also make it implementation defined. (While explicitly permitting it with data-sharing clauses.) This matches essentially what is in GCC, except that 'private' (and other privatizations) are not properly handled.

[PATCH 2/2] tree-optimization/117050 - fix ICE with non-grouped .MASK_LOAD SLP

The following fixes an oversight when handling permuted non-grouped .MASK_LOAD SLP discovery. Bootstrapped and tested on x86_64-unknown-linux-gnu. This requires 1/2. PR tree-optimization/117050 * tree-vect-slp.cc (vect_build_slp_tree_2): Properly handle non-grouped masked

Re: [PATCH] gcc.target/i386/pr115407.c: Only run for lp64

On Thu, Oct 10, 2024 at 7:13 PM H.J. Lu wrote: > > Since -mcmodel=large is valid only for lp64, run pr115407.c only for > lp64. > > * gcc.target/i386/pr115407.c: Only run for lp64. > > -- > H.J. This time is the correct patch. -- H.J. From 566b1920ce82e12a4355f4131116d4069536a61f Mon Sep 17 00:

[PATCH 1/2] Remove SLP_INSTANCE_UNROLLING_FACTOR, compute VF in vect_make_slp_decision

The following prepares us for SLP instances with a non-uniform number of lanes. We already have this with load permutation lowering, but we managed to keep that within the constraints of the per SLP instance computed VF based on its max_nunits (with a vector type fixed for each node) and the insta

Re: [PATCH] gcc.target/i386: Replace long with long long

On Thu, Oct 10, 2024 at 7:14 PM H.J. Lu wrote: > > Since long is 64-bit for x32, replace long with long long for x32. > > * gcc.target/i386/bmi2-pr112526.c: Replace long with long long. > * gcc.target/i386/pr105854.c: Likewise. > * gcc.target/i386/pr112943.c: Likewise. > * gcc.target/i386/pr67325.

Re: [PATCH] fold fold_truth_andor field merging into ifcombine was: [PATCH] assorted improvements for fold_truth_andor_1)

On Thu, Sep 26, 2024 at 10:49 AM Alexandre Oliva wrote: > > > This patch introduces various improvements to the logic that merges > field compares, moving it into ifcombine. > > Before the patch, we could merge: > > (a.x1 EQNE b.x1) ANDOR (a.y1 EQNE b.y1) > > into something like: > > (((type

[PATCH] g++.target/i386/pr105953.C: Skip for x32

Since -mabi=ms isn't supported for x32, skip g++.target/i386/pr105953.C for x32. * g++.target/i386/pr105953.C: Skip for x32. -- H.J. From 51b697d584743db0c954be293341506616c2b803 Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Thu, 10 Oct 2024 19:00:32 +0800 Subject: [PATCH] g++.target/i386/pr1

[PATCH] gcc.target/i386: Replace long with long long

Since long is 64-bit for x32, replace long with long long for x32. * gcc.target/i386/bmi2-pr112526.c: Replace long with long long. * gcc.target/i386/pr105854.c: Likewise. * gcc.target/i386/pr112943.c: Likewise. * gcc.target/i386/pr67325.c: Likewise. * gcc.target/i386/pr97971.c: Likewise. -- H.J.

[PATCH] gcc.target/i386/pr115407.c: Only run for lp64

Since -mcmodel=large is valid only for lp64, run pr115407.c only for lp64. * gcc.target/i386/pr115407.c: Only run for lp64. -- H.J. From 51b697d584743db0c954be293341506616c2b803 Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Thu, 10 Oct 2024 19:00:32 +0800 Subject: [PATCH] g++.target/i386/pr105

Re: [PATCH] RISC-V:Bugfix for C++ code compilation failure with rv32imafc_zve32f[pr116883]

LGTM On Thu, Oct 10, 2024 at 4:52 PM 钟居哲 wrote: > > LGTM from my side. But I'd rather let kito chime in to see more comments. > > Thanks. > > juzhe.zh...@rivai.ai > > > From: Li Xu > Date: 2024-10-10 14:24 > To: gcc-patches > CC: kito.cheng; palmer; juzhe.zhong; p

Re: [PATCH] RISC-V:Bugfix for C++ code compilation failure with rv32imafc_zve32f[pr116883]

LGTM from my side. But I'd rather let kito chime in to see more comments. Thanks. juzhe.zh...@rivai.ai From: Li Xu Date: 2024-10-10 14:24 To: gcc-patches CC: kito.cheng; palmer; juzhe.zhong; pan2.li; xuli Subject: [PATCH] RISC-V:Bugfix for C++ code compilation failure with rv32imafc_zve32f[pr

Re: [PATCH v1 1/4] RISC-V: Add testcases for form 5 of scalar signed SAT_TRUNC

lgtm juzhe.zh...@rivai.ai From: pan2.li Date: 2024-10-10 16:33 To: gcc-patches CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li Subject: [PATCH v1 1/4] RISC-V: Add testcases for form 5 of scalar signed SAT_TRUNC From: Pan Li Form 5: #define DEF_SAT_S_TRUNC_FMT_5(NT, WT, NT_MIN

Re: [PATCH v1 2/4] RISC-V: Add testcases for form 6 of scalar signed SAT_TRUNC

lgtm juzhe.zh...@rivai.ai From: pan2.li Date: 2024-10-10 16:33 To: gcc-patches CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li Subject: [PATCH v1 2/4] RISC-V: Add testcases for form 6 of scalar signed SAT_TRUNC From: Pan Li Form 6: #define DEF_SAT_S_TRUNC_FMT_6(NT, WT, NT_MIN

Re: [PATCH v1 4/4] RISC-V: Add testcases for form 8 of scalar signed SAT_TRUNC

lgtm juzhe.zh...@rivai.ai From: pan2.li Date: 2024-10-10 16:34 To: gcc-patches CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li Subject: [PATCH v1 4/4] RISC-V: Add testcases for form 8 of scalar signed SAT_TRUNC From: Pan Li Form 8: #define DEF_SAT_S_TRUNC_FMT_8(NT, WT, NT_MIN

Re: [PATCH v1 3/4] RISC-V: Add testcases for form 7 of scalar signed SAT_TRUNC

lgtm juzhe.zh...@rivai.ai From: pan2.li Date: 2024-10-10 16:34 To: gcc-patches CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li Subject: [PATCH v1 3/4] RISC-V: Add testcases for form 7 of scalar signed SAT_TRUNC From: Pan Li Form 7: #define DEF_SAT_S_TRUNC_FMT_7(NT, WT, NT_MIN

Re: [PATCH v1 2/2] RISC-V: Add testcases for form 4 of scalar signed SAT_TRUNC

lgtm juzhe.zh...@rivai.ai From: pan2.li Date: 2024-10-10 14:53 To: gcc-patches CC: richard.guenther; Tamar.Christina; juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li Subject: [PATCH v1 2/2] RISC-V: Add testcases for form 4 of scalar signed SAT_TRUNC From: Pan Li Form 4: #define

Re: [PATCH] aarch64: Fix folding of degenerate svwhilele case [PR117045]

> On 9 Oct 2024, at 17:35, Richard Sandiford wrote: > > External email: Use caution opening links or attachments > > > Tamar Christina writes: >> Hi Richard, >> >>> -Original Message- >>> From: Richard Sandiford >>> Sent: Wednesday, October 9, 2024 12:58 PM >>> To: gcc-patches@gcc

[PATCH v1 3/4] RISC-V: Add testcases for form 7 of scalar signed SAT_TRUNC

From: Pan Li Form 7: #define DEF_SAT_S_TRUNC_FMT_7(NT, WT, NT_MIN, NT_MAX) \ NT __attribute__((noinline)) \ sat_s_trunc_##WT##_to_##NT##_fmt_7 (WT x) \ { \ NT trunc = (NT)x;

[PATCH v1 1/4] RISC-V: Add testcases for form 5 of scalar signed SAT_TRUNC

From: Pan Li Form 5: #define DEF_SAT_S_TRUNC_FMT_5(NT, WT, NT_MIN, NT_MAX) \ NT __attribute__((noinline)) \ sat_s_trunc_##WT##_to_##NT##_fmt_5 (WT x) \ { \ NT trunc = (NT)x;

[PATCH v1 2/4] RISC-V: Add testcases for form 6 of scalar signed SAT_TRUNC

From: Pan Li Form 6: #define DEF_SAT_S_TRUNC_FMT_6(NT, WT, NT_MIN, NT_MAX) \ NT __attribute__((noinline)) \ sat_s_trunc_##WT##_to_##NT##_fmt_6 (WT x) \ { \ NT trunc = (NT)x;

[PATCH v1 4/4] RISC-V: Add testcases for form 8 of scalar signed SAT_TRUNC

From: Pan Li Form 8: #define DEF_SAT_S_TRUNC_FMT_8(NT, WT, NT_MIN, NT_MAX) \ NT __attribute__((noinline)) \ sat_s_trunc_##WT##_to_##NT##_fmt_8 (WT x) \ { \ NT trunc = (NT)x;

Re: [PATCH] [PR116831] match.pd: Check trunc_mod vector obtap before folding.

> On 10 Oct 2024, at 09:03, Richard Biener wrote: > > External email: Use caution opening links or attachments > > > On Wed, 9 Oct 2024, Jennifer Schmitz wrote: > >> >>> On 8 Oct 2024, at 10:31, Richard Biener wrote: >>> >>> External email: Use caution opening links or attachments >>> >>

[Patch] Fortran: Use OpenACC's acc_on_device builtin, fix OpenMP' __builtin_is_initial_device (was: [Patch] (was: [Patch] Fortran/OpenMP: Fix __builtin_omp_is_initial_device))

I forgot to update the subject line. To make it easier to find (patch archeology), now with proper subject line … Tobias Burnus wrote: Sometimes waiting a bit leads to better code … Tobias Burnus wrote: ... [I guess, we eventually want to add support for more builtins. For instance, acc_on_d

[ABOUT-TO-PUSH PATCH] MAINTAINERS (s390 port): Add myself

ChangeLog: * MAINTAINERS (s390 port): Add myself. --- I hope the overflow into the email column doesn't break any tooling. I will leave the patch as is for some time before pushing. MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 9257b33

[Patch] (was: [Patch] Fortran/OpenMP: Fix __builtin_omp_is_initial_device)

Sometimes waiting a bit leads to better code … Tobias Burnus wrote: ... [I guess, we eventually want to add support for more builtins. For instance, acc_on_device would be a candidate, but I could imagine some additional builtins.] I have now implemented acc_on_device and I think the new fix

Re: [PATCH] [PR113816] AArch64: Use SVE bit op reduction for vector reductions

> On 2 Oct 2024, at 14:34, Tamar Christina wrote: > > External email: Use caution opening links or attachments > > >> -Original Message- >> From: Kyrylo Tkachov >> Sent: Wednesday, October 2, 2024 1:09 PM >> To: Richard Sandiford >> Cc: Tamar Christina ; Jennifer Schmitz >> ; gcc-pa

[PATCH][PR113816] AArch64: Use SIMD+GPR for logical vector reductions

This patch implements the optabs reduc_and_scal_, reduc_ior_scal_, and reduc_xor_scal_ for ASIMD modes V8QI, V16QI, V4HI, and V8HI for TARGET_SIMD to improve codegen for bitwise logical vector reduction operations. Previously, either only vector registers or only general purpose registers (GPR) wer

Re: [PATCH 0/2] Prime path coverage to gcc/gcov

Ping. On 10/3/24 12:46, Jørgen Kvalsvik wrote: This is both a ping and a minor update. A few of the patches from the previous set have been merged, but the big feature still needs review. Since then it has been quiet, but there are two notable changes: 1. The --prime-paths-{lines,source} flags

Re: [PATCH] i386: Fix some patterns's mem attribute.

On Thu, Oct 10, 2024 at 5:46 AM Hu, Lin1 wrote: > > Hi, all > > This is another patch to modify some pattern's type attr from ssemov to > ssemov2. > > Some ssemov pattern's mem attr should be load when their 2 operand is a memory > operand. > > Bootstrapped and regtested on x86-64-linux-pc, OK for

Re: [PATCH] [PR116831] match.pd: Check trunc_mod vector obtap before folding.

On Wed, 9 Oct 2024, Jennifer Schmitz wrote: > > > On 8 Oct 2024, at 10:31, Richard Biener wrote: > > > > External email: Use caution opening links or attachments > > > > > > On Fri, 4 Oct 2024, Jennifer Schmitz wrote: > > > >> As in https://gcc.gnu.org/pipermail/gcc-patches/2024-September/66