Re: [PATCH v2] add explicit ABI and align options to pr88233.c

on 2024/5/29 14:32, Alexandre Oliva wrote: > On May 26, 2024, "Kewen.Lin" wrote: > >> Hi, >> on 2024/4/22 17:38, Alexandre Oliva wrote: >>> Ping? >>> https://gcc.gnu.org/pipermail/gcc-patches/2021-March/566530.html >>> (modified version follows) > >> Segher originated this test case, I was expec

Re: [PATCH 01/11] OpenMP/PolyInt: Pass poly-int structures by address to OMP libs.

On 5/30/24 6:28 PM, Richard Sandiford wrote: Tejas Belagod writes: Currently poly-int type structures are passed by value to OpenMP runtime functions for shared clauses etc. This patch improves on this by passing around poly-int structures by address to avoid copy-overhead. gcc/ChangeLog

Re: [PATCH 2/2] xtensa: Use epilogue_completed rather than cfun->machine->epilogue_done

On Thu, May 30, 2024 at 6:33 AM Takayuki 'January June' Suwa wrote: > > In commit ad89d820bf, an "epilogue_done" member was added to the > machine_function structure, but it is sufficient to use the existing > "epilogue_completed" global variable. > > gcc/ChangeLog: > > * config/xtensa/xte

Re: [PATCH 1/2] xtensa: Use REG_P(), MEM_P(), etc. instead of comparing GET_CODE()

On Thu, May 30, 2024 at 6:33 AM Takayuki 'January June' Suwa wrote: > > Instead of comparing directly, this patch replaces as much as possible with > macros that determine RTX code such as REG_P(), SUBREG_P() or MEM_P(), etc. > > gcc/ChangeLog: > > * config/xtensa/xtensa.cc (xtensa_valid_m

[PATCH v6] Match: Support more form for scalar unsigned SAT_ADD

From: Pan Li Update in v6 * Fix more doc build error. Update in v5 * Fix some doc build error. Log in v4: After we support one gassign form of the unsigned .SAT_ADD, we would like to support more forms including both the branch and branchless. There are 5 other forms of .SAT_ADD, list as bel

Re: [PATCH 3/3] [APX CCMP] Support ccmp for float compare

On Wed, May 15, 2024 at 4:21 PM Hongyu Wang wrote: > > The ccmp insn itself doesn't support fp compare, but x86 has fp comi > insn that changes EFLAG which can be the scc input to ccmp. Allow > scalar fp compare in ix86_gen_ccmp_first except ORDERED/UNORDERD > compare which can not be identified i

Re: [PATCH 1/3] [APX CCMP] Support APX CCMP

On Wed, May 15, 2024 at 4:24 PM Hongyu Wang wrote: > > APX CCMP feature implements conditional compare which executes compare > when EFLAGS matches certain condition. > > CCMP introduces default flags value (dfv), when conditional compare does > not execute, it will directly set the flags accordin

Re: [PATCH] i386: Optimize EQ/NE comparison between avx512 kmask and -1.

On Tue, May 28, 2024 at 4:00 PM Hu, Lin1 wrote: > > Hi all, > > This patch aims to acheive EQ/NE comparison between avx512 kmask and -1 > by using kxortest with checking CF. > > Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,-m64}. Ok for trunk? Ok. > > BRs, > Lin > > gcc/ChangeLog: > >

Re: Reverted recent patches to resource.cc

On 5/30/24 8:09 PM, Hans-Peter Nilsson wrote: Date: Wed, 29 May 2024 21:23:58 -0600 Cc: gcc-patches@gcc.gnu.org I don't bother with qemu.exp at all. I've set up binfmt handlers so that I can execute foreign binaries. So given a root filesystem, I can chroot into it and do whatever I need.

[to-be-committed] [RISC-V] Use Zbkb for general 64 bit constants when profitable

Basically this adds the ability to generate two independent constants during synthesis, then bring them together with a pack instruction. Thus we never need to go out to the constant pool when zbkb is enabled. The worst sequence we ever generate is lui+addi+lui+addi+pack Obviously if either

[PATCHv2, rs6000] Optimize vector construction with two vector doubleword loads [PR103568]

Hi, This patch optimizes vector construction with two vector doubleword loads. It generates an optimal insn sequence as "xxlor" has lower latency than "mtvsrdd" on Power10. Compared with previous version, the main change is to use "isa" attribute to guard "lxsd" and "lxsdx". https://gcc.gnu.or

Re: Reverted recent patches to resource.cc

> Date: Wed, 29 May 2024 21:23:58 -0600 > Cc: gcc-patches@gcc.gnu.org > I don't bother with qemu.exp at all. I've set up binfmt handlers so > that I can execute foreign binaries. > > So given a root filesystem, I can chroot into it and do whatever I need. > As far as dejagnu is concerned it

RE: [PATCH] aarch64: Add vector floating point extend patterns [PR113880, PR113869]

> Pengxuan Zheng writes: > > This patch improves vectorization of certain floating point widening > > operations for the aarch64 target by adding vector floating point > > extend patterns for > > V2SF->V2DF and V4HF->V4SF conversions. > > > > PR target/113880 > > PR target/113869 > > > > g

[PATCH v2] aarch64: Add vector floating point extend pattern [PR113880, PR113869]

This patch adds vector floating point extend pattern for V2SF->V2DF and V4HF->V4SF conversions by renaming the existing aarch64_float_extend_lo_ pattern to the standard optab one, i.e., extend2. This allows the vectorizer to vectorize certain floating point widening operations for the aarch64 targe

[committed] [x86] Rename double_u with __double_u to avoid pulluting the namespace.

Committed as an obvious patch. gcc/ChangeLog: * config/i386/emmintrin.h (__double_u): Rename from double_u. (_mm_load_sd): Replace double_u with __double_u. (_mm_store_sd): Ditto. (_mm_loadh_pd): Ditto. (_mm_loadl_pd): Ditto. * config/i386/xmmintrin

[PATCH v5] Match: Support more form for scalar unsigned SAT_ADD

From: Pan Li Update in v5 * Fix some doc build error. Log in v4: After we support one gassign form of the unsigned .SAT_ADD, we would like to support more forms including both the branch and branchless. There are 5 other forms of .SAT_ADD, list as below: Form 1: #define SAT_ADD_U_1(T) \

RE: [PATCH] aarch64: testsuite: Explicitly add -mlittle-endian to vget_low_2.c

> Pengxuan Zheng writes: > > vget_low_2.c is a test case for little-endian, but we missed the > > -mlittle-endian flag in r15-697-ga2e4fe5a53cf75. > > > > gcc/testsuite/ChangeLog: > > > > * gcc.target/aarch64/vget_low_2.c: Add -mlittle-endian. > > Ok, thanks. > > If you'd like write access,

[committed] i386: Rewrite bswaphi2 handling [PR115102]

Introduce *bswaphi2 instruction pattern and enable bswaphi2 expander also for non-movbe targets. The testcase: unsigned short bswap8 (unsigned short val) { return ((val & 0xff00) >> 8) | ((val & 0xff) << 8); } now expands through bswaphi2 named expander. Rewrite bswaphi_lowpart insn pattern a

[PATCH v3 3/6] btf: refactor and simplify implementation

This patch heavily refactors btfout.cc to take advantage of the structural changes in the prior commits. Now that inter-type references are internally stored as simply pointers, all the painful, brittle, confusing infrastructure that was used in the process of converting CTF type IDs to BTF type I

Re: [Patch, rs6000, aarch64, middle-end] Add implementation for different targets for pair mem fusion

Hi! On Fri, May 31, 2024 at 01:21:44AM +0530, Ajit Agarwal wrote: > Code is implemented with pure virtual functions to interface with target > code. It's not a pure function. A pure function -- by definition -- has no side effects. These things have side effects. What you mean is this is *an i

[PATCH v3 5/6] bpf,btf: enable BTF pruning by default for BPF

This patch enables -fprune-btf by default in the BPF backend when generating BTF information, and fixes BPF CO-RE generation when using -fprune-btf. When generating BPF CO-RE information, we must ensure that types used in CO-RE relocations always have sufficient BTF information emited so that the

[PATCH v3 6/6] opts: allow any combination of DWARF, CTF, BTF

Previously it was not supported to generate both CTF and BTF debug info in the same compiler run, as both formats made incompatible changes to the same internal data structures. With the structural change in the prior patches, in particular the guarantee that CTF will always be fully emitted befor

[PATCH v3 4/6] btf: add -fprune-btf option

This patch adds a new option, -fprune-btf, to control BTF debug info generation. As the name implies, this option enables a kind of "pruning" of the BTF information before it is emitted. When enabled, rather than emitting all type information translated from DWARF, only information for types dire

[PATCH v3 2/6] ctf: use pointers instead of IDs internally

This patch replaces all inter-type references in the ctfc internal data structures with pointers, rather than the references-by-ID which were used previously. A couple of small updates in the BPF backend are included to make it compatible with the change. This change is only to the in-memory repr

[PATCH v3 1/6] ctf, btf: restructure CTF/BTF emission

This commit makes some structural changes to the CTF/BTF debug info emission. In particular: a) CTF is new always fully generated and emitted before any BTF-related procedures are run. This means that BTF-related functions can change, even irreversibly, the shared in-memory represen

[PATCH v3 0/6] btf: refactor and add pruning option

[v2: https://gcc.gnu.org/pipermail/gcc-patches/2024-May/650482.html Changes from v2: - Handle -flto when generating BTF (in patch 1). For LTO builds, BTF is emitted at early_finish as before. For non-LTO builds, BTF will be emitted at (late) finish for all targets. - Move the option pars

Re: [COMMITTED] ggc: Reduce GGC_QUIRE_SIZE on Solaris/SPARC [PR115031]

> It turns out that this exhaustion of the 32-bit address space happens > due to a combination of three issues: > > * the SPARC pagesize of 8 kB, > > * ggc-page.cc's chunk size of 512 * pagesize, i.e. 4 MB, and > > * mmap adding two 8 kB unmapped red-zone pages to each mapping > > which result

Re: [PATCH 4/4]AArch64: enable new predicate tuning for Neoverse cores.

Tamar Christina writes: > Hi All, > > This enables the new tuning flag for Neoverse V1, Neoverse V2 and Neoverse N2. > It is kept off for generic codegen. > > Note the reason for the +sve even though they are in aarch64-sve.exp is if the > testsuite is ran with a forced SVE off option, e.g. -march

Re: [PATCH 3/4]AArch64: add new alternative with early clobber to patterns

Tamar Christina writes: > [...] > @@ -6651,8 +6661,10 @@ (define_insn "and3" > (and:PRED_ALL (match_operand:PRED_ALL 1 "register_operand") > (match_operand:PRED_ALL 2 "register_operand")))] >"TARGET_SVE" > - {@ [ cons: =0, 1 , 2 ] > - [ Upa , Upa, Upa ] an

Re: [PATCH v10 2/5] Convert references with "counted_by" attributes to/from .ACCESS_WITH_SIZE.

> On May 30, 2024, at 15:43, Joseph Myers wrote: > > On Thu, 30 May 2024, Qing Zhao wrote: > >> In order to make this working, the routine digest_init in c-typeck.cc >> is updated to fold calls to .ACCESS_WITH_SIZE to its first argument >> when require_constant is TRUE. > > The new change

[Patch, rs6000, aarch64, middle-end] Add implementation for different targets for pair mem fusion

Hello All: Common infrastructure using generic code for pair mem fusion of different targets. rs6000 target specific specific code implements virtual functions defined by generic code. Code is implemented with pure virtual functions to interface with target code. Target specific code are added

Re: [PATCH v10 2/5] Convert references with "counted_by" attributes to/from .ACCESS_WITH_SIZE.

On Thu, 30 May 2024, Qing Zhao wrote: > In order to make this working, the routine digest_init in c-typeck.cc > is updated to fold calls to .ACCESS_WITH_SIZE to its first argument > when require_constant is TRUE. The new changes here are OK. -- Joseph S. Myers josmy...@redhat.com

Re: [PATCH v3 #2/2] [rs6000] adjust return_pc debug attrs

Hi Alex, On Thu, May 30, 2024 at 01:40:27PM -0300, Alexandre Oliva wrote: > Sorry, I misnumbered this patch as #1/2 when first posting v3. I see at least five completely different patches in this email thread, with different subjects and all. > On May 28, 2024, Segher Boessenkool wrote: > > >

Re: [PATCH v3 #1/2] [rs6000] adjust return_pc debug attrs

On Wed, May 29, 2024 at 03:52:15AM -0300, Alexandre Oliva wrote: > On May 27, 2024, "Kewen.Lin" wrote: > > > I wonder if it's possible to have a test case for this? > > gcc.dg/guality/pr54519-[34].c at -O[1g] are fixed by this patch on > ppc64le-linux-gnu. Are these the sort of test case you're

Re: [RFC/PATCH] Replace {FLOAT,{,LONG_}DOUBLE}_TYPE_SIZE with new hook

On Wed, 29 May 2024, Kewen.Lin wrote: > > Note that when removing a target macro, it's a good idea to add it to the > > "Old target macros that have moved to the target hooks structure." list > > (of #pragma GCC poison) in system.h to ensure any new target that was > > originally written before

Re: [PATCH v3] libstdc++: Fix std::ranges::iota not in numeric [PR108760]

When I remove for importing __memcmp (my apologies for writing __memcpy) from libstdc++-v3/include/bits/ranges_algobase.h and try to rerun the code, I get the following error: In file included from $HOME/projects/objdirforgcc/_pfx/include/c++/15.0.0/numeric:69, from ranges-iot

Re: [PATCH] Fix LTO type mismatch warning on transparent union

> Am 30.05.2024 um 13:46 schrieb Eric Botcazou : > >  >> >> Do function pointers inter-operate TBAA wise for this case and would this >> possibly An issue? > > Do you mean in LTO mode? I must say I'm not sure of the way LTO performs TBAA > for function pointers: does it require (strict) mat

Re: [C PATCH, v2]: allow aliasing of compatible types derived from enumeral types [PR115157]

On Thu, May 30, 2024 at 12:48 AM Martin Uecker wrote: > > > Hi Ian, > > can you give me a green light for the go changes. The C FE > changes were approved. > > The only change with respect to the last version are > the removal of the unneeded null check for the > main variant (as discussed) and th

Re: [PATCH v3 #2/2] [rs6000] adjust return_pc debug attrs

Sorry, I misnumbered this patch as #1/2 when first posting v3. On May 28, 2024, Segher Boessenkool wrote: > Please don't (incorrectly!) line-wrap changelogs. Lines are 80 > characters wide, not 60 or 72 or whatever. 80. Indents are tabs that > take 8 columns. ACK. When was it bumped up to 8

Re: [PATCH 2/4]AArch64: add new tuning param and attribute for enabling conditional early clobber

Tamar Christina writes: >> -Original Message- >> From: Tamar Christina >> Sent: Wednesday, May 22, 2024 10:29 AM >> To: Richard Sandiford >> Cc: gcc-patches@gcc.gnu.org; nd ; Richard Earnshaw >> ; Marcus Shawcroft >> ; ktkac...@gcc.gnu.org >> Subject: RE: [PATCH 2/4]AArch64: add new tuni

[PATCH 6/6] vect: Optimize order of lane-reducing statements in loop def-use cycles [PR114440]

When transforming multiple lane-reducing operations in a loop reduction chain, originally, corresponding vectorized statements are generated into def-use cycles starting from 0. The def-use cycle with smaller index, would contain more statements, which means more instruction dependency. For example

[PATCH 5/6] vect: Support multiple lane-reducing operations for loop reduction [PR114440]

For lane-reducing operation(dot-prod/widen-sum/sad) in loop reduction, current vectorizer could only handle the pattern if the reduction chain does not contain other operation, no matter the other is normal or lane-reducing. Actually, to allow multiple arbitray lane-reducing operations, we need to

[PATCH 4/6] vect: Bind input vectype to lane-reducing operation

The input vectype is an attribute of lane-reducing operation, instead of reduction PHI that it is associated to, since there might be more than one lane-reducing operations with different type in a loop reduction chain. So bind each lane-reducing operation with its own input type. Thanks, Feng ---

[PATCH 3/6] vect: Set STMT_VINFO_REDUC_DEF for non-live stmt in loop reduction

Normally, vectorizable checking on statement in a loop reduction chain does not use the reduction PHI information. But some special statements might need it in vectorizable analysis, especially, for multiple lane-reducing operations support later. Thanks, Feng --- gcc/ * tree-vect-loop.cc

[PATCH 2/6] vect: Split out partial vect checking for reduction into a function

This is a patch that is split out from https://gcc.gnu.org/pipermail/gcc-patches/2024-May/652626.html. Partial vectorization checking for vectorizable_reduction is a piece of relatively isolated code, which may be reused by other places. Move the code into a new function for sharing. Thanks, Fen

[PATCH 1/6] vect: Add a function to check lane-reducing code [PR114440]

This is a patch that is split out from https://gcc.gnu.org/pipermail/gcc-patches/2024-May/652626.html. Check if an operation is lane-reducing requires comparison of code against three kinds (DOT_PROD_EXPR/WIDEN_SUM_EXPR/SAD_EXPR). Add an utility function to make source coding for the check handy

Re: [PATCH] ira: Fix go_through_subreg offset calculation [PR115281]

On 5/30/24 03:59, Richard Sandiford wrote: Tested on aarch64-linux-gnu & x86_64-linux-gnu. OK to install? Yes.  Thank you, Richard. gcc/ PR rtl-optimization/115281 * ira-conflicts.cc (go_through_subreg): Use the natural size of the inner mode rather than the outer m

Re: [PATCH] [RFC] Target-independent store forwarding avoidance. [PR48696] Target-independent store forwarding avoidance.

On Fri, May 24, 2024 at 9:27 AM Richard Biener wrote: > > On Thu, 23 May 2024, Manolis Tsamis wrote: > > > This pass detects cases of expensive store forwarding and tries to avoid > > them > > by reordering the stores and using suitable bit insertion sequences. > > For example it can transform th

[PATCH v4] Match: Support more form for scalar unsigned SAT_ADD

From: Pan Li After we support one gassign form of the unsigned .SAT_ADD, we would like to support more forms including both the branch and branchless. There are 5 other forms of .SAT_ADD, list as below: Form 1: #define SAT_ADD_U_1(T) \ T sat_add_u_1_##T(T x, T y) \ { \ return (T)(x

Re: [COMMITTED 01/12] - Move all relation queries into relation_oracle.

Hello... Le 23/05/2024 à 22:52, Andrew MacLeod a écrit : A range-query currently provides a couple of relation query routines, plus it also provides direct access to an oracle.   This patch moves those queries into the oracle where they should be, and ands the ability to create and destroy the

Re: [PATCH] vect: Support multiple lane-reducing operations for loop reduction [PR114440]

>> Hi, >> >> The patch was updated with the newest trunk, and also contained some minor >> changes. >> >> I am working on another new feature which is meant to support pattern >> recognition >> of lane-reducing operations in affine closure originated from loop reduction >> variable, >> like: >>

[COMMITTED] ggc: Reduce GGC_QUIRE_SIZE on Solaris/SPARC [PR115031]

g++.dg/modules/pr99023_b.X currently FAILs on 32-bit Solaris/SPARC: FAIL: g++.dg/modules/pr99023_b.X -std=c++2a 1 blank line(s) in output FAIL: g++.dg/modules/pr99023_b.X -std=c++2a (test for excess errors) Excess errors: cc1plus: out of memory allocating 1048344 bytes after a total of 7913472 b

Re: [PATCH 00/11] AArch64/OpenMP: Test SVE ACLE types with various OpenMP constructs.

Tejas Belagod writes: > Note: This patch series is based on Richard's initial patch > https://gcc.gnu.org/pipermail/gcc-patches/2022-November/606741.html > and Jakub's suggestion > https://gcc.gnu.org/pipermail/gcc-patches/2023-February/611892.html > > The following patch series handles variou

Re: [PATCH 01/11] OpenMP/PolyInt: Pass poly-int structures by address to OMP libs.

Tejas Belagod writes: > Currently poly-int type structures are passed by value to OpenMP runtime > functions for shared clauses etc. This patch improves on this by passing > around poly-int structures by address to avoid copy-overhead. > > gcc/ChangeLog > * omp-low.c (use_pointer_for_field)

Re: [PATCH 03/11] AArch64: Diagnose OpenMP offloading when SVE types involved.

Tejas Belagod writes: > The target clause in OpenMP is used to offload loop kernels to accelarator > peripeherals. target's 'map' clause is used to move data from and to the > accelarator. When the data is SVE type, it may not be suitable because of > various reasons i.e. the two SVE targets may

[pushed] Add new text_art::tree_widget and use it in analyzer

This patch adds a new text_art::tree_widget, which makes it easy to generate hierarchical visualizations using either ASCII: +- Child 0 | +- Grandchild 0 0 | +- Grandchild 0 1 | `- Grandchild 0 2 +- Child 1 | +- Grandchild 1 0 | +- Grandchild 1 1 | `- Grandchild 1 2 `- Chil

[pushed] analyzer: fix a -Wunused-parameter

Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu. Pushed to trunk as r15-926-g0b3a3a66eb816b. gcc/analyzer/ChangeLog: * infinite-loop.cc (looping_back_event::get_desc): Fix unused parameter warning introduced by me in r15-636-g770657d02c986c. Signed-off-by: David Malc

Re: [PATCH 02/11] AArch64: Add test cases for SVE types in OpenMP shared clause.

Tejas Belagod writes: > This patch tests various shared clauses with SVE types. It also adds a test > scaffold to run OpenMP tests in under the gcc.target testsuite. > > gcc/testsuite/ChangeLog: > > * gcc.target/aarch64/sve/omp/aarch64-sve-omp.exp: New scaffold. Hopefully Jakub can comment

Re: [Patch, aarch64, middle-end\ v4: Move pair_fusion pass from aarch64 to middle-end

Hello Richard: On 30/05/24 4:44 pm, Richard Sandiford wrote: > Thanks for the update. Some comments below, but looks very close > to ready. > Thanks a lot. > Ajit Agarwal writes: >> diff --git a/gcc/pair-fusion.cc b/gcc/pair-fusion.cc >> new file mode 100644 >> index 000..060fd95

[PATCH v10 3/5] Use the .ACCESS_WITH_SIZE in builtin object size.

gcc/ChangeLog: * tree-object-size.cc (access_with_size_object_size): New function. (call_object_size): Call the new function. gcc/testsuite/ChangeLog: * gcc.dg/builtin-object-size-common.h: Add a new macro EXPECT. * gcc.dg/flex-array-counted-by-3.c: New test.

[PATCH v10 5/5] Add the 6th argument to .ACCESS_WITH_SIZE

to carry the TYPE of the flexible array. Such information is needed during tree-object-size.cc. We cannot use the result type or the type of the 1st argument of the routine .ACCESS_WITH_SIZE to decide the element type of the original array due to possible type casting in the source code. gcc/c/C

[PATCH v10 4/5] Use the .ACCESS_WITH_SIZE in bound sanitizer.

gcc/c-family/ChangeLog: * c-ubsan.cc (get_bound_from_access_with_size): New function. (ubsan_instrument_bounds): Handle call to .ACCESS_WITH_SIZE. gcc/testsuite/ChangeLog: * gcc.dg/ubsan/flex-array-counted-by-bounds-2.c: New test. * gcc.dg/ubsan/flex-array-counted

[PATCH v10 2/5] Convert references with "counted_by" attributes to/from .ACCESS_WITH_SIZE.

Including the following changes: * The definition of the new internal function .ACCESS_WITH_SIZE in internal-fn.def. * C FE converts every reference to a FAM with a "counted_by" attribute to a call to the internal function .ACCESS_WITH_SIZE. (build_component_ref in c_typeck.cc) This includ

[PATCH v10 1/5] Provide counted_by attribute to flexible array member field (PR108896)

'counted_by (COUNT)' The 'counted_by' attribute may be attached to the C99 flexible array member of a structure. It indicates that the number of the elements of the array is given by the field "COUNT" in the same structure as the flexible array member. GCC may use this inf

[PATCH v10 0/5] New attribute "counted_by" to annotate bounds for C99 FAM(PR108896)

Hi, This is the 10th version of the patch. Which is rebased on the latest trunk. Compare with the 9th version, all the difference are in patch #2, including a small C FE change in the routine "digest_init". all others are middle-end changes. please review the changes for the patch #2: updates p

Re: [PATCH] gimple ssa: Teach switch conversion to optimize powers of 2 switches

On Thu, May 30, 2024 at 5:09 AM Filip Kastl wrote: > > Hi, > > This patch adds a transformation into the switch conversion pass -- > the "exponential index transform". This transformation can help switch > conversion convert switches it otherwise could not. The transformation is > intended for s

[PATCH] gimple ssa: Teach switch conversion to optimize powers of 2 switches

Hi, This patch adds a transformation into the switch conversion pass -- the "exponential index transform". This transformation can help switch conversion convert switches it otherwise could not. The transformation is intended for switches whose cases are all powers of 2. Here is a more detailed

Re: [PATCH] Fix LTO type mismatch warning on transparent union

> Do function pointers inter-operate TBAA wise for this case and would this > possibly An issue? Do you mean in LTO mode? I must say I'm not sure of the way LTO performs TBAA for function pointers: does it require (strict) matching of the type for all the parameters of the pointed-to function t

[PING] [PATCH] RISC-V: Add Zfbfmin extension

1 In the previous patch, the libcall for BF16 was implemented: 2 Riscv provides Zfbfmin extension, which completes the "Scalar BF16 Converts":

[PATCH] Fix PR c++/111106: missing ; causes internal compiler error

We currently fail upon the following because an assert in dependent_type_p fails for f's parameter === cut here === consteval int id (int i) { return i; } constexpr int f (auto i) requires requires { id (i) } { return i; } void g () { f (42); } === cut here === This patch fixes this by handling s

Re: [Patch, aarch64, middle-end\ v4: Move pair_fusion pass from aarch64 to middle-end

Thanks for the update. Some comments below, but looks very close to ready. Ajit Agarwal writes: > diff --git a/gcc/pair-fusion.cc b/gcc/pair-fusion.cc > new file mode 100644 > index 000..060fd95 > --- /dev/null > +++ b/gcc/pair-fusion.cc > @@ -0,0 +1,3012 @@ > +// Pass to fuse adjace

Re: [PATCH] Fix -Wstringop-overflow warning in 23_containers/vector/types/1.cc

On Thu, 30 May 2024 at 06:11, François Dumont wrote: > > Looks like this new version works the same to fix the warning without > the issues reported here. > > All 23_containers/vector tests run in C++98/14/20 so far. > > Ok to commit once I've complete the testsuite (or some bot did it for me > !)

Re: [PATCH] aarch64: testsuite: Explicitly add -mlittle-endian to vget_low_2.c

Pengxuan Zheng writes: > vget_low_2.c is a test case for little-endian, but we missed the > -mlittle-endian > flag in r15-697-ga2e4fe5a53cf75. > > gcc/testsuite/ChangeLog: > > * gcc.target/aarch64/vget_low_2.c: Add -mlittle-endian. Ok, thanks. If you'd like write access, please follow the

Re: [PATCH] aarch64: Add vector floating point extend patterns [PR113880, PR113869]

Pengxuan Zheng writes: > This patch improves vectorization of certain floating point widening > operations > for the aarch64 target by adding vector floating point extend patterns for > V2SF->V2DF and V4HF->V4SF conversions. > > PR target/113880 > PR target/113869 > > gcc/ChangeLog: >

Re: [PATCH] [libstdc++-v3] [rtems] enable filesystem support

Thanks. I got bounces from oarcorp.com and rtems.org, are the details in MAINTAINERS out of date for Joel and Ralf? On Thu, 30 May 2024 at 09:19, Alexandre Oliva wrote: > > On May 30, 2024, Jonathan Wakely wrote: > > > Typo here, "rtemps"? > > Ugh, thanks, fixed. > > > OK with that fixed (and c

Re: [PATCH] [libstdc++-v3] [rtems] enable filesystem support

On May 30, 2024, Jonathan Wakely wrote: > Typo here, "rtemps"? Ugh, thanks, fixed. > OK with that fixed (and configure regenerated). I also untabified the new lines, to match the surrounding context. Here's what I installed: [libstdc++-v3] [rtems] enable filesystem support mkdir, chdir and c

[PATCH] ira: Fix go_through_subreg offset calculation [PR115281]

go_through_subreg used: else if (!can_div_trunc_p (SUBREG_BYTE (x), REGMODE_NATURAL_SIZE (GET_MODE (x)), offset)) to calculate the register offset for a pseudo subreg x. In the blessed days before poly-int, this was: *offset = (SUBREG_BYTE (x) / REGMODE_NATURA

Re: [C PATCH, v2]: allow aliasing of compatible types derived from enumeral types [PR115157]

Hi Ian, can you give me a green light for the go changes. The C FE changes were approved. The only change with respect to the last version are the removal of the unneeded null check for the main variant (as discussed) and that I also removed the container->decls_seen.add (TREE_TYPE (decl)); a

Re: [RFC/RFA] [PATCH 08/12] Add a new pass for naive CRC loops detection

> Am 30.05.2024 um 00:31 schrieb Jeff Law : > >  > >> On 5/28/24 1:01 AM, Richard Biener wrote: >>> On Fri, May 24, 2024 at 10:46 AM Mariam Arutunian >>> wrote: >>> >>> This patch adds a new compiler pass aimed at identifying naive CRC >>> implementations, >>> characterized by the presence

[pushed] wwwdocs: *: Use https to access gcc.gnu.org/onlinedocs

Not sure we really need to keep all those docus for all our point releases. Might make more sense use the latest for each branch. But that's another discussion. Gerald --- htdocs/gcc-10/index.html | 12 ++-- htdocs/gcc-11/index.html | 10 +- htdocs/gcc-12/index.html | 8 +++