[PATCH] lower-bitint: Avoid merging non-mergeable stmt with cast and mergeable stmt [PR112902]

Hi! Before bitint lowering, the IL has: b.0_1 = b; _2 = -b.0_1; _3 = (unsigned _BitInt(512)) _2; a.1_4 = a; a.2_5 = (unsigned _BitInt(512)) a.1_4; _6 = _3 * a.2_5; on the first function. Now, gimple_lower_bitint has an optimization (when not -O0) that it avoids assigning underlying VA

[PATCH] vr-values: Avoid ICEs on large _BitInt cast to floating point [PR112901]

Hi! For casts from integers to floating point, simplify_float_conversion_using_ranges uses SCALAR_INT_TYPE_MODE and queries optabs on the optimization it wants to make. That doesn't really work for large/huge BITINT_TYPE, those have BLKmode which is not scalar int mode. Querying an optab is not

Re: [PATCH] haifa-sched: Avoid overflows in extend_h_i_d [PR112411]

On Fri, 8 Dec 2023, Jakub Jelinek wrote: > On Thu, Dec 07, 2023 at 11:54:01AM +0100, Jakub Jelinek wrote: > > On Thu, Dec 07, 2023 at 09:36:23AM +0100, Jakub Jelinek wrote: > > > Without the dg-skip-if I got on 64-bit host: > > > cc1: out of memory allocating 571230784744 bytes after a total of 27

Re: [pushed][PATCH v2 0/2] Delete ISA_BASE_LA64V110 related definitions.

Pushed to r14-6303 and r14-6304. 在 2023/12/5 上午10:30, Lulu Cheng 写道: 1. Rebase Xi Ruoyao's patch a to the latest commit. https://gcc.gnu.org/pipermail/gcc-patches/2023-November/636798.html 2. remove the #if !defined(IN_LIBGCC2) && !defined(IN_TARGET_LIBS) && !defined(IN_RTS) guards in loongarch

[PATCH] haifa-sched: Avoid overflows in extend_h_i_d [PR112411]

On Thu, Dec 07, 2023 at 11:54:01AM +0100, Jakub Jelinek wrote: > On Thu, Dec 07, 2023 at 09:36:23AM +0100, Jakub Jelinek wrote: > > Without the dg-skip-if I got on 64-bit host: > > cc1: out of memory allocating 571230784744 bytes after a total of 2772992 > > bytes > > I've looked at this and the

Re: [PATCH] treat argp-based mem as frame related in dse

Hi, Jeff Law writes: > On 12/6/23 02:27, Jiufu Guo wrote: >> Hi, >> >> The issue mentioned in PR112525 would be able to be handled by >> updating dse.cc to treat arg_pointer_rtx similarly with frame_pointer_rtx. >> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=30271#c10 also mentioned >> this i

[PATCH] [ICE] Support vpcmov for V4HF/V4BF/V2HF/V2BF under TARGET_XOP.

Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. Ready push to trunk. gcc/ChangeLog: PR target/112904 * config/i386/mmx.md (*xop_pcmov_): New define_insn. gcc/testsuite/ChangeLog: * g++.target/i386/pr112904.C: New test. --- gcc/config/i386/mmx.md

[gcc-wwwdocs PATCH] gcc-13/14: Mention recent update for x86_64 backend

Hi all, This patch will mention the following changes in wwwdocs for x86_64 backend: - AVX10.1 support - APX EGPR, PUSH2POP2, PPX and NDD support - Xeon Phi ISAs deprecated Also I adjust the words in x86_64 part for GCC 13. Ok for gcc-wwwdocs? Thx, Haochen Mention AVX10.1 support, APX su

Re: [PATCH] testsuite: scev: expect fail on ilp32

On Thu, 7 Dec 2023, Hans-Peter Nilsson wrote: > > Date: Mon, 4 Dec 2023 12:58:03 +0100 (CET) > > From: Richard Biener > > > On Sat, 2 Dec 2023, Hans-Peter Nilsson wrote: > > > > Date: Fri, 1 Dec 2023 08:07:14 +0100 (CET) > > > > From: Richard Biener > > > > I read from your messages that the te

Re: [PATCH]

On Thu, Dec 7, 2023 at 6:52 PM Alexandre Oliva wrote: > > On Dec 7, 2023, Thomas Schwinge wrote: > > > Thank you for looking into this so promptly! > > You're welcome ;-) > > > > during IPA pass: emutls > > [...]/source-gcc/gcc/testsuite/c-c++-common/strub-unsupported-3.c:18:1: > > inte

[Committed] RISC-V: Remove redundant check of better_main_loop_than_p in COST model

Since loop vectorizer won't call better_main_loop_than_p if !flag_vect_cost_model. Committed as it is obvious. gcc/ChangeLog: * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): Remove redundant check. --- gcc/config/riscv/riscv-vector-costs.cc | 3 --- 1 file chan

Re: [PATCH] i386: Mark Xeon Phi ISAs as deprecated

On Wed, Dec 6, 2023 at 3:52 PM Richard Biener wrote: > > On Wed, Dec 6, 2023 at 3:33 AM Jiang, Haochen wrote: > > > > > -Original Message- > > > From: Jiang, Haochen > > > Sent: Friday, December 1, 2023 4:51 PM > > > To: Richard Biener > > > Cc: gcc-patches@gcc.gnu.org; Liu, Hongtao ; >

Re: Re: [PATCH][v2] RISC-V: Add avail interface into function_group_info

2023-12-08 11:35 Kito Cheng wrote: >> Without comma, there is a warning "warning: ISO C++11 requires at least one >> argument for the "..." in a variadic macro". >> So I add the comma. > >Oh, thanks, I wasn't aware that, maybe take one more argument to '...' > >#define DEF_RVV_FUNCTION(NAME, S

Re: [PATCH] LoongArch: Allow -mcmodel=extreme and model attribute with -mexplicit-relocs=auto

On 2023-12-08 10:04, chenglulu wrote: 在 2023/12/7 下午8:20, Xi Ruoyao 写道: There seems no real reason to require -mexplicit-relocs=always for -mcmodel=extreme or model attribute.  As the linker does not know how to relax a 3-operand la.local or la.global pseudo instruction, just emit explicit rel

Re: Re: [PATCH][v2] RISC-V: Add avail interface into function_group_info

> Without comma, there is a warning "warning: ISO C++11 requires at least one > argument for the "..." in a variadic macro". > So I add the comma. Oh, thanks, I wasn't aware that, maybe take one more argument to '...' #define DEF_RVV_FUNCTION(NAME, SHAPE, PREDS, ...) Anyway my intention is to r

Re: [PATCH] tree-optimization/PR112774 - SCEV: extend the chrec tree with a nonwrapping flag

> Yes, I can see that. I think the patch is OK with a minor nit - can you > please document the nothrow flag usage in TREE_CHREC in > tree-core.h? There's a big comment doing flags documentation: Thanks, committed with the new documentation: https://gcc.gnu.org/g:2efe3a7de0107618397264017fb045f2

Re: [PATCH V3 2/3] Using pli for constant splitting

Hi, Thanks for your insight and helpful review! "Kewen.Lin" writes: > Hi Jeff, > > on 2023/12/6 13:24, Jiufu Guo wrote: >> Hi, >> >> For constant building e.g. r120=0x, which does not fit 'li or lis', >> 'pli' is used to build this constant via 'emit_move_insn'. >> >> While for a co

Re: [PATCH V3 1/3]rs6000: update num_insns_constant for 2 insns

Hi, Thanks for your always kind and helpful review!! "Kewen.Lin" writes: > Hi Jeff, > > on 2023/12/6 13:24, Jiufu Guo wrote: >> Hi, >> >> Trunk gcc supports more constants to be built via two instructions: >> e.g. "li/lis; xori/xoris/rldicl/rldicr/rldic". >> And then num_insns_constant shoul

Re: Re: [PATCH][v2] RISC-V: Add avail interface into function_group_info

2023-12-08 11:18 Kito Cheng wrote: >> @@ -31,624 +31,627 @@ along with GCC; see the file COPYING3. If not see >>   - OPS_INFO describes all information of return type and each >> argument type. >> >> + - AVAIL this argument is the optional for AVAIL.Determin the enab

Re: [PATCH][v2] RISC-V: Add avail interface into function_group_info

> @@ -31,624 +31,627 @@ along with GCC; see the file COPYING3. If not see > - OPS_INFO describes all information of return type and each > argument type. > > + - AVAIL this argument is the optional for AVAIL.Determin the enable > + of the intrinsic function. > + > */ > #if

Re: [V2 PATCH] Simplify vector ((VCE (a cmp b ? -1 : 0)) < 0) ? c : d to just (VCE ((a cmp b) ? (VCE c) : (VCE d))).

ping. On Thu, Nov 16, 2023 at 6:49 PM liuhongt wrote: > > Update in V2: > 1) Add some comments before the pattern. > 2) Remove ? from view_convert. > > Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. > Ok for trunk? > > When I'm working on PR112443, I notice there's some misoptimization

Re: [PATCH][v2] RISC-V: Add avail interface into function_group_info

2023-12-08 10:44 Feng Wang wrote: Have run all the vector api-testing. >Patch v2: Using variadic macro and add the dependency into t-riscv > >In order to add other extension about vector,this patch add >unsigned int (*avail) (void) into function_group_info to determine >whether to re

[PATCH][v2] RISC-V: Add avail interface into function_group_info

Patch v2: Using variadic macro and add the dependency into t-riscv In order to add other extension about vector,this patch add unsigned int (*avail) (void) into function_group_info to determine whether to register the intrinsic based on ISA info. gcc/ChangeLog: * config/riscv/riscv-vecto

Re: [patch-2v3, rs6000] Guard fctid on PowerPC64 and PowerPC476 [PR112707]

Hi Haochen, on 2023/12/8 09:58, HAO CHEN GUI wrote: > Hi, > The "fctid" is supported on 64-bit Power processors and PowerPC476. It > need a guard to check it. The patch fixes the issue. > > Compared with last version, > https://gcc.gnu.org/pipermail/gcc-patches/2023-December/639536.html > the

[PATCH] Don't assume it's AVX_U128_CLEAN after call_insn whose abi.mode_clobber(V4DImode) deosn't contains all SSE_REGS.

If the function desn't clobber any sse registers or only clobber 128-bit part, then vzeroupper isn't issued before the function exit. the status not CLEAN but ANY after the function. Also for sibling_call, it's safe to issue an vzeroupper. Also there could be missing vzeroupper since there's no mo

Re: [PATCH v3] LoongArch: Fix eh_return epilogue for normal returns

On Thu, Dec 07, 2023 at 04:13:51PM +0800, Xi Ruoyao wrote: > > I understand and I don't think adding {} is wrong. The problem is the > indent change causes a large chunk of diff and it makes reviewing more > difficult. Thus generally we should not mix real code change and format > change in a co

Re: [PATCH] LoongArch: Allow -mcmodel=extreme and model attribute with -mexplicit-relocs=auto

在 2023/12/7 下午8:20, Xi Ruoyao 写道: There seems no real reason to require -mexplicit-relocs=always for -mcmodel=extreme or model attribute. As the linker does not know how to relax a 3-operand la.local or la.global pseudo instruction, just emit explicit relocs for SYMBOL_PCREL64, and under TARGE

Re: [PATCH] testsuite: Adjust for the new permerror -Wincompatible-pointer-types

On Thu, Dec 07, 2023 at 10:18:47AM +0100, Florian Weimer wrote: > * Yang Yujie: > > > With this patch, I also noticed a few errors in building unpatched older > > software like expect-5.45.4, perl-5.28.3 and bash-5.0. Will this also be > > the case when GCC 14 gets released? > > For Fedora, we k

Re: [patch-2v3, rs6000] Guard fctid on PowerPC64 and PowerPC476 [PR112707]

Hi, The "fctid" is supported on 64-bit Power processors and PowerPC476. It need a guard to check it. The patch fixes the issue. Compared with last version, https://gcc.gnu.org/pipermail/gcc-patches/2023-December/639536.html the main change is to change the target requirement in pr88558*.c.

Re: [PATCH v3 2/3] libphobos: Update build scripts for LoongArch64.

On Thu, Dec 07, 2023 at 11:34:28AM +0100, Iain Buclaw wrote: > > Just a nitpick, I'd thought the committing of switchcontext.S should > come before this. I have no strong opinion either way. > > OK to commit. > > Iain. Thanks for the suggestion, indeed this makes sense. Yujie

Re: [PATCH v3 1/3] LoongArch: Adjust D version strings.

On Thu, Dec 07, 2023 at 11:30:16AM +0100, Iain Buclaw wrote: > Hi, > > Thanks for this. > > Excerpts from Yang Yujie's message of Dezember 1, 2023 11:08 am: > > diff --git a/gcc/d/dmd/cond.d b/gcc/d/dmd/cond.d > > index 568b639e0b6..02af0cc9e29 100644 > > --- a/gcc/d/dmd/cond.d > > +++ b/gcc/d/dm

Re: [PATCH] libgccjit: Add type checks in gcc_jit_block_add_assignment_op

On Thu, 2023-12-07 at 17:34 -0500, Antoni Boucher wrote: > Hi. > This patch adds checks gcc_jit_block_add_assignment_op to make sure > it > is only ever called on numeric types. > > With the previous patch, this might require a change to also allow > vector types here. > > Thanks for the review.

Re: [PATCH] libgccjit: Make is_int return false on vector types

Can I merge this on master even though we're not in phase 1 anymore? On Thu, 2023-12-07 at 20:07 -0500, David Malcolm wrote: > On Thu, 2023-12-07 at 17:32 -0500, Antoni Boucher wrote: > > Hi. > > This patch changes the function is_int to return false on vector > > types. > > Thanks for the review.

Re: [PATCH] libgccjit: Make is_int return false on vector types

On Thu, 2023-12-07 at 17:32 -0500, Antoni Boucher wrote: > Hi. > This patch changes the function is_int to return false on vector > types. > Thanks for the review. Thanks; looks good to me Dave

Re: [PATCH] libgccjit: Make new_array_type take unsigned long

On Thu, 2023-12-07 at 17:29 -0500, Antoni Boucher wrote: > Hi. > This patches update gcc_jit_context_new_array_type to take the size > as > an unsigned long instead of a int, to allow creating bigger array > types. > > I haven't written the ChangeLog yet because I wasn't sure it's > allowed > to c

Re: [PATCH] libgccjit: Fix get_size of size_t

On Thu, 2023-12-07 at 17:26 -0500, Antoni Boucher wrote: > Hi. > This patch fixes getting the size of size_t (bug 112910). > > There's one issue with this patch: like every other feature that > checks > for target-specific stuff, it requires a compilation before actually > fetching the size of the

Re: [PATCH 1/5][V3][ifcvt] optimize x=c ? (y op z) : y by RISC-V Zicond like insns

On 12/5/23 01:12, Fei Gao wrote: op=[PLUS, MINUS, IOR, XOR] Conditional op, if zero rd = (rc == 0) ? (rs1 op rs2) : rs1 --> czero.nez rd, rs2, rc op rd, rs1, rd Conditional op, if non-zero rd = (rc != 0) ? (rs1 op rs2) : rs1 --> czero.eqz rd, rs2, rc op rd, rs1, rd Co-authored-by: Xiao Zeng

[pushed] analyzer: fix ICE for 2 bits before the start of base region [PR112889]

Cncrete bindings were using -1 and -2 in the offset field to signify deleted and empty hash slots, but these are valid values, leading to assertion failures inside hash_map::put on a debug build, and probable bugs in a release build. (gdb) call k.dump(true) start: -2, size: 1, next: -1 (gdb) p k.

Re: [PATCH] Expand: Pass down equality only flag to cmpmem expand

On 11/28/23 00:43, HAO CHEN GUI wrote: Hi, This patch passes down the equality only flags from emit_block_cmp_hints to cmpmem optab so that the target specific expand can generate optimized insns for equality only compare. Targets (e.g. rs6000) can generate more efficient insn sequence if t

[PATCH] libgccjit: Add type checks in gcc_jit_block_add_assignment_op

Hi. This patch adds checks gcc_jit_block_add_assignment_op to make sure it is only ever called on numeric types. With the previous patch, this might require a change to also allow vector types here. Thanks for the review. From 932048619671c61af224708a3da484b9f54a30a3 Mon Sep 17 00:00:00 2001 From

[PATCH] libgccjit: Make is_int return false on vector types

Hi. This patch changes the function is_int to return false on vector types. Thanks for the review. From 60ebfb998bd349ca2f05b115de5452378027e4de Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Thu, 26 Oct 2023 19:17:55 -0400 Subject: [PATCH] libgccjit: Make is_int return false on vector types

[PATCH] libgccjit: Make new_array_type take unsigned long

Hi. This patches update gcc_jit_context_new_array_type to take the size as an unsigned long instead of a int, to allow creating bigger array types. I haven't written the ChangeLog yet because I wasn't sure it's allowed to change the type of a function like that. If it isn't, what would you suggest

[PATCH] libgccjit: Fix get_size of size_t

Hi. This patch fixes getting the size of size_t (bug 112910). There's one issue with this patch: like every other feature that checks for target-specific stuff, it requires a compilation before actually fetching the size of the type. Which means that getting the size before a compilation might be

[Committed V2] RISC-V: Support interleave vector with different step sequence

This patch fixes 64 ICEs in full coverage testing since they happens due to same reason. Before this patch: internal compiler error: in expand_const_vector, at config/riscv/riscv-v.cc:1270 appears 400 times in full coverage testing report. The root cause is we didn't support interleave vector

Re: [PATCH] treat argp-based mem as frame related in dse

On 12/6/23 02:27, Jiufu Guo wrote: Hi, The issue mentioned in PR112525 would be able to be handled by updating dse.cc to treat arg_pointer_rtx similarly with frame_pointer_rtx. https://gcc.gnu.org/bugzilla/show_bug.cgi?id=30271#c10 also mentioned this idea.

Re: [PATCH v5] Introduce strub: machine-independent stack scrubbing

On Dec 6, 2023, Jan Hubicka wrote: > There is also access attribute which speaks directly about individual > arugments, perhaps you want to drop this one too? Ah, I've looked a little into it, and now I have a vague recollection of why I don't mess with them: they only apply to arguments of poi

Re: [PATCH v5] Introduce strub: machine-independent stack scrubbing

On Dec 6, 2023, Jan Hubicka wrote: > I am sorry for sending this late. No need to be sorry. Thank you very much for taking the time to review and comment on it. > I think the ipa changes are generally fine. Phew :-) >> +static inline bool >> +strub_always_inline_p (cgraph_node *node) >> +{

Re: [PATCH] RISC-V: Fix AVL propagation ICE for vleff/vlsegff

On 12/7/23 05:15, Robin Dapp wrote: LGTM. Btw your vsetvl patch from yesterday fixes the vectorized strlen/strcmp problems. Those use vleff as first instruction. Definitely good news. jeff

Re: [PATCH] testsuite: scev: expect fail on ilp32

On 12/7/23 09:33, Hans-Peter Nilsson wrote: Date: Mon, 4 Dec 2023 12:58:03 +0100 (CET) From: Richard Biener On Sat, 2 Dec 2023, Hans-Peter Nilsson wrote: Date: Fri, 1 Dec 2023 08:07:14 +0100 (CET) From: Richard Biener I read from your messages that the testcases pass on arm*-*-*? Yes: t

Re: [PATCH V2 0/2] RISC-V: Add intrinsics for Bitmanip and Scalar Crypto extensions

On 12/7/23 09:59, Christoph Müllner wrote: On Thu, Dec 7, 2023 at 11:18 AM Liao Shihua wrote: In accordance with the suggestions of Christoph Müllner, the following amendments are made Update v1 -> v2: 1. Rename *_intrinsic-* to *_intrinsic-XLEN. 2. Typo fix. 3. Intrinsics with i

[committed] libstdc++: Fix misleading typedef name in

Tested x86_64-linux. Pushed to trunk. -- >8 -- This local typedef for uintptr_t was accidentally named uint64_t, probably from a careless code completion shortcut. We don't need the typedef at all since it's only used once. Just use __UINTPTR_TYPE__ directly instead. libstdc++-v3/ChangeLog:

[committed] libstdc++: Use instead of in

Tested x86_64-linux. Pushed to trunk. I'll backport this too. -- >8 -- In r14-5922-g6c8f2d3a08bc01 I added to , so that uintptr_t is declared if that header is compiled as a header unit. I used because that's what already includes, so it seemed simpler to be consistent. However, this means tha

[committed] libstdc++: Fix recent changes to __glibcxx_assert [PR112882]

Tested x86_64-linux. Pushed to trunk. -- >8 -- The changes in r14-6198-g5e8a30d8b8f4d7 were broken, as I used _GLIBCXX17_CONSTEXPR for the 'if _GLIBCXX17_CONSTEXPR (true)' condition, forgetting that it would also be used for the is_constant_evaluated() check. Using 'if constexpr (std::is_constant

Re: [PATCH v7] Introduce attribute sym_alias

On Dec 6, 2023, Jan Hubicka wrote: >> On Nov 30, 2023, Jan Hubicka wrote: >> >> >> + if (VAR_P (replaced)) >> >> + varpool_node::create_alias (sym_node->decl, replacement); >> >> + else >> >> + cgraph_node::create_alias (sym_node->decl, replacement); >> >> Unfortunately, this change

[PATCH] RISC-V: XFAIL scan dump fails for autovec PR111311

Clean up scan dump failures Juzhe mentioned could be ignored for now with vector enabled. This will help reduce noise and make it more obvious if a bug or regression is introduced. The failures that are still reported are either execution failures or failures that are also present on armv8-a+sve g

Re: [Committed] RISC-V: Remove xfail from ssa-fre-3.c testcase

Committed! On 12/6/2023 8:22 AM, Palmer Dabbelt wrote: On Tue, 05 Dec 2023 16:39:06 PST (-0800), e...@rivosinc.com wrote: Ran the test case at 122e7b4f9d0c2d54d865272463a1d812002d0a5c where the xfail That's the original port submission, I'm actually kind of surprised it still builds/works at

Re: [PATCH 3/4] libgcc: aarch64: Add SME runtime support

The 12/07/2023 17:36, Richard Sandiford wrote: > Szabolcs Nagy writes: > > + > > +#include "auto-target.h" > > +#include > > + sorry, this seems to fail when building --without-headers i will respin this, handling the 'inhibit_libc' case.

Re: [PING][PATCH 2/2] arm: Add support for MVE Tail-Predicated Low Overhead Loops

Thanks for addressing my comments. I have reviewed this and the other patch before and they LGTM. I however do not have approval rights so you will need the OK from a maintainer. Thanks for doing this :) Andre On 30/11/2023 12:55, Stamatis Markianos-Wright wrote: Hi Andre, Thanks for the co

[PATCH]

On Dec 7, 2023, Thomas Schwinge wrote: > Thank you for looking into this so promptly! You're welcome ;-) > during IPA pass: emutls > [...]/source-gcc/gcc/testsuite/c-c++-common/strub-unsupported-3.c:18:1: > internal compiler error: in verify_curr_properties, at passes.cc:2198 Aah, t

Re: [PATCH v2] ifcvt: Handle multiple rewired regs and refactor noce_convert_multiple_sets

On Thu, Nov 23, 2023 at 11:01 PM Richard Sandiford wrote: > > Manolis Tsamis writes: > > The existing implementation of need_cmov_or_rewire and > > noce_convert_multiple_sets_1 assumes that sets are either REG or SUBREG. > > This commit enchances them so they can handle/rewire arbitrary set > >

Re: [PATCH 3/4] libgcc: aarch64: Add SME runtime support

Szabolcs Nagy writes: > The call ABI for SME (Scalable Matrix Extension) requires a number of > helper routines which are added to libgcc so they are tied to the > compiler version instead of the libc version. See > https://github.com/ARM-software/abi-aa/blob/main/aapcs64/aapcs64.rst#sme-support-r

Re: [PATCH v7 3/5] OpenMP: Pointers and member mappings

Hi Tobias! On Wed, 6 Dec 2023 12:36:34 +0100 Tobias Burnus wrote: > Hi Julian, > > LGTM, except for: > > * The 'target exit data' handling - comments below - looks a bit > fishy/inconsistent. > > I intent to have a closer look with more code context, but maybe you > should have a look at it a

Re: [PATCH 4/5] aarch64: rcpc3: add Neon ACLE wrapper functions to `arm_neon.h'

On Thu, 9 Nov 2023 at 19:44, Victor Do Nascimento wrote: > > Create the necessary mappings from the ACLE-defined Neon intrinsics > names[1] to the internal builtin function names. > > [1] https://arm-software.github.io/acle/neon_intrinsics/advsimd.html Hi Victor, It seems this patch broke kernel b

Re: Several test failures due to "Introduce strub: machine-independent stack scrubbing"

On Dec 7, 2023, FX Coudert wrote: > The commit > https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=f0a90c7d7333fc7f554b906245c84bdf04d716d7 > (Introduce strub: machine-independent stack scrubbing) has introduced > many test failures on x86_64-apple-darwin21: Nevermind, the followup patch I'd sugges

Re: [PATCH] Add support for function attributes and variable attributes

It seems like you forgot to prefix the commit message with "libgccjit: ". On Thu, 2023-11-30 at 10:55 +0100, Guillaume Gomez wrote: > Ping David. :) > > Le jeu. 23 nov. 2023 à 22:59, Antoni Boucher a > écrit : > > David: I found back the comment you made. Here it is: > > > >    I see you have p

Re: Several test failures due to "Introduce strub: machine-independent stack scrubbing"

> However, I'm very surprised that you're hitting this with the initial > commit. It's as if strub support was disabled on the target, but even > if you were hitting this with e.g. offloading, only the followup commit > introduced code to disable strub for such targets as nvptx. Anyway, do > you

Re: [PATCH V2 0/2] RISC-V: Add intrinsics for Bitmanip and Scalar Crypto extensions

On Thu, Dec 7, 2023 at 11:18 AM Liao Shihua wrote: > > In accordance with the suggestions of Christoph Müllner, the following > amendments are made > > Update v1 -> v2: > 1. Rename *_intrinsic-* to *_intrinsic-XLEN. > 2. Typo fix. > 3. Intrinsics with immediate arguments will use marcos at

Re: [ARC PATCH] Add *extvsi_n_0 define_insn_and_split for PR 110717.

On 12/7/23 09:04, Roger Sayle wrote: Hi Jeff, Doh! Great catch. The perils of not (yet) being able to actually run any ARC execution tests myself. ACK. Shouldn't operands[4] be GEN_INT ((HOST_WIDE_INT_1U << tmp) - 1)? Yes(-ish), operands[4] should be GEN_INT(HOST_WIDE_INT_1U << (tmp

[PATCH 4/4] libgcc: aarch64: Add SME unwinder support

To support the ZA lazy save scheme, the PCS requires the unwinder to reset the SME state to PSTATE.SM=0, PSTATE.ZA=0, TPIDR2_EL0=0 on entry to an exception handler. We use the __arm_za_disable SME runtime call unconditionally to achieve this. https://github.com/ARM-software/abi-aa/blob/main/aapcs64

[PATCH 3/4] libgcc: aarch64: Add SME runtime support

The call ABI for SME (Scalable Matrix Extension) requires a number of helper routines which are added to libgcc so they are tied to the compiler version instead of the libc version. See https://github.com/ARM-software/abi-aa/blob/main/aapcs64/aapcs64.rst#sme-support-routines The routines are in sh

[PATCH 2/4] libgcc: aarch64: Configure check for __getauxval

Add configure check for the __getauxval ABI symbol, which is always available on aarch64 glibc, and may be available on other linux C runtimes. For now only enabled on glibc, others have to override it target_configargs=libgcc_cv_have___getauxval=yes This is deliberately obscure as it should be

[PATCH 1/4] libgcc: aarch64: Configure check for .variant_pcs support

Ideally SME support routines in libgcc are marked as variant PCS symbols so check if as supports the directive. --- libgcc/config.in| 3 +++ libgcc/configure| 39 +++ libgcc/configure.ac | 17 + 3 files changed, 59 insertions(+) diff --

[PATCH 0/4] libgcc: aarch64: Add SME runtime

Add SME (Scalable Matrix Extension) support to libgcc. Szabolcs Nagy (4): libgcc: aarch64: Configure check for .variant_pcs support libgcc: aarch64: Configure check for __getauxval libgcc: aarch64: Add SME runtime support libgcc: aarch64: Add SME unwinder support libgcc/config.in

Re: Several test failures due to "Introduce strub: machine-independent stack scrubbing"

On Dec 7, 2023, FX Coudert wrote: > The commit > https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=f0a90c7d7333fc7f554b906245c84bdf04d716d7 > (Introduce strub: machine-independent stack scrubbing) has introduced > many test failures on x86_64-apple-darwin21: Please give the followup commit f908368d

Re: [PATCH v2 0/3] [GCC] arm: vld1_types_xN ACLE intrinsics

Pushed, thanks. R. On 07/12/2023 15:41, ezra.sito...@arm.com wrote: Add xN variants of vld1_types intrinsic.

Re: [PATCH v2 0/3] [GCC] arm: vst1q_types_xN ACLE intrinsics

Pushed, thanks. R. On 07/12/2023 15:36, ezra.sito...@arm.com wrote: Add xN variants of vst1q_types intrinsic.

Re: [PATCH] strub: enable conditional support

Hi Alexandre! Thank you for looking into this so promptly! On 2023-12-07T00:33:59-0300, Alexandre Oliva wrote: > On Dec 6, 2023, Alexandre Oliva wrote: > >> Disabling the runtime bits is easy, once we determine what condition we >> wish to test for. I suppose testing for target support in the

Re: [PATCH v2 0/3] [GCC] arm: vst1_types_xN ACLE intrinsics

Pushed, thanks. R. On 07/12/2023 15:28, ezra.sito...@arm.com wrote: Add xN variants of vst1_types intrinsic.

Re: [PATCH] testsuite: adjust call to abort in excess-precision-12

On Thu, Dec 07, 2023 at 05:27:28PM +0100, Marc Poulhiès wrote: > abort() is not always available, using the builtin as done in other > tests. > > gcc/testsuite/ChangeLog: > > * g++.target/i386/excess-precision-12.C: call builtin_abort instead of > abort. > --- > Tested on x86_64-linux and

Re: [PATCH] testsuite: require avx_runtime for vect-simd-clone-17f

On Thu, Dec 07, 2023 at 05:28:09PM +0100, Marc Poulhiès wrote: > The test fails parsing the 'vect' dump when not using -mavx. Make the > dependency explicit. > > gcc/testsuite/ChangeLog: > > * gcc.dg/vect/vect-simd-clone-17f.c: Add dep on avx_runtime. > --- > Tested on x86_64-linux and x86_

Re: [PATCH] testsuite: add missing dg-require ifunc in pr105554.c

On Thu, Dec 07, 2023 at 05:25:39PM +0100, Marc Poulhiès wrote: > The 'target_clones' attribute depends on the ifunc support. > > gcc/testsuite/ChangeLog: > * gcc.target/i386/pr105554.c: Add dg-require ifunc. > --- > Tested on x86_64-linux and x86_64-elf. > > Ok for master? > > gcc/testsui

Re: [PATCH] testsuite: scev: expect fail on ilp32

> Date: Mon, 4 Dec 2023 12:58:03 +0100 (CET) > From: Richard Biener > On Sat, 2 Dec 2023, Hans-Peter Nilsson wrote: > > > Date: Fri, 1 Dec 2023 08:07:14 +0100 (CET) > > > From: Richard Biener > > > I read from your messages that the testcases pass on arm*-*-*? > > Yes: they pass (currently XPASS

[PATCH] testsuite: require avx_runtime for vect-simd-clone-17f

The test fails parsing the 'vect' dump when not using -mavx. Make the dependency explicit. gcc/testsuite/ChangeLog: * gcc.dg/vect/vect-simd-clone-17f.c: Add dep on avx_runtime. --- Tested on x86_64-linux and x86_64-elf. Ok for master? gcc/testsuite/gcc.dg/vect/vect-simd-clone-17f.c | 3

[PATCH] testsuite: adjust call to abort in excess-precision-12

abort() is not always available, using the builtin as done in other tests. gcc/testsuite/ChangeLog: * g++.target/i386/excess-precision-12.C: call builtin_abort instead of abort. --- Tested on x86_64-linux and x86_64-elf. Ok for master? gcc/testsuite/g++.target/i386/excess-precision-12

[PATCH] testsuite: add missing dg-require ifunc in pr105554.c

The 'target_clones' attribute depends on the ifunc support. gcc/testsuite/ChangeLog: * gcc.target/i386/pr105554.c: Add dg-require ifunc. --- Tested on x86_64-linux and x86_64-elf. Ok for master? gcc/testsuite/gcc.target/i386/pr105554.c | 1 + 1 file changed, 1 insertion(+) diff --git a

Re: [PATCH] aarch64: add -fno-stack-protector to tests

On Thu, Dec 07, 2023 at 04:05:47PM +, Richard Sandiford wrote: > Marek Polacek writes: > > Bootstrapped/regtested on aarch64-pc-linux-gnu, ok for trunk/13? > > > > -- >8 -- > > These tests fail when the testsuite is executed with > > -fstack-protector-strong. > > To avoid this, this patch add

Re: [PATCH] aarch64: add -fno-stack-protector to tests

Marek Polacek writes: > Bootstrapped/regtested on aarch64-pc-linux-gnu, ok for trunk/13? > > -- >8 -- > These tests fail when the testsuite is executed with -fstack-protector-strong. > To avoid this, this patch adds -fno-stack-protector to dg-options. > > The list of FAILs is appended. As you can

Re: [PATCH] driver: Fix memory leak.

On Thu, Dec 07, 2023 at 04:01:11PM +, Costas Argyris wrote: > Thanks for all the explanations. > > In that case I restrict this patch to just freeing the buffer from > within driver::finalize only (I think it should be XDELETEVEC > instead of XDELETE, no?). Both macros are exactly the same, b

RE: [ARC PATCH] Add *extvsi_n_0 define_insn_and_split for PR 110717.

Hi Jeff, Doh! Great catch. The perils of not (yet) being able to actually run any ARC execution tests myself. > Shouldn't operands[4] be GEN_INT ((HOST_WIDE_INT_1U << tmp) - 1)? Yes(-ish), operands[4] should be GEN_INT(HOST_WIDE_INT_1U << (tmp - 1)). And the 32s in the test cases need to be 16

Re: [PATCH] driver: Fix memory leak.

Thanks for all the explanations. In that case I restrict this patch to just freeing the buffer from within driver::finalize only (I think it should be XDELETEVEC instead of XDELETE, no?). On Thu, 7 Dec 2023 at 15:42, Jakub Jelinek wrote: > On Thu, Dec 07, 2023 at 03:16:29PM +, Costas Argyri

Re: [PATCH] c-family: Fix up -fno-debug-cpp [PR111965]

On Thu, Dec 07, 2023 at 08:53:37AM +0100, Jakub Jelinek wrote: > Hi! > > As can be seen in the second testcase, -fno-debug-cpp is actually > implemented the same as -fdebug-cpp and so doesn't turn the debugging > off. > > The following patch fixes that. > > Bootstrapped/regtested on x86_64-linux

[PATCH V3 3/4] OpenMP: Use enumerators for names of trait-sets and traits

This patch introduces enumerators to represent trait-set names and trait names, which makes it easier to use tables to control other behavior and for switch statements to dispatch on the tags. The tags are stored in the same place in the TREE_LIST structure (OMP_TSS_ID or OMP_TS_ID) and are encode

[PATCH V3 4/4] OpenMP: Permit additional selector properties

This patch adds "hpe" to the known properties for the "vendor" selector, and support for "acquire" and "release" for "atomic_default_mem_order". gcc/ChangeLog * omp-general.cc (vendor_properties): Add "hpe". (atomic_default_mem_order_properties): Add "acquire" and "release".

[PATCH V3 1/4] OpenMP: Introduce accessor macros and constructors for context selectors.

This patch hides the underlying nested TREE_LIST structure of context selectors behind accessor macros that have more meaningful names than the generic TREE_PURPOSE/TREE_VALUE accessors. There is a slight change to the representation in that the score expression in trait-selectors has a distinguis

[PATCH V3 2/4] OpenMP: Unify representation of name-list properties.

Previously, name-list properties specified as identifiers were stored in the TREE_PURPOSE/OMP_TP_NAME slot, while those specified as strings were stored in the TREE_VALUE/OMP_TP_VALUE slot. This patch puts both representations in OMP_TP_VALUE with a magic cookie in OMP_TP_NAME. gcc/ChangeLog

[PATCH V3 0/4] OpenMP: Improve data abstractions for context selectors

Here is a new version of my context selector implementation cleanup patch set, incorporating comments from Tobias on V2 of part 3. Parts 1 and 2 are unchanged from V1 except that I rebased them so they should apply cleanly to mainline head now. There's a new part 4 that adds new functionality, ha

Re: [gcc15] nested functions in C

On 2023-12-07 10:42, Eric Botcazou wrote: I think from a language standpoint, the general idea that nested functions are just any functions inside functions (which is how the C nested functions essentially behave) is too broad and they should be restricted to minimal implementations that, e.g. do

Re: [PATCH] driver: Fix memory leak.

On Thu, Dec 07, 2023 at 03:16:29PM +, Costas Argyris wrote: > > Still reachable memory at exit e.g. from valgrind is not a bug. > > Indeed, this is coming from a valgrind report here: > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93019 > > where it was noted that the driver memory leaks

Re: [gcc15] nested functions in C

> I think from a language standpoint, the general idea that nested > functions are just any functions inside functions (which is how the C > nested functions essentially behave) is too broad and they should be > restricted to minimal implementations that, e.g. don't have side-effects > or if they d

[PATCH v2 1/3] [GCC] arm: vld1_types_x2 ACLE intrinsics

From: Ezra Sitorus This patch is part of a series of patches implementing the _xN variants of the vld1 intrinsic for the arm port. This patch adds the _x2 variants of the vld1 intrinsic. The previous vld1_x2 has been updated to vld1q_x2 to take into account that it works with 4-word-length types

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