On Thu, 16 Nov 2023, Jason Merrill wrote:
> On 10/30/23 08:57, Richard Biener wrote:
> > We have a support case that shows GCC 7 sometimes creates
> > DW_TAG_label refering to itself via a DW_AT_abstract_origin
> > when using LTO. This for example triggers the sanity check
> > added below during
On Thu, 16 Nov 2023, Martin Jambor wrote:
> Hello,
>
> PR109849 shows that a loop that heavily pushes and pops from a stack
> implemented by a C++ std::vec results in slow code, mainly because the
> vector structure is not split by SRA and so we end up in many loads
> and stores into it. This is
Hello Richard:
This patch does decision making in code sinking considers the following
decision.
High register pressure region is true if the following criteria
satisfied.
a) If liveout (early_bb) <= livein (early_bb).
b) if liveout (best_bb) <= liveout (early_bb).
c) !best_bb->count >= early_bb
Fix segment fault on tuple move:
bbl loader
z ra 000102ac sp 003ffaf0 gp 0001c0b8
tp t0 000104a0 t1 000f t2
s0 s1 a0 003ffb30 a1 003ffb58
a2 000
The XTheadInt ISA extension provides acceleration interruption
instructions as defined in T-Head-specific:
* th.ipush
* th.ipop
Ref:
https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf
gcc/ChangeLog:
* config/riscv/riscv-protos.h (th_in
Hello Richard:
On 16/11/23 3:28 pm, Richard Biener wrote:
> On Mon, Oct 30, 2023 at 1:10 PM Ajit Agarwal wrote:
>>
>> Hello Richard:
>>
>> Currently, code sinking will sink code at the use points with loop having
>> same
>> nesting depth. The following patch improves code sinking by placing the
Intel APX PPX feature has been released in [1].
PPX stands for Push-Pop Acceleration. PUSH/PUSH2 and its corresponding POP
can be marked with a 1-bit hint to indicate that the POP reads the
value written by the PUSH from the stack. The processor tracks these marked
instructions internally and fast
Hello Richard:
Currently, code sinking will sink code at the use points with loop having same
nesting depth. The following patch improves code sinking by placing the sunk
code in immediate dominator with same loop nest depth.
Review comments are incorporated.
For example :
void bar();
int j;
vo
gcc/ChangeLog:
* config/loongarch/loongarch.cc: Do not restore the saved eh_return
data registers ($r4-$r7) for a normal return of a function that calls
__builtin_eh_return elsewhere.
* config/loongarch/loongarch-protos.h: Same.
* config/loongarch/loongarch.
在 2023/11/17 下午12:55, Xi Ruoyao 写道:
On Fri, 2023-11-17 at 10:41 +0800, chenglulu wrote:
Hi,
Thank you very much for the modification, but I think we need to support
la664 with the configuration items of configure.
I'll add it.
I also defined ISA_BASE_LA64V110 to represent the LoongArch1.1
From: xuli
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112537
-mmemcpy-strategy=[auto|libcall|scalar|vector]
auto: Current status, use scalar or vector instructions.
libcall: Always use a library call.
scalar: Only use scalar instructions.
vector: Only use vector instructions.
PR targ
The missing cbranchv*{hi,qi}4 maybe needed by early break vectorization.
Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
Ready push to trunk.
gcc/ChangeLog:
* config/i386/sse.md (cbranch4): Extend to Vector
HI/QImode.
---
gcc/config/i386/sse.md | 10 --
1 file
Resent as plain text to appear on the patch tracker
Hi all,
This is the beginning of a patch to introduce the extended attribute
for asm declarations proposed in
https://gcc.gnu.org/pipermail/gcc-patches/2023-November/636563.html. I
will need some reviewer help in implementing this patch, as I am
On Fri, 2023-11-17 at 10:41 +0800, chenglulu wrote:
> Hi,
>
> Thank you very much for the modification, but I think we need to support
> la664 with the configuration items of configure.
I'll add it.
> I also defined ISA_BASE_LA64V110 to represent the LoongArch1.1
> instruction set, what do you
> From: Jonathan Wakely
> Date: Thu, 16 Nov 2023 08:12:39 +
> PR libstdc++/111667
> * include/Makefile.am: Add new header.
> * include/Makefile.in: Regenerate.
> * include/bits/out_ptr.h: New file.
> * include/bits/shared_ptr.h (__is_shared_ptr): Move definition
When evaluating dynamic LMUL, notice we can do better on VLA SLP with duplicate
VLA shuffle indice.
Consider this following case:
void
foo (uint16_t *restrict a, uint16_t *restrict b, int n)
{
for (int i = 0; i < n; ++i)
{
a[i * 8] = b[i * 8 + 3] + 1;
a[i * 8 + 1] = b[i * 8 + 6
Hi all,
This is the beginning of a patch to introduce the extended attribute
for asm declarations proposed in
https://gcc.gnu.org/pipermail/gcc-patches/2023-November/636563.html. I
will need some reviewer help in implementing this patch, as I am not
very familiar with gcc's internals.
The attribu
On 11/16/23 18:20, Sam James wrote:
Jeff, I don't suppose you could dig out the old bugs/commits just out of
interest?
That work goes back to the early 90s when I was primarily responsible
for the PA platform. But the core issue hasn't changed in that not
enough context is provided for re
This adds initial support for function multiversioning on aarch64 using
the target_version and target_clones attributes. This loosely follows
the Beta specification in the ACLE [1], although with some differences
that still need to be resolved (possibly as follow-up patches).
Existing function mu
This patch adds support for the "target_version" attribute to the middle
end and the C++ frontend, which will be used to implement function
multiversioning in the aarch64 backend.
On targets that don't use the "target" attribute for multiversioning,
there is no conflict between the "target" and "t
Change the handling of some attribute mutual exclusions to use the
generic attribute exclusion lists, and fix some asymmetric exclusions by
adding the exclusions for always_inline after noinline or target_clones.
Aside from the new always_inline exclusions, the only change is
functionality is the
This patch changes the handling of mutual exclusions involving the
target and target_clones attributes to use the generic attribute
exclusion lists. Additionally, the duplicate handling for the
always_inline and noinline attribute exclusion is removed.
The only change in functionality is the choi
This is added to enable function multiversioning, but can also be used
directly. The interface is chosen to match that used in LLVM's
compiler-rt, to facilitate cross-compiler compatibility.
The content of the patch is derived almost entirely from Pavel's prior
contributions to compiler-rt/lib/bu
This series adds support for function multiversioning on aarch64.
Patch 1/5 is a repost of my copy of Pavel's aarch64 cpu feature detection code
to libgcc. This is slightly refactored in a later patch, but I've preserved
this patch as-is to make the attribution clearer.
Patches 2/5 and 3/5 are mi
Hi,
Thank you very much for the modification, but I think we need to support
la664 with the configuration items of configure.
I also defined ISA_BASE_LA64V110 to represent the LoongArch1.1
instruction set, what do you think?
在 2023/11/16 下午9:18, Xi Ruoyao 写道:
Loongson 3A6000 processor wil
The LoongArch has defined ctz and clz on the backend, but if we want GCC
do CTZ transformation optimization in forwprop2 pass, GCC need to know
the value of c[lt]z at zero, which may be beneficial for some test cases
(like spec2017 deepsjeng_r).
After implementing the macro, we test dynamic instru
Pushed to r14-5544
在 2023/11/16 下午8:31, Jiahao Xu 写道:
These tests fail when they are first added,this patch adjusts the
scan-assembler-times
to fix them.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/vector/lasx/lasx-vcond-1.c: Adjust assembler
times.
* gcc.target/loongarch
Pushed to r14-5545.
在 2023/11/16 下午4:44, Jiahao Xu 写道:
Based on SPEC2017 performance evaluation results, it's better to make them equal
to the cost of unaligned store/load so as to avoid odd alignment peeling.
gcc/ChangeLog:
* config/loongarch/loongarch.cc
(loongarch_builtin_ve
Hi Vladimir,
Thank you so much for your review. Based on your comments, I feel like
there are a lot of issues, especially the long compile time issue. So
I'm going to reorganize and refactor the patches so that as many of them
as possible can be reviewed separately. this way there will be fewe
The following functions invoke signed integer overflow (UB) for some extreme
values of days and months [1]:
weekday operator+(const weekday& x, const days& y); // #1
month operator+(const month& x, const months& y); // #2
For #1, the crux of the problem is that, in libstdc++, days::rep is i
Sam James writes:
> John David Anglin writes:
>
>> On 2023-11-16 4:52 p.m., Jeff Law wrote:
>>>
>>>
>>> On 11/16/23 10:54, John David Anglin wrote:
Tested on hppa-unknown-linux-gnu and hppa64-hp-hpux11.11. Committed
to trunk.
This patch works around problem compiling pytho
John David Anglin writes:
> On 2023-11-16 4:52 p.m., Jeff Law wrote:
>>
>>
>> On 11/16/23 10:54, John David Anglin wrote:
>>> Tested on hppa-unknown-linux-gnu and hppa64-hp-hpux11.11. Committed
>>> to trunk.
>>>
>>> This patch works around problem compiling python3.11 by improving
>>> REG+D ad
So looking for thoughts from the community on this one
Let's take this RTL:
(insn 10 9 11 2 (set (reg:SI 144)
(unspec_volatile [
(const_int 0 [0])
] UNSPECV_FRFLAGS)) "j.c":11:3 discrim 1 362 {riscv_frflags}
(nil))
(insn 11 10 55 2 (set (reg:DI 140
On Thu, Nov 16, 2023 at 7:07 PM Bruno Haible wrote:
> David Edelsohn wrote:
> > > ibm-clang links against libpthread.a as well:
> > > $ ldd /opt/IBM/openxlC/17.1.1/bin/.ibm-clang.orig
> > > /opt/IBM/openxlC/17.1.1/bin/.ibm-clang.orig needs:
> > > /usr/lib/libpthreads.a(shr_xp
BB vectorizer relies on the backend support of
.REDUC_{PLUS,IOR,XOR,AND} to vectorize reduction.
Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
Ready push to trunk.
gcc/ChangeLog:
PR target/112325
* config/i386/sse.md (reduc__scal_): New expander.
(REDUC_ANY_LO
x86 backend support reduc_{and,ior,xor>_scal_m for vector integer
modes.
Ok for trunk?
gcc/testsuite/ChangeLog:
* lib/target-supports.exp (vect_logical_reduc): Add i?86-*-*
and x86_64-*-*.
---
gcc/testsuite/lib/target-supports.exp | 3 ++-
1 file changed, 2 insertions(+), 1 dele
David Edelsohn wrote:
> > ibm-clang links against libpthread.a as well:
> > $ ldd /opt/IBM/openxlC/17.1.1/bin/.ibm-clang.orig
> > /opt/IBM/openxlC/17.1.1/bin/.ibm-clang.orig needs:
> > /usr/lib/libpthreads.a(shr_xpg5_64.o)
> > /usr/opt/zlibNX/lib/libz.a(libz.so.1)
> >
On Thu, Nov 16, 2023 at 5:52 PM Arsen Arsenović wrote:
>
> David Edelsohn writes:
>
> > On Thu, Nov 16, 2023 at 5:22 PM Arsen Arsenović wrote:
> >
> >>
> >> David Edelsohn writes:
> >>
> >> > Don't build with the dependent libraries in tree. Don't build the
> >> > dependent libraries as share
On Thu, 16 Nov 2023, Jason Merrill wrote:
> On 11/11/23 03:22, Jakub Jelinek wrote:
> > Hi!
> >
> > While filing a clang request to return 18 on _BitInts for
> > __builtin_classify_type instead of -1 they return currently, I've
> > noticed that we return -1 for vector types. I'm not convinced it
On Thu, Nov 16, 2023 at 5:47 PM Bruno Haible wrote:
> Hi David,
>
> > the default, distributed libintl library will not allow GCC to be built
> > with NLS enabled.
>
> The problem is this configure test from gettext.m4
>
> checking for GNU gettext in libintl... no
>
> It should say
>
> checki
Bruno Haible writes:
> Hi David,
>
>> the default, distributed libintl library will not allow GCC to be built
>> with NLS enabled.
>
> The problem is this configure test from gettext.m4
>
> checking for GNU gettext in libintl... no
>
> It should say
>
> checking for GNU gettext in libintl...
David Edelsohn writes:
> On Thu, Nov 16, 2023 at 5:22 PM Arsen Arsenović wrote:
>
>>
>> David Edelsohn writes:
>>
>> > Don't build with the dependent libraries in tree. Don't build the
>> > dependent libraries as shared libraries. The libraries are already built
>> > and in /opt/cfarm, as men
Hi David,
> the default, distributed libintl library will not allow GCC to be built
> with NLS enabled.
The problem is this configure test from gettext.m4
checking for GNU gettext in libintl... no
It should say
checking for GNU gettext in libintl... yes
I reproduce it with simple hello-wo
Hi.
This patch fixes a RTL bug when using some target-specific builtins in
libgccjit (bug 112576).
The test use a function from an unmerged patch:
https://gcc.gnu.org/pipermail/jit/2023q1/001605.html
Thanks for the review!
From 9236998f5ad3156ebe39e97c03d1a28ce80dd95a Mon Sep 17 00:00:00 2001
Fro
On 2023-11-16 4:52 p.m., Jeff Law wrote:
On 11/16/23 10:54, John David Anglin wrote:
Tested on hppa-unknown-linux-gnu and hppa64-hp-hpux11.11. Committed
to trunk.
This patch works around problem compiling python3.11 by improving
REG+D address handling. The change results in smaller code and
On Thu, Nov 16, 2023 at 5:22 PM Arsen Arsenović wrote:
>
> David Edelsohn writes:
>
> > Don't build with the dependent libraries in tree. Don't build the
> > dependent libraries as shared libraries. The libraries are already built
> > and in /opt/cfarm, as mentioned in the Compile Farm wiki.
>
> For the fortran testcase we don't even run into this but hit an
> internal def and assert on
>
> gcc_assert (STMT_VINFO_VEC_STMTS (def_stmt_info).length () == ncopies);
>
> I think this shows missing handling of .COND_* in the bool pattern recognition
> as we get the 'bool' condition as b
Hi.
This patch fixes a segfault that happens when compiling librsvg (more
specifically its dependency aho-corasick) with rustc_codegen_gcc (bug
112575).
I was not able to create a reproducer for this bug: I'm assuming I
might need to concat all the reproducers together in the same file in
order to
David Edelsohn writes:
> Don't build with the dependent libraries in tree. Don't build the
> dependent libraries as shared libraries. The libraries are already built
> and in /opt/cfarm, as mentioned in the Compile Farm wiki.
>
> AIX is not Solaris and not Linux. It doesn't use ELF. AIX share
I forgot to attach the patch.
On Thu, 2023-11-16 at 17:19 -0500, Antoni Boucher wrote:
> Hi.
> This patch adds the support for the type bfloat16 (bug 112574).
>
> This was asked to be splitted from a another patch sent here:
> https://gcc.gnu.org/pipermail/jit/2023q1/001607.html
>
> Thanks for t
Hi.
This patch adds the support for the type bfloat16 (bug 112574).
This was asked to be splitted from a another patch sent here:
https://gcc.gnu.org/pipermail/jit/2023q1/001607.html
Thanks for the review.
On Thu, Nov 16, 2023 at 1:52 PM Bruno Haible wrote:
> David Edelsohn wrote:
> > I manually commented out HAVE_PTHREAD_API from config.h and produced a
> > libintl.a without references to pthreads.
>
> Good finding!
>
> Commenting out HAVE_PTHREAD_API from config.h is also what makes the
> option
On 11/11/23 03:22, Jakub Jelinek wrote:
Hi!
While filing a clang request to return 18 on _BitInts for
__builtin_classify_type instead of -1 they return currently, I've
noticed that we return -1 for vector types. I'm not convinced it is a good
idea to change behavior of __builtin_classify_type (
On 11/16/23 10:54, John David Anglin wrote:
Tested on hppa-unknown-linux-gnu and hppa64-hp-hpux11.11. Committed
to trunk.
This patch works around problem compiling python3.11 by improving
REG+D address handling. The change results in smaller code and
reduced register pressure.
Dave
---
hp
Don't build with the dependent libraries in tree. Don't build the
dependent libraries as shared libraries. The libraries are already built
and in /opt/cfarm, as mentioned in the Compile Farm wiki.
AIX is not Solaris and not Linux. It doesn't use ELF. AIX shared
libraries *ARE* shared object fil
Support for constructing composite type for structs and unions
in C23.
gcc/c:
* c-typeck.cc (composite_type_internal): Adapted from
composite_type to support structs and unions.
(composite_type): New wrapper function.
(build_conditional_operator): Return compo
Bootstrapped and regtested on x86_64-pc-linux-gnu. I don't have write
access.
-- >8 --
Modules streaming requires DECL_CONTEXT to be set on declarations that
are streamed. This ensures that __cxa_thread_atexit is given translation
unit context much like is already done with many other support
fun
Tell the backend which types are equivalent by setting
TYPE_CANONICAL to one struct in the set of equivalent
structs. Structs are considered equivalent by ignoring
all sizes of arrays nested in types below field level.
gcc/c:
* c-decl.cc (c_struct_hasher): Hash stable for struct
Allow redefinition of enum types and enumerators. Diagnose
nested redefinitions including redefinitions in the enum
specifier for enum types with fixed underlying type.
gcc/c:
* c-tree.h (c_parser_enum_specifier): Add parameter.
* c-decl.cc (start_enum): Allow redefinition.
Implement redeclaration and compatibility rules for
structures and unions in C23.
gcc/c/:
* c-decl.cc (previous_tag): New function.
(get_parm_info): Turn off warning for C2X.
(start_struct): Allow redefinitons.
(finish_struct): Diagnose conflicts.
* c-tre
Joseph,
this is another revised series for the C23 rules for type
compatibility.
1/4 c23: tag compatibility rules for struct and unions
2/4 c23: tag compatibility rules for enums
3/4 c23: aliasing of compatible tagged types
4/4 c23: construct composite type for tagged types
The first two were
Arsen Arsenović writes:
> [[PGP Signed Part:Good signature from 52C294301EA2C493 Arsen Arsenović
> (Gentoo Developer UID) (trust ultimate) created at
> 2023-11-16T19:47:16+0100 using EDDSA]]
>
> David Edelsohn writes:
>
>> On Wed, Nov 15, 2023 at 9:22 AM Arsen Arsenović wrote:
>>
>>>
>>> Da
On 11/12/23 07:08, Lehua Ding wrote:
This patch relax the subreg track capability to all subreg registers.
The patch is ok for me when general issues I mentioned in my first email
and the issue given below are fixed.
gcc/ChangeLog:
* ira-build.cc (get_reg_unit_size): New.
(ha
On 10/30/23 08:57, Richard Biener wrote:
We have a support case that shows GCC 7 sometimes creates
DW_TAG_label refering to itself via a DW_AT_abstract_origin
when using LTO. This for example triggers the sanity check
added below during LTO bootstrap.
Making this check cover more than just DW_A
On 11/12/23 07:08, Lehua Ding wrote:
This patch changes the previous way of creating a copy between allocnos to
objects.
gcc/ChangeLog:
* ira-build.cc (find_allocno_copy): Removed.
(find_object): New.
(ira_create_copy): Adjust.
(add_allocno_copy_to_list): Adju
On 13 Nov 2023, at 16:18, Arnaud Charlet wrote:
>
> OK, I thought there would be some defines that we could use for that, too
> bad if there isn't
> and indeed we might need to perform another runtime check then as
> suggested by Iain.
I can see a possible interface,
On Wed, Nov 15, 2023 at 01:25:27PM +0100, Jakub Jelinek wrote:
> On Fri, Nov 03, 2023 at 06:51:16PM -0400, Marek Polacek wrote:
> > + if (flag_hardened)
> > + {
> > + if (!fortify_seen_p && optimize > 0)
> > + {
> > + if (TARGET_GLIBC_MAJOR == 2 && TARGET_GLIBC_MINOR >= 35)
On Thu, 16 Nov 2023 at 13:49, Jonathan Wakely wrote:
>
> From: Thomas Rodgers
>
> These two patches were written by Tom earlier this year, before he left
> Red Hat. We should finish reviewing them for GCC 14 (and probably squash
> them into one?)
>
> Tom, you mentioned further work that changes t
Hi Tobias,
On 11/16/23 14:01, Tobias Burnus wrote:
This adds -std=f2023, which is mostly a prep patch for future changes.
However, Fortran 2023, https://j3-fortran.org/doc/year/23/23-007r1.pdf
changes two things which is taken
care in this patch:
(A) In "6.3.2.1 Free form line length":
Fortra
Bruno Haible writes:
> Arsen Arsenović wrote:
>> > * If yes, then the question is how distributors will in general package
>> > libintl on AIX. If it's installed in public locations (such as in
>> > /opt/freeware/{lib,lib64}/libintl.a on gcc119.fsffrance.org), then we
>> > have a p
Arsen Arsenović wrote:
> > * If yes, then the question is how distributors will in general package
> > libintl on AIX. If it's installed in public locations (such as in
> > /opt/freeware/{lib,lib64}/libintl.a on gcc119.fsffrance.org), then we
> > have a problem: It may cause undefined
David Edelsohn wrote:
> I manually commented out HAVE_PTHREAD_API from config.h and produced a
> libintl.a without references to pthreads.
Good finding!
Commenting out HAVE_PTHREAD_API from config.h is also what makes the
option --enable-threads=isoc work as expected on AIX 7.3.
Bruno
Bruno Haible writes:
> David Edelsohn wrote:
>> > It is great that gettext and libintl can be built thread-safe, but GCC
>> > (cc1, gcov, etc.) are not pthreads applications and are not built with
>> > pthreads. Because libintl defaults to pthreads enabled, NLS cannot
>> > function in GCC on AI
Xi Ruoyao writes:
> On Wed, 2023-11-15 at 15:14 +0100, Arsen Arsenović wrote:
>> That is interesting. They should be using the same checks. I've
>> checked trunk and regenerated files on it, and saw no significant diff
>> (some whitespace changes only). Could you post the config.log of
>> bot
David Edelsohn wrote:
> > It is great that gettext and libintl can be built thread-safe, but GCC
> > (cc1, gcov, etc.) are not pthreads applications and are not built with
> > pthreads. Because libintl defaults to pthreads enabled, NLS cannot
> > function in GCC on AIX by default.
> ...
> The la
David Edelsohn writes:
> On Wed, Nov 15, 2023 at 9:22 AM Arsen Arsenović wrote:
>
>>
>> David Edelsohn writes:
>>
>> > GCC had been working on AIX with NLS, using "--with-included-gettext".
>> > --disable-nls gets past the breakage, but GCC does not build for me on
>> AIX
>> > with NLS enabled
> -Original Message-
> From: Tamar Christina
> Sent: Thursday, November 16, 2023 3:19 PM
> To: Richard Biener
> Cc: gcc-patches@gcc.gnu.org; nd ; j...@ventanamicro.com
> Subject: RE: [PATCH 7/21]middle-end: update IV update code to support early
> breaks and arbitrary exits
>
> > -Or
Committed!
On 11/15/2023 11:34 PM, Kito Cheng wrote:
ohhh, thanks for fixing that, LGTM!
On Thu, Nov 16, 2023 at 7:31 AM Edwin Lu wrote:
Fix __riscv_unaligned_fast/slow/avoid macro name to
__riscv_misaligned_fast/slow/avoid to be consistent with the RISC-V API Spec
gcc/ChangeLog:
*
I manually commented out HAVE_PTHREAD_API from config.h and produced a
libintl.a without references to pthreads. Configuring GCC with that custom
libintl.a enables NLS. I now am building GCC with NLS and we will see how
well it functions.
gettext depends on pthreads by default and the versions d
Sometimes the compiler emits the following code with qi_ext_0:
shrl$8, %eax
addb%bh, %al
Patch introduces new low part QImode insn patterns with both of
their input arguments extracted from high register. This invalid
insn is split after reload to a move from the high reg
This patch adjusts the mem{cpy,set} expansion in the aarch64 backend to use
individual loads/stores instead of ldp/stp at expand time. The idea is to rely
on the ldp fusion pass to fuse the accesses together later in the RTL pipeline.
The earlier parts of the RTL pipeline should be able to do a b
This is a v3 of the aarch64 load/store pair fusion pass.
v2 was posted here:
- https://gcc.gnu.org/pipermail/gcc-patches/2023-October/633601.html
The main changes since v2 are as follows:
We now handle writeback opportunities as well. E.g. for this testcase:
void foo (long *p, long *q, long x,
This patch overhauls the load/store pair patterns with two main goals:
1. Fixing a correctness issue (the current patterns are not RA-friendly).
2. Allowing more flexibility in which operand modes are supported, and which
combinations of modes are allowed in the two arms of the load/store pair,
Thus far the writeback forms of ldp/stp have been exclusively used in
prologue and epilogue code for saving/restoring of registers to/from the
stack.
As such, forms of ldp/stp that weren't needed for prologue/epilogue code
weren't supported by the aarch64 backend. This patch generalizes the
load/
Later patches allow using SVE modes in ldp/stp with -msve-vector-bits=128,
so we need to make sure that we don't use SVE addressing modes when
printing the address for the ldp/stp.
This patch does that.
Bootstrapped/regtested as a series on aarch64-linux-gnu, OK for trunk?
gcc/ChangeLog:
This adjusts aarch64_print_operand to recognize zero rtxes in modes other than
VOIDmode. This allows us to use xzr/wzr for zero vectors, for example.
Bootstrapped/regtested as a series on aarch64-linux-gnu, OK for trunk?
gcc/ChangeLog:
* config/aarch64/aarch64.cc (aarch64_print_operand)
For the ret function, allow the loads to be emitted in either order in
the codegen. The order gets inverted with the new load/store pair pass.
OK for trunk?
gcc/testsuite/ChangeLog:
* g++.target/aarch64/pr103147-10.C (ret): Allow loads in either order.
* gcc.target/aarch64/pr103
Later patches in the series allow ldp and stp to use SVE modes if
-msve-vector-bits=128 is provided. This patch therefore adjusts tests
that pass -msve-vector-bits=128 to allow ldp/stp to save/restore SVE
registers.
OK for trunk?
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/sve/pcs/sta
The tests currently depending on memcpy lowering forming stps at -O0,
but we no longer want to form stps during memcpy lowering, but instead
in the load/store pair fusion pass.
This patch therefore tweaks affected tests to enable optimizations
(-O1), and adjusts the tests to avoid parts of the str
This adds some helpers to access-utils.h for removing accesses from an
access_array. This is needed by the upcoming aarch64 load/store pair
fusion pass.
Bootstrapped/regtested as a series on aarch64-linux-gnu, OK for trunk?
gcc/ChangeLog:
* rtl-ssa/access-utils.h (filter_accesses): New.
N.B. this is just a rebased (but otherwise unchanged) version of the
same patch already posted here:
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/633348.html
this is the only unreviewed dependency from the previous series, so it
seemed easier just to re-post it (not least to appease the
Hi,
This patch series reworks the load/store pair representation in the aarch64
backend and adds a new load/store pair fusion pass.
Patch 1/11 is just a rebased version of the patch from the previous version of
the series to add support to RTL-SSA for inserting new insns.
Patch 2/11 adds some RT
Bruno,
The issue appears to be that intl/gnulib-lib/{mbrtowc.c,setlocale_null.c}
include pthread.h based on HAVE_PTHREAD_API, which is defined as 1 in
intl/config.h build directory despite requesting --disable-pthreads.
Thanks, David
On Thu, Nov 16, 2023 at 11:35 AM David Edelsohn wrote:
> I c
Tested on hppa-unknown-linux-gnu and hppa64-hp-hpux11.11. Committed
to trunk.
This patch works around problem compiling python3.11 by improving
REG+D address handling. The change results in smaller code and
reduced register pressure.
Dave
---
hppa: Revise REG+D address support to allow long di
On Thu, Nov 16, 2023 at 11:58 AM Richard Biener
wrote:
>
>
> Am 16.11.2023 um 17:00 schrieb David Edelsohn :
>
>
> Bruno,
>
> I have been able to tweak the environment and build gettext and libintl.
> With the updated libintl and environment, GCC reliably does not use NLS.
>
> The issue is that
This is PR ada/109881, a tree sharing issue for the internal return type
synthesized for a function returning a dynamically-sized type and taking an
Out or In/Out parameter passed by copy.
Tested on x86-64/Linux, applied on mainline, 13 and 12 branches.
2023-11-16 Eric Botcazou
PR
Tested x86_64-linux. Pushed to trunk.
-- >8 --
The formatter for std::thread::id should default to right-align, and the
formatter for std::stacktrace_entry should not just ignore the
fill-and-align and width from the format-spec!
libstdc++-v3/ChangeLog:
PR libstdc++/112564
* inc
ChangeLog:
* MAINTAINERS: Add myself.
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index c43167d9a75..f0112f5d029 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -486,6 +486,7 @@ Fariborz Jahanian
Surya Kumari J
Am 16.11.2023 um 17:00 schrieb David Edelsohn :Bruno,I have been able to tweak the environment and build gettext and libintl. With the updated libintl and environment, GCC reliably does not use NLS.The issue is that libintl utilizes pthreads. AIX does not provide no-op pthread stubs in libc. pt
Hello,
PR109849 shows that a loop that heavily pushes and pops from a stack
implemented by a C++ std::vec results in slow code, mainly because the
vector structure is not split by SRA and so we end up in many loads
and stores into it. This is because it is passed by reference
to (re)allocation me
1 - 100 of 187 matches
Mail list logo
