Hello All:
This patch add new pass to replace contiguous addresses vector load lxv with
mma instruction
lxvp.
Bootstrapped and regtested with powepc64-linux-gnu.
Thanks & Regards
Ajit
rs6000: Add new pass for replacement of contiguous lxv with lxvp.
New pass to replace contiguous addresses l
OK
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-07 14:25
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Add more run test for FP rounding autovec
From: Pan Li
For _Float16 types, add run test for:
* ceil
* floor
* nearbyint
* rint
* round
Hi all,
Sorry for the patch revision delay since just back from the vacation.
I have slightly revised this patch for the __EVEX256__ request with the code:
diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc
index 47768fa0940..9c44bd7fb63 100644
--- a/gcc/config/i386/i386-c.cc
+++
From: Pan Li
For _Float16 types, add run test for:
* ceil
* floor
* nearbyint
* rint
* round
* roundeven
* trunc
For float and double, add run test for:
* roundeven
The zfa extension is required for these run test cases, the simulation
target_board may look like below for rv64.
target_board="r
On 10/5/23 08:46, Stefan Schulze Frielinghaus wrote:
> gcc/ChangeLog:
>
> * config/s390/s390.md: Make use of new copysign RTL.
Ok. Thanks!
Andreas
> ---
> gcc/config/s390/s390.md | 6 ++
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/gcc/config/s390/s390.md b/gcc
Thanks Jeff, committed with a better Changelog as your suggestion.
Pan
-Original Message-
From: Jeff Law
Sent: Saturday, October 7, 2023 12:53 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; Wang, Yanzhang ;
kito.ch...@gmail.com
Subject: Re: [PATCH v1] RISC-V: Bugfi
On 10/6/23 22:49, pan2...@intel.com wrote:
From: Pan Li
Given we have RTL as below.
(plus:DI (mult:DI (reg:DI 138 [ g.4_6 ])
(const_int 8 [0x8]))
(lo_sum:DI (reg:DI 167)
(symbol_ref:DI ("f") [flags 0x86] )
))
When handling (plus (plus (mult
From: Pan Li
Given we have RTL as below.
(plus:DI (mult:DI (reg:DI 138 [ g.4_6 ])
(const_int 8 [0x8]))
(lo_sum:DI (reg:DI 167)
(symbol_ref:DI ("f") [flags 0x86] )
))
When handling (plus (plus (mult (a) (mem_shadd_constant)) (fp)) (C)) case,
the fp
Commited, thanks juzhe.
--
Li Xu
>OK.
>
>
>
>juzhe.zh...@rivai.ai
>
>From: Li Xu
>Date: 2023-10-07 11:18
>To: gcc-patches
>CC: kito.cheng; palmer; juzhe.zhong; xuli
>Subject: [PATCH] RISC-V: Fix scan-assembler-times of RVV test case
>From: xuli
>
>gcc/testsuite/ChangeLog:
>
> *
On Wed, Oct 04, 2023 at 02:13:46PM +0200, Jan-Benedict Glaw wrote:
> Seems this breaks for me with
>
> ../gcc/configure [...] --enable-werror-always --enable-languages=all
> --disable-gcov --disable-shared --disable-threads
> --target=loongarch64-linux-gnuf32 --without-headers
> make V=1 all-gcc
OK.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-10-07 11:18
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH] RISC-V: Fix scan-assembler-times of RVV test case
From: xuli
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c: Adjust a
From: xuli
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c: Adjust assembler
times.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c: Ditto.
---
.../gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c | 10 +-
.../gcc.target/riscv/rvv/vsetvl
On Fri, Sep 22, 2023 at 6:58 PM Hongyu Wang wrote:
>
> From: Kong Lingling
>
> Add -mapx-features= enumeration to separate subfeatures of APX_F.
> -mapxf is treated same as previous ISA flag, while it sets
> -mapx-features=apx_all that enables all subfeatures.
Ok for this and the resest of patche
On Thu, Sep 28, 2023 at 11:23 AM ZiNgA BuRgA wrote:
>
> That sounds about right. The code I had in mind would perhaps look like:
>
>
> #if defined(__AVX512BW__) && defined(__AVX512VL__)
> #if defined(__EVEX256__) && !defined(__EVEX512__)
> // compiled code is AVX10.1/256 and AVX512
Thanks for reporting it.
I think we may need to change it into:
+ /* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 4 "vect" {
target {! vect_load_lanes } } } } */
+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 3 "vect" {
target vect_strided5 && vect_load_la
Hi, Kito & Jeff
Due to National Day reasons, I was unable to reply to the email in a timely
manner.
Thank you for making the necessary changes to this patch. For the introduction
of this bug,
I will also carefully summarize my experience and lessons to avoid the
recurrence of such problems.
T
> So if you think you got everything correct the patch is OK as-is,
> I just wasn't sure - maybe the neutral_element change deserves
> a comment as to how MINUS_EXPR is handled.
Heh, I never think I got everything correct ;)
Added this now:
static bool
fold_left_reduction_fn (code_helper code,
Dear all,
the attached simple patch fixes a mixup of error messages for -ffpe-trap
and -ffpe-summary. While at it, I though it might be useful to accept
'none' as allowable argument to -ffpe-trap, so that traps previously set
on the command line may be cleared. This change is also documented.
R
Am Freitag, dem 06.10.2023 um 06:50 -0400 schrieb Siddhesh Poyarekar:
> On 2023-10-06 01:11, Martin Uecker wrote:
> > Am Donnerstag, dem 05.10.2023 um 15:35 -0700 schrieb Kees Cook:
> > > On Thu, Oct 05, 2023 at 04:08:52PM -0400, Siddhesh Poyarekar wrote:
> > > > 2. How would you handle signedness
Vlad recently introduced a new gate @ira_in_progress, similar to
counterparts @{reload,lra}_in_progress.
Use this to hide the constant synthesis splitter from being recog* ()
by IRA register equivalence logic which is eager to undo the splits,
generating worse code for constants (and sometimes no
On 10/6/23 11:49, Vineet Gupta wrote:
Vlad recently introduced a new gate @ira_in_progress, similar to
counterparts @{reload,lra}_in_progress.
Use this to hide the constant synthesis splitter from being recog* ()
by IRA register equivalence logic which is eager to undo the splits,
generating
On 10/6/23 08:17, Manolis Tsamis wrote:
SNIP
So I was ready to ACK, but realized there weren't any testresults for a
primary platform mentioned. So I ran this on x86.
It's triggering one regression (code quality).
Specifically gcc.target/i386/pr52146.c
The f-m-o code is slightly worse than
Vlad recently introduced a new gate @ira_in_progress, similar to
counterparts @{reload,lra}_in_progress.
Use this to hide the constant synthesis splitter from being recog* ()
by IRA register equivalence logic which is eager to undo the splits,
generating worse code for constants (and sometimes no
gcc/ChangeLog:
* doc/extend.texi (Function Attributes): Mention standard attribute
syntax.
(Variable Attributes): Likewise.
(Type Attributes): Likewise.
(Attribute Syntax): Likewise.
---
gcc/doc/extend.texi | 74 +++--
Hi Bruno,
Bruno Haible writes:
>> * intlmacosx.m4: Import from gettext-0.22 (serial 8).
>
> A further suggestion (can be done in a separate patch, later):
>
> Use intlmacosx.m4 from gettext-0.22.3 (serial 9).
>
> This version enables portability to macOS 14, which was released
> on 2023-
Arsen Arsenović wrote:
> * intlmacosx.m4: Import from gettext-0.22 (serial 8).
A further suggestion (can be done in a separate patch, later):
Use intlmacosx.m4 from gettext-0.22.3 (serial 9).
This version enables portability to macOS 14, which was released
on 2023-09-26. (Older versions
On 15/09/2023 10:16, Juzhe-Zhong wrote:
This test failed in RISC-V:
FAIL: gcc.dg/vect/slp-1.c -flto -ffat-lto-objects scan-tree-dump-times vect
"vectorizing stmts using SLP" 4
FAIL: gcc.dg/vect/slp-1.c scan-tree-dump-times vect "vectorizing stmts using
SLP" 4
Because this loop:
/* SLP with
On Thu, Oct 5, 2023 at 1:05 AM Jeff Law wrote:
>
>
>
> On 10/3/23 05:45, Manolis Tsamis wrote:
> > This is a new RTL pass that tries to optimize memory offset calculations
> > by moving them from add immediate instructions to the memory loads/stores.
> > For example it can transform this:
> >
> >
I've just committed this patch. It should have no functional changes
except to make it easier to add new alternatives into the
alternative-heavy move instructions.
Andrewamdgcn: switch mov insns to compact syntax
The move instructions typically have many alternatives (and I'm about to add
more
Afternoon,
This patch is a rebase and rewording of
https://inbox.sourceware.org/20230925150921.894157-1-ar...@aarsen.me/
Changes since v1:
- Implement Brunos suggested changes to install.texi.
- Elaborate commit message in p2 (as requested by the Binutils
maintainers).
Arsen Arsenović (2):
i
ChangeLog:
* intl: Remove directory. Replaced with out-of-tree GNU
gettext.
---
Note that the commit message here doesn't pass the changelog verifier.
What should I reword it as? mklog suggests:
ChangeLog:
* intl/ChangeLog: Removed.
* intl/Makefile.in: Removed.
Grr! I've done it again. ENOPATCH.
> -Original Message-
> From: Roger Sayle
> Sent: 06 October 2023 14:58
> To: 'gcc-patches@gcc.gnu.org'
> Cc: 'Uros Bizjak'
> Subject: [X86 PATCH] Implement doubleword right shifts by 1 bit using
s[ha]r+rcr.
>
>
> This patch tweaks the i386 back-en
This patch tweaks the i386 back-end's ix86_split_ashr and ix86_split_lshr
functions to implement doubleword right shifts by 1 bit, using a shift
of the highpart that sets the carry flag followed by a rotate-carry-right
(RCR) instruction on the lowpart.
Conceptually this is similar to the recent
On Thu, Oct 5, 2023 at 5:54 PM Jeff Law wrote:
>
>
>
> On 10/3/23 05:45, Manolis Tsamis wrote:
> > This is a new RTL pass that tries to optimize memory offset calculations
>
> > +
> > +/* If INSN is a root memory instruction then compute a potentially new
> > offset
> > + for it and test if the
On Fri, 6 Oct 2023, Robin Dapp wrote:
> > We might need a similar assert
> >
> > gcc_assert (HONOR_SIGNED_ZEROS (vectype_out)
> > && !HONOR_SIGN_DEPENDENT_ROUNDING (vectype_out));?
>
> erm, obviously not that exact assert but more something like
>
> if (HONOR_SIGNED_
On 10/6/2023 2:24 PM, Saurabh Jha wrote:
Hey,
This patch adds support for the Cortex-X4 CPU to GCC.
Regression testing for aarch64-none-elf target and found no regressions.
Okay for gcc-master? I don't have commit access so if it looks okay,
could someone please help me commit this?
Thanks
Hey,
This patch adds support for the Cortex-X4 CPU to GCC.
Regression testing for aarch64-none-elf target and found no regressions.
Okay for gcc-master? I don't have commit access so if it looks okay,
could someone please help me commit this?
Thanks,
Saurabh
gcc/ChangeLog
* config/aar
I've just committed this simple patch to silence an enum warning.
Andrewamdgcn: silence warning
gcc/ChangeLog:
* config/gcn/gcn.cc (print_operand): Adjust xcode type to fix warning.
diff --git a/gcc/config/gcn/gcn.cc b/gcc/config/gcn/gcn.cc
index f6cff659703..ef3b6472a52 100644
--- a/g
> We might need a similar assert
>
> gcc_assert (HONOR_SIGNED_ZEROS (vectype_out)
> && !HONOR_SIGN_DEPENDENT_ROUNDING (vectype_out));?
erm, obviously not that exact assert but more something like
if (HONOR_SIGNED_ZEROS && !HONOR_SIGN_DEPENDENT_ROUNDING...)
{
i
> ... here we probably get PLUS_EXPR for MINUS_EXPR above but IIRC
> for MINUS_EXPR the !as_initial case should return positive zero.
>
> Can you double-check?
You're referring to the canonicalization from a - CST to a + -CST so
that the neutral op would need to change with it? Argh, good point.
From: Ezra Sitorus
This patch is part of a series of patches implementing the _xN variants of the
vst1 intrinsic for arm32.
This patch adds the _x4 variants of the vst1 intrinsic.
ACLE documents are at https://developer.arm.com/documentation/ihi0053/latest/
ISA documents are at https://develope
From: Ezra Sitorus
This patch is part of a series of patches implementing the _xN variants of the
vst1 intrinsic for arm32.
This patch adds the _x3 variants of the vst1 intrinsic.
ACLE documents are at https://developer.arm.com/documentation/ihi0053/latest/
ISA documents are at https://develope
From: Ezra Sitorus
This patch is part of a series of patches implementing the _xN variants of the
vst1 intrinsic for arm32.
This patch adds the _x2 variants of the vst1 intrinsic. Tests use xN so that
the latter variants (_x3, _x4) could be added.
ACLE documents are at https://developer.arm.co
Add xN variants of vst1_types intrinsic.
On 2023-10-06 01:11, Martin Uecker wrote:
Am Donnerstag, dem 05.10.2023 um 15:35 -0700 schrieb Kees Cook:
On Thu, Oct 05, 2023 at 04:08:52PM -0400, Siddhesh Poyarekar wrote:
2. How would you handle signedness of the size field? The size gets
converted to sizetype everywhere it is used and over
From: Ezra Sitorus
This patch is part of a series of patches implementing the _xN variants of the
vld1q intrinsic for arm32.
This patch adds the _x4 variants of the vld1q intrinsic. This depends on the
the _x2 patch.
ACLE documents are at https://developer.arm.com/documentation/ihi0053/latest/
From: Ezra Sitorus
This patch is part of a series of patches implementing the _xN variants of the
vld1q intrinsic for arm32.
This patch adds the _x3 variants of the vld1q intrinsic. This depends on the
the _x2 patch.
ACLE documents are at https://developer.arm.com/documentation/ihi0053/latest/
From: Ezra Sitorus
This patch is part of a series of patches implementing the _xN variants of the
vld1q intrinsic for arm32.
This patch adds the _x2 variants of the vld1q intrinsic. Tests use xN so that
the latter variants (_x3, _x4) could be added.
ACLE documents are at https://developer.arm.
Add xN variants of vld1q_types intrinsic.
On Thu, 5 Oct 2023, Jan Hubicka wrote:
[...]
> Richi, can you please look at the gimple matching part?
What did you have in mind? I couldn't find anything obvious in the
patch counting as gimple matching - do you have a pointer?
Thanks,
Richard.
On Thu, Sep 14, 2023 at 2:43 PM Di Zhao OS
wrote:
>
> This is a new version of the patch on "nested FMA".
> Sorry for updating this after so long, I've been studying and
> writing micro cases to sort out the cause of the regression.
Sorry for taking so long to reply.
> First, following previous
On Thu, 5 Oct 2023, Robin Dapp wrote:
> Hi Tamar,
>
> > The only comment I have is whether you actually need this helper
> > function? It looks like all the uses of it are in cases you have, or
> > will call conditional_internal_fn_code directly.
> removed the cond_fn_p entirely in the attached v
Just that it doesn't get forgotten, the attached patch needs to be
applied on top.
It handles 'tile'/'unroll' directive names in the 'contains'/'absent'
clauses of the 'assume'/'assumes' directives.
Currently, we don't do anything with it after parsing; hence, no further
changes are required. (W
If a CONST_INT represents an integer of a mode with fewer bits than in
HOST_WIDE_INT, then the integer is sign extended. For those two
optimizations touched by this patch, the integers of interest have only
the most significant bit set w.r.t their mode, therefore, they were sign
extended. Thus in
On Fri, Oct 6, 2023 at 1:15 AM Andrew Pinski wrote:>
> Match has a pattern which converts `vec_cond(vec_cond(a,b,0), c, d)`
> into `vec_cond(a & b, c, d)` but since in this case a is a comparison
> fold will change `a & b` back into `vec_cond(a,b,0)` which causes an
> infinite loop.
> The best way
On Thu, Oct 5, 2023 at 10:46 PM Tamar Christina wrote:
>
> > -Original Message-
> > From: Richard Sandiford
> > Sent: Thursday, October 5, 2023 9:26 PM
> > To: Tamar Christina
> > Cc: gcc-patches@gcc.gnu.org; nd ; Richard Earnshaw
> > ; Marcus Shawcroft
> > ; Kyrylo Tkachov
> > Subject:
Richard Biener writes:
> On Thu, Oct 5, 2023 at 5:49 PM Andrea Corallo wrote:
>>
>> Hello all,
>>
>> this patch checks in mdcompact, the tool written in elisp that I used
>> to mass convert all the multi choice pattern in the aarch64 back-end to
>> the new compact syntax.
>>
>> I tested it on Em
On Thu, 5 Oct 2023, Tamar Christina wrote:
> Hi All,
>
> This adds a masked variant of copysign. Nothing very exciting just the
> general machinery to define and use a new masked IFN.
>
> Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.
>
> Note: This patch is part of a testseri
On Thu, 5 Oct 2023, Tamar Christina wrote:
> Hi All,
>
> When ifcvt was initially added masking was not a thing and as such it was
> rather conservative in what it supported.
>
> For builtins it only allowed C99 builtin functions which it knew it can fold
> away.
>
> These days the vectorizer i
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