On 9/29/23 16:53, Jivan Hakobyan wrote:
After f088b768d01a commit riscv_sched_variable_issue function requires
that all insns should have a type attribute.
When I sent my previous patch there was no such limitation.
Currently, I have regressions on my tests. This patch fixes them.
gcc/Change
After f088b768d01a commit riscv_sched_variable_issue function requires
that all insns should have a type attribute.
When I sent my previous patch there was no such limitation.
Currently, I have regressions on my tests. This patch fixes them.
gcc/ChangeLog:
* config/riscv/bitmanip.md (*_no
So this ends up looking a lot like the bits that I had to revert several
weeks ago :-)
The core issue we have is given an INSN the generic code will cost the
SET_SRC and SET_DEST and sum them. But that's far from ideal on a RISC
target.
For a register destination, the cost can be determin
On 9/29/23 14:59, Jeff Law wrote:
On 9/29/23 15:37, Patrick O'Neill wrote:
Resolves this error on rv32gcv:
cc1: error: ABI requires '-march=rv32'
compiler exited with status 1
FAIL: gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c -O0 (test for
excess errors)
Tested for regressions using gl
On 9/29/23 15:11, Roger Sayle wrote:
Hi Claudiu,
The patch looks sane. Have you run dejagnu test suite?
I've not yet managed to set up an emulator or compile the entire toolchain,
so my dejagnu results are only useful for catching (serious) problems in the
compile only tests:
On 9/29/23 15:37, Patrick O'Neill wrote:
Resolves this error on rv32gcv:
cc1: error: ABI requires '-march=rv32'
compiler exited with status 1
FAIL: gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c -O0 (test for excess
errors)
Tested for regressions using glibc rv32gcv/rv64gcv multilib on
r14-4
Resolves this error on rv32gcv:
cc1: error: ABI requires '-march=rv32'
compiler exited with status 1
FAIL: gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c -O0 (test for excess
errors)
Tested for regressions using glibc rv32gcv/rv64gcv multilib on
r14-4339-geaa41a6dc12.
gcc/testsuite/ChangeLog:
On 9/29/23 12:05, Jeff Law wrote:
On 9/12/23 12:54, Patrick O'Neill wrote:
This testcase causes lots of false-positives for machine description
files.
contrib/ChangeLog:
* check_GNU_style_lib.py: Skip machine description file bracket
linting.
OK. We probably need a completely separ
Hi Claudiu,
> The patch looks sane. Have you run dejagnu test suite?
I've not yet managed to set up an emulator or compile the entire toolchain,
so my dejagnu results are only useful for catching (serious) problems in the
compile only tests:
=== gcc Summary ===
# of expected pa
On 9/28/23 03:46, Maciej W. Rozycki wrote:
On Wed, 27 Sep 2023, Jeff Law wrote:
IMO this is one of those places where we should just be as normal as
possible. So if the other big ports allow system headers then we should,
otherwise we should move everyone over to testing in some way we'll c
On 8/23/23 22:53, Li, Pan2 wrote:
Thanks Jeff.
That implies a save/restore pair around the call (possibly optimized so
that we minimize the number of save/restores). I would have expected
x86 to already be doing this. But maybe there's some ABI thing around
mmx vs x86 state that allows it
On 8/25/23 06:44, Li, Pan2 wrote:
Hi Jeff,
You might also peek at the RTL gcse/pre code which is also LCM based and
has the same class of problems.
I found a similar approach to take care of this in gcse.cc/pre_edge_insert with
some comments as below.
/* We can't insert anything on an
On 9/5/23 01:12, Andrew Pinski wrote:
On Mon, Sep 4, 2023 at 11:06 PM Jeff Law via Gcc-patches
wrote:
On 9/1/23 11:30, Andrew Pinski via Gcc-patches wrote:
So it turns out there was a simplier way of starting to
improve VRP to start to fix PR 110131, PR 108360, and PR 108397.
That was re
On 9/5/23 01:46, Andrew Pinski wrote:
On Tue, Sep 5, 2023 at 12:09 AM Jeff Law via Gcc-patches
wrote:
On 9/1/23 20:32, Andrew Pinski via Gcc-patches wrote:
This turns out to be a latent bug in ssa_name_has_boolean_range
where it would return true for all boolean types but all of the
uses
On Fri, Sep 29, 2023 at 2:09 PM Michael Meissner
wrote:
> When I first implemented COPYSIGN support in the power7 days, we did not
> have a
> copysign RTL insn, so I had to use UNSPEC to represent the copysign
> instruction. This patch removes those UNSPECs, and it uses the native RTL
> copysign
On 9/12/23 13:09, Jivan Hakobyan via Gcc-patches wrote:
In the case when we have C code like this
int foo (int a) {
return 100 & ~a;
}
GCC generates the following instruction sequence
foo:
not a0,a0
andia0,a0,100
ret
This patch replaces that with this sequence
On 9/12/23 03:18, Feng Wang wrote:
New patch add some comments and update docs for this new usage.
---
Accoring to Kito's advice, using "MASK(name) Var(other_flag_name)"
to generate MASK and TARGET MACRO automatically.
This patch improve the MACRO generation of MASK_* and TARGET_*.
Due to the
On 9/12/23 04:13, Manolis Tsamis wrote:
+
+/* Get the single reaching definition of an instruction inside a BB.
+ The definition is desired for REG used in INSN.
+ Return the definition insn or NULL if there's no definition with
+ the desired criteria. */
+static rtx_insn*
+get_single_
Hi,
This patch implements pex_unix_exec_child using posix_spawn when
available.
This should especially benefit recent macOS (where vfork just calls
fork), but should have equivalent or faster performance on all
platforms.
In addition, the implementation is substantially simpler than the
vfork+exe
On 9/12/23 12:54, Patrick O'Neill wrote:
This testcase causes lots of false-positives for machine description files.
contrib/ChangeLog:
* check_GNU_style_lib.py: Skip machine description file bracket linting.
OK. We probably need a completely separate checker for for .md files.
j
On 8/10/23 07:04, Stefan Schulze Frielinghaus via Gcc-patches wrote:
In the former fix in commit 41ef5a34161356817807be3a2e51fbdbe575ae85 I
completely missed the fact that the normal form of a generated constant for a
mode with fewer bits than in HOST_WIDE_INT is a sign extended version of the
On 9/19/23 10:06, Stefan Schulze Frielinghaus wrote:
Since this patch is sitting in the queue for quite some time and (more
importantly?) solves a bootstrap problem let me reiterate:
While writing the initial commit 7cdd0860949c6c3232e6cff1d7ca37bb5234074c
and the subsequent (potential) fix 4
On 9/29/23 12:05, Kito Cheng wrote:
Hi Jeff:
Could you take a look for this? RISC-V part is ok to me.
Thanks :)
Yea, I've got two things on my list to review from a doc standpoint.
This is one of 'em.
jeff
When I first implemented COPYSIGN support in the power7 days, we did not have a
copysign RTL insn, so I had to use UNSPEC to represent the copysign
instruction. This patch removes those UNSPECs, and it uses the native RTL
copysign insn.
I have tested this on both big endian and little endian Powe
Hi Jeff:
Could you take a look for this? RISC-V part is ok to me.
Thanks :)
Feng Wang 於 2023年9月12日 週二 17:18 寫道：
> New patch add some comments and update docs for this new usage.
> ---
> Accoring to Kito's advice, using "MASK(name) Var(other_flag_name)"
> to generate MASK and TARGET MACRO autom
Hi Roger,
The patch looks sane. Have you run dejagnu test suite?
Thanks,
Claudiu
-Original Message-
From: Roger Sayle
Sent: Friday, September 29, 2023 6:54 PM
To: gcc-patches@gcc.gnu.org
Cc: Claudiu Zissulescu
Subject: [ARC PATCH] Use rlc r0,0 to implement scc_ltu (i.e. carry_flag ?
On 27 September 2023 06:46:29 CEST, Bernhard Reutner-Fischer
wrote:
>On 27 September 2023 06:43:24 CEST, Jakub Jelinek wrote:
>>Hi!
>>
>>While looking into vec.h, I've noticed we still have a workaround for
>>GCC 4.1-4.3 bugs.
>
>
>This is https://gcc.gnu.org/PR105656
>thanks,
Mere cosmetics, b
On 9/19/23 02:46, Jin Ma wrote:
This patch adds the 'Zfbfmin' extension for riscv, which is based on spec of
bfloat16:
https://github.com/riscv/riscv-bfloat16/commit/5578e34e15a44e9ad13246072a29f51274b4d999
The 'Zfbfmin' extension of binutils-gdb (REVIEW ONLY):
https://sourceware.org/piperma
On 9/19/23 02:44, Jin Ma wrote:
gcc/ChangeLog:
* config/riscv/iterators.md (HFBF): New.
* config/riscv/riscv-builtins.cc (riscv_init_builtin_types):
Initialize data type_Bfloat16.
* config/riscv/riscv-modes.def (FLOAT_MODE): New.
(ADJUST_FLOAT_FORMAT):
Thanks Jeff, pushed as 94e68ce96c285e479736851f1ad8cc87c8c3ff0c
FX
On 9/20/23 07:53, FX Coudert wrote:
ping**2
Hi,
This was a painful one to fix, because I hate regexps, especially when they are
quoted. On darwin, we have this failure:
FAIL: gcc.dg/debug/dwarf2/inline4.c scan-assembler
DW_TAG_inlined_subroutine[^(]*([^)]*)[^(]*\
Arsen Arsenović wrote:
> Do you like the following?
>
> @@ -486,7 +486,7 @@ found in a subdirectory of your GCC sources
> will be built together with GCC, unless present in the system (either in
> libc or as a stand-alone library).
>
> -The in-tree configuration requires GNU gettext v0.22.
> +
On Fri, 29 Sept 2023 at 17:29, Nathaniel Shead
wrote:
>
> On Fri, Sep 29, 2023 at 04:06:33PM +0100, Jonathan Wakely wrote:
> > On Fri, 29 Sept 2023 at 10:32, Jonathan Wakely wrote:
> > > > Thanks for the comments, here's an updated version of the patch.
> > > > Bootstrapped and regtested on x86_6
On Fri, Sep 29, 2023 at 04:06:33PM +0100, Jonathan Wakely wrote:
> On Fri, 29 Sept 2023 at 10:32, Jonathan Wakely wrote:
> > > Thanks for the comments, here's an updated version of the patch.
> > > Bootstrapped and regtested on x86_64-pc-linux-gnu.
> >
> > Great, I'll get this committed today - th
Bruno Haible writes:
> Arsen Arsenović wrote:
>> -+The in-tree configuration requires GNU gettext v0.22.
>
> Can you change this to "... requires GNU gettext version 0.22 or newer.",
> please?
> I wouldn't like to give the impression that a particular release (0.22) is the
> only one that works
Since 2005, it was assumed in the Linux kernel that all PA 2.0 processors
supported the ldcw cacheable hint and that natural alignment could be used
for ldcw,co. However, I recently fired up an old A500 machine with PA8600
processors and found that 16-byte alignment was needed for ldcw,co on it.
A
This patch teaches the ARC backend that the contents of the carry flag
can be placed in an integer register conveniently using the "rlc rX,0"
instruction, which is a rotate-left-through-carry using zero as a source.
This is a convenient special case for the LTU form of the scc pattern.
unsigned i
On Fri, 29 Sept 2023 at 10:32, Jonathan Wakely wrote:
> > Thanks for the comments, here's an updated version of the patch.
> > Bootstrapped and regtested on x86_64-pc-linux-gnu.
>
> Great, I'll get this committed today - thanks!
That's done now.
> >
> > I'll note that there are some existing cal
On Thu, 28 Sept 2023 at 20:39, Dimitrij Mijoski via Libstdc++
wrote:
>
> This patch fixes the handling of surrogate code points in all standard
> facets for transcoding Unicode that are based on std::codecvt. Surrogate
> code points should always be treated as error. On the other hand
> surrogate
On 9/26/23 18:50, Tamar Christina wrote:
Hi All,
For targets that allow conversion between int and float modes this adds a new
optimization transforming fneg (fabs (x)) into x | (1 << signbit(x)). Such
sequences are common in scientific code working with gradients.
The transformed instructi
On 9/29/23 02:19, Paul Iannetta wrote:
On Tue, Sep 26, 2023 at 08:29:11AM -0600, Jeff Law wrote:
On 9/25/23 03:55, Paul Iannetta wrote:
On Mon, Sep 18, 2023 at 08:39:34AM +0200, Paul Iannetta wrote:
On Thu, Sep 14, 2023 at 04:24:33PM +0200, Paul Iannetta wrote:
Hi,
This is a small patch
On Fri, 29 Sept 2023 at 15:07, Jonathan Wakely wrote:
>
> On Tue, 6 Dec 2016 at 17:59, Jonathan Wakely wrote:
> > >Subject: [PATCH 3/3] Enable libstdc++ compilation in AVR targets
> > >
> > >Enable libstdc++ compilation in AVR targets with AVR-Libc. Most
> > >floating point math functions are alre
On Tue, 6 Dec 2016 at 17:59, Jonathan Wakely wrote:
> >Subject: [PATCH 3/3] Enable libstdc++ compilation in AVR targets
> >
> >Enable libstdc++ compilation in AVR targets with AVR-Libc. Most
> >floating point math functions are already defined in AVR-Libc, so
> >defines are in place to avoid multip
On 9/27/23 17:21, Vineet Gupta wrote:
On 9/27/23 13:14, Jeff Law wrote:
It would help to describe how these patterns were under specified so
that folks don't continue to make the same mistake as new tests get
added.
dg-final scan-assembler, scan-assembler-not, and scan-assembler-times
us
On 9/29/23 04:40, Roger Sayle wrote:
I agree that this looks dubious. Normally, if the middle-end/optimizers
wish to reuse a SUBREG in a context where the flags are not valid, it
should create a new one with the desired flags, rather than "mutate"
an existing (and possibly shared) RTX.
SUBRE
Hello All:
This patch add new pass to replace contiguous addresses vector load lxv with
mma instruction
lxvp.
Bootstrapped and regtested with powepc64-linux-gnu.
Thanks & Regards
Ajit
rs6000: Add new pass for replacement of contiguous lxv with lxvp
New pass to replace contiguous addresses vec
Hi Paul,
thanks. Commit to trunk as a680274616ec6b26ccfdcee400ed7f54e341d40c
and backported to gcc-13 as d9b3269bdccac2db9200303494c4e82f2aeb7bbc
Thanks for the fast review.
Regards,
Andre
On Fri, 29 Sep 2023 13:38:57 +0100
Paul Richard Thomas wrote:
> Hi Andre,
>
> Yes indeed - it's
On Fri, 29 Sep 2023, Jakub Jelinek wrote:
> Hi!
>
> As reported by Jonathan on IRC, my vec.h patch broke build with GCC 4.8.x
> or 4.9.x as system compiler, e.g. on CFarm.
> The problem is that while all of
> std::is_trivially_{destructible,copyable,default_constructible} traits
> are in C++, onl
Hi Andre,
Yes indeed - it's fine for trunk and, I would suggest, 13-branch.
Cheers
Paul
On Fri, 29 Sept 2023 at 11:01, Andre Vehreschild wrote:
>
> Hi Paul,
>
> thanks for the quick review. I've added a testcase with a module and a
> finalizer in the derived type. This also is no problem.
>
>
On 9/28/23 21:49, Vineet Gupta wrote:
On 9/28/23 20:17, Jeff Law wrote:
I can bootstrap & regression test alpha using QEMU user mode
emulation. So we might be able to trigger something that way. It'll
take some time, but might prove fruitful.
That would be awesome. It's not like this thi
On 9/29/23 04:37, Jakub Jelinek wrote:
On Thu, Sep 28, 2023 at 11:53:53AM -0400, Aldy Hernandez wrote:
ipa_bits is even worse, because unlike niter analysis, I think it is very
much desirable to support IPA VRP of all supported _BitInt sizes. Shall
we perhaps use trailing_wide_int storage in
Arsen Arsenović wrote:
> -+The in-tree configuration requires GNU gettext v0.22.
Can you change this to "... requires GNU gettext version 0.22 or newer.",
please?
I wouldn't like to give the impression that a particular release (0.22) is the
only one that works.
Also, some people may understand '
On Fri, Sep 29, 2023 at 11:30:06AM +0100, Richard Sandiford wrote:
> Yeah, think I agree with this. widest_int really combined two things:
>
> (a) a way of storing any integer IL value without loss of precision
>
> (b) a way of attaching sign information
>
> Arithmetic on widest_int is dubious,
Applied to master. Thanks!
--Philipp.
On Fri, 29 Sept 2023 at 12:34, Richard Sandiford
wrote:
>
> Manos Anagnostakis writes:
> > Improves on: 834fc2bf
> >
> > This improves the code structure of the ldp-stp policies
> > patch introduced in 834fc2bf
> >
> > Bootstrapped and regtested on aarch64-l
Hi!
As reported by Jonathan on IRC, my vec.h patch broke build with GCC 4.8.x
or 4.9.x as system compiler, e.g. on CFarm.
The problem is that while all of
std::is_trivially_{destructible,copyable,default_constructible} traits
are in C++, only std::is_trivially_destructible has been implemented in
I agree that this looks dubious. Normally, if the middle-end/optimizers
wish to reuse a SUBREG in a context where the flags are not valid, it
should create a new one with the desired flags, rather than "mutate"
an existing (and possibly shared) RTX.
I wonder if creating a new SUBREG here also f
Manos Anagnostakis writes:
> Improves on: 834fc2bf
>
> This improves the code structure of the ldp-stp policies
> patch introduced in 834fc2bf
>
> Bootstrapped and regtested on aarch64-linux.
>
> gcc/ChangeLog:
> * config/aarch64/aarch64-opts.h (enum aarch64_ldp_policy): Removed.
> (en
Richard Biener writes:
> On Thu, 28 Sep 2023, Jakub Jelinek wrote:
>
>> Hi!
>>
>> On Tue, Aug 29, 2023 at 05:09:52PM +0200, Jakub Jelinek via Gcc-patches
>> wrote:
>> > On Tue, Aug 29, 2023 at 11:42:48AM +0100, Richard Sandiford wrote:
>> > > > I'll note tree-ssa-loop-niter.cc also uses GMP in s
Improves on: 834fc2bf
This improves the code structure of the ldp-stp policies
patch introduced in 834fc2bf
Bootstrapped and regtested on aarch64-linux.
gcc/ChangeLog:
* config/aarch64/aarch64-opts.h (enum aarch64_ldp_policy): Removed.
(enum aarch64_ldp_stp_policy): Merged enums
On Fri, Sep 29, 2023 at 11:00:01AM +0100, Jonathan Wakely wrote:
> > +/* Destruct N elements in DST. */
> > +
> > +template
> > +inline void
> > +vec_destruct (T *dst, unsigned n)
> > +{
> > + for ( ; n; ++dst, --n)
> > +dst->~T ();
> > +}
> > +
> > /* Control data for vectors. This contai
Hi Paul,
thanks for the quick review. I've added a testcase with a module and a
finalizer in the derived type. This also is no problem.
Regtests ok on x86_64_linux_gnu/f37. Ok for trunk?
Regards,
Andre
On Thu, 28 Sep 2023 19:21:12 +0100
Paul Richard Thomas wrote:
> Hi Andre,
>
> The p
On Thu, 28 Sept 2023 at 10:17, Jakub Jelinek wrote:
>
> Hi!
>
> On Wed, Sep 27, 2023 at 12:46:45PM +0200, Jakub Jelinek wrote:
> > On Wed, Sep 27, 2023 at 07:17:22AM +, Richard Biener wrote:
> > > OK I guess. Can you summarize the limitations for non-POD types
> > > in the big comment at the
On Thu, 28 Sept 2023 at 18:25, François Dumont wrote:
>
>
> On 28/09/2023 18:18, Jonathan Wakely wrote:
> > On Wed, 27 Sept 2023 at 05:44, François Dumont wrote:
> >> Still no chance to get feedback from TC ? Maybe I can commit the below
> >> then ?
> > I've heard back from Tim now. Please use "T
The following conservatively fixes loop distribution to only
recognize memset/memcpy and friends when at least one element
is going to be processed. This avoids having an unconditional
builtin call in the IL that might imply the source and destination
pointers are non-NULL when originally pointers
On Thu, 28 Sep 2023, Jakub Jelinek wrote:
> Hi!
>
> On Tue, Aug 29, 2023 at 05:09:52PM +0200, Jakub Jelinek via Gcc-patches wrote:
> > On Tue, Aug 29, 2023 at 11:42:48AM +0100, Richard Sandiford wrote:
> > > > I'll note tree-ssa-loop-niter.cc also uses GMP in some cases, widest_int
> > > > is rea
On Fri, 29 Sept 2023 at 00:25, Nathaniel Shead
wrote:
>
> On Wed, Sep 27, 2023 at 03:13:35PM +0100, Jonathan Wakely wrote:
> > On Sat, 23 Sept 2023 at 08:30, Nathaniel Shead via Libstdc++
> > wrote:
> > >
> > > On Sat, Sep 23, 2023 at 07:40:48AM +0100, Jonathan Wakely wrote:
> > > > On Sat, 23 Se
Confidentiality Warning: This e-mail contains information intended only for the use of the individual or entity named above. If the reader of this e-mail is not the intended recipient or the employee or agent responsible for delivering it to the intended recipient, any dissemination, publication or
On Fri, 29 Sep 2023, Jakub Jelinek wrote:
> On Thu, Sep 28, 2023 at 04:03:55PM +0200, Jakub Jelinek wrote:
> > Bet we should make wide_int_storage and widest_int_storage GTY ((user)) and
> > just declare but don't define the handlers or something similar.
>
> That doesn't catch anything, but the
On Fri, 29 Sep 2023, Jakub Jelinek wrote:
> On Wed, Sep 27, 2023 at 11:15:26AM +, Richard Biener wrote:
> > > tree-vect-patterns.cc:2947 unprom.quick_grow (nops);
> > > T = vect_unpromoted_value
> > > Go for quick_grow_cleared? Something else?
> >
> > The CTOR zero-initializes everything, s
On Wed, Sep 27, 2023 at 11:15:26AM +, Richard Biener wrote:
> > tree-vect-patterns.cc:2947 unprom.quick_grow (nops);
> > T = vect_unpromoted_value
> > Go for quick_grow_cleared? Something else?
>
> The CTOR zero-initializes everything, so maybe it can go. In theory
> .set_op could also be c
Thanks for the update.
Manos Anagnostakis writes:
> Improves on: 834fc2bf
>
> This improves the code structure of the ldp-stp policies
> patch introduced in 834fc2bf
>
> Bootstrapped and regtested on aarch64-linux.
>
> gcc/ChangeLog:
> * config/aarch64/aarch64-opts.h (enum aarch64_ldp_polic
On Thu, Sep 28, 2023 at 11:53:53AM -0400, Aldy Hernandez wrote:
> > ipa_bits is even worse, because unlike niter analysis, I think it is very
> > much desirable to support IPA VRP of all supported _BitInt sizes. Shall
> > we perhaps use trailing_wide_int storage in there, or conditionally
> > rwid
On Thu, 28 Sep 2023, Sergei Trofimovich wrote:
> From: Sergei Trofimovich
>
> There are 3 GC root tables:
>
>gt_ggc_rtab
>gt_ggc_deletable_rtab
>gt_pch_scalar_rtab
>
> `deletable` and `scalar` tables are both simple: each element always
> contains a pointer to the beginning of the
On Thu, Sep 28, 2023 at 04:03:55PM +0200, Jakub Jelinek wrote:
> Bet we should make wide_int_storage and widest_int_storage GTY ((user)) and
> just declare but don't define the handlers or something similar.
That doesn't catch anything, but the following incremental patch compiles
just fine, provi
On Tue, Sep 26, 2023 at 08:29:11AM -0600, Jeff Law wrote:
>
>
> On 9/25/23 03:55, Paul Iannetta wrote:
> > On Mon, Sep 18, 2023 at 08:39:34AM +0200, Paul Iannetta wrote:
> > > On Thu, Sep 14, 2023 at 04:24:33PM +0200, Paul Iannetta wrote:
> > > > Hi,
> > > >
> > > > This is a small patch so that
On Fri, Sep 29, 2023 at 08:31:47AM +0200, Richard Biener wrote:
> > IIRC the primary reason we settled on gcc-4.8.x was RHEL7/Centos7. With
> > RHEL 7 approaching EOL moving the baseline forward would seem to make sense.
> >
> > I'd want to know if this affects folks using SuSE's enterprise distro
Richard,
在 2023/9/28 21:39, Richard Sandiford 写道:
> That looks easily solvable though. I've posted a potential fix as:
>
>https://gcc.gnu.org/pipermail/gcc-patches/2023-September/631595.html
>
> Is that the only blocker to doing this in generic code?
Thanks so much for your patch. It works
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