Re: [PATCH] MATCH: Simplify `(X % Y) < Y` pattern.

On Wed, Sep 13, 2023 at 12:11 AM Andrew Pinski via Gcc-patches wrote: > > This merges the two patterns to catch > `(X % Y) < Y` and `Y > (X % Y)` into one by > using :c on the comparison operator. > It does not change any code generation nor > anything else. It is more to allow for better > mainta

Re: [PATCH v2 08/11] Native complex ops: Add explicit vector of complex

On Tue, Sep 12, 2023 at 7:26 PM Joseph Myers wrote: > > On Tue, 12 Sep 2023, Sylvain Noiry via Gcc-patches wrote: > > > Summary: > > Allow the creation and usage of builtins vectors of complex > > in C, using __attribute__ ((vector_size ())) > > If you're adding a new language feature like this, y

Re: [PATCH 2/2] MATCH: Move `X <= MAX(X, Y)` before `MIN (X, C1) < C2` pattern

On Tue, Sep 12, 2023 at 5:41 PM Andrew Pinski via Gcc-patches wrote: > > Since matching C1 as C2 here will decrease how much other simplifications > will need to happen to get the final answer. > > OK? Bootstrapped and tested on x86_64-linux-gnu. OK Richard. > gcc/ChangeLog: > > * match

Re: [PATCH 1/2] MATCH: [PR111364] Add some more minmax cmp operand simplifications

On Tue, Sep 12, 2023 at 5:31 PM Andrew Pinski via Gcc-patches wrote: > > This adds a few more minmax cmp operand simplifications which were missed > before. > `MIN(a,b) < a` -> `a > b` > `MIN(a,b) >= a` -> `a <= b` > `MAX(a,b) > a` -> `a < b` > `MAX(a,b) <= a` -> `a >= b` > > OK? Bootstrapped and

RE: [PATCH v1] RISC-V: Bugfix PR111362 for incorrect frm emit

Committed, thanks Kito. Pan -Original Message- From: Kito Cheng Sent: Wednesday, September 13, 2023 2:16 PM To: Li, Pan2 Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang Subject: Re: [PATCH v1] RISC-V: Bugfix PR111362 for incorrect frm emit LGTM :) On Wed, Sep 13,

Re: [PATCH v1] RISC-V: Bugfix PR111362 for incorrect frm emit

LGTM :) On Wed, Sep 13, 2023 at 2:07 PM Pan Li via Gcc-patches wrote: > > From: Pan Li > > When the mode switching from NONE to CALL, we will restore the > frm but lack some check if we have static frm insn in cfun. > > This patch would like to fix this by adding static frm insn check. > > gcc/C

[PATCH v1] RISC-V: Bugfix PR111362 for incorrect frm emit

From: Pan Li When the mode switching from NONE to CALL, we will restore the frm but lack some check if we have static frm insn in cfun. This patch would like to fix this by adding static frm insn check. gcc/ChangeLog: * PR target/111362 * config/riscv/riscv.cc (riscv_emit_frm_m

Re: [committed] RISC-V: Remove redundant ABI test

lgtm On Wed, Sep 13, 2023 at 11:23 AM Juzhe-Zhong wrote: > > We only support and report warning for RVV types. > > We don't report warning for GNU vectors. > So this testcase checking is incorrect and the FAIL is bogus. > > Remove it and commit it. > > gcc/testsuite/ChangeLog: > > * gcc.t

[PATCH v4 12/22] LoongArch: Add tests for ASX builtin functions.

gcc/testsuite/ChangeLog: * gcc.target/loongarch/vector/lasx/lasx-builtin.c: New test. --- .../loongarch/vector/lasx/lasx-builtin.c | 1509 + 1 file changed, 1509 insertions(+) create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-builtin.c diff --g

[PATCH v4 13/22] LoongArch: Add tests for ASX xvldrepl/xvstelm instruction generation.

gcc/testsuite/ChangeLog: * gcc.target/loongarch/vector/lasx/lasx-xvldrepl.c: New test. * gcc.target/loongarch/vector/lasx/lasx-xvstelm.c: New test. --- .../loongarch/vector/lasx/lasx-xvldrepl.c| 16 .../loongarch/vector/lasx/lasx-xvstelm.c | 14 +++

[PATCH v4 07/22] LoongArch: Add tests for ASX vector xvand/xvandi/xvandn/xvor/xvori/ xvnor/xvnori/xvxor/xvxori instructions.

gcc/testsuite/ChangeLog: * gcc.target/loongarch/vector/lasx/lasx-xvand.c: New test. * gcc.target/loongarch/vector/lasx/lasx-xvandi.c: New test. * gcc.target/loongarch/vector/lasx/lasx-xvandn.c: New test. * gcc.target/loongarch/vector/lasx/lasx-xvnor.c: New test.

[PATCH v4 00/22] Added support for ASX vector instructions.

In order to better test the function of the vector instruction, the 256 bit test cases are further split according to the function of the instruction. Xiaolong Chen (22): LoongArch: Add tests for ASX vector xvadd/xvadda/xvaddi/xvaddwev/ xvaddwodxvsadd instructions. LoongArch: Add tests

[PATCH v4 23/23] LoongArch: Add tests for SX vector vfmadd/vfnmadd/vld/vst instructions.

gcc/testsuite/ChangeLog: * gcc.target/loongarch/vector/lsx/lsx-vfmadd_d.c: New test. * gcc.target/loongarch/vector/lsx/lsx-vfmadd_s.c: New test. * gcc.target/loongarch/vector/lsx/lsx-vfnmadd_d.c: New test. * gcc.target/loongarch/vector/lsx/lsx-vfnmadd_s.c: New test.

[PATCH v4 22/23] LoongArch: Add tests for SX vector vand/vandi/vandn/vor/vori/vnor/ vnori/vxor/vxori instructions.

gcc/testsuite/ChangeLog: * gcc.target/loongarch/vector/lsx/lsx-vand.c: New test. * gcc.target/loongarch/vector/lsx/lsx-vandi.c: New test. * gcc.target/loongarch/vector/lsx/lsx-vandn.c: New test. * gcc.target/loongarch/vector/lsx/lsx-vnor.c: New test. * gcc.t

[PATCH v4 11/23] LoongArch: Add tests for SX vector vexth/vextl/vldi/vneg/vsat instructions.

gcc/testsuite/ChangeLog: * gcc.target/loongarch/vector/lsx/lsx-vexth-1.c: New test. * gcc.target/loongarch/vector/lsx/lsx-vexth-2.c: New test. * gcc.target/loongarch/vector/lsx/lsx-vextl-1.c: New test. * gcc.target/loongarch/vector/lsx/lsx-vextl-2.c: New test.

[PATCH v4 18/23] LoongArch: Add tests for SX vector floating point arithmetic instructions.

gcc/testsuite/ChangeLog: * gcc.target/loongarch/vector/lsx/lsx-vfadd_d.c: New test. * gcc.target/loongarch/vector/lsx/lsx-vfadd_s.c: New test. * gcc.target/loongarch/vector/lsx/lsx-vfclass_d.c: New test. * gcc.target/loongarch/vector/lsx/lsx-vfclass_s.c: New test.

[PATCH v4 10/23] LoongArch: Add tests for SX vector vmax/vmaxi/vmin/vmini instructions.

gcc/testsuite/ChangeLog: * gcc.target/loongarch/vector/lsx/lsx-vmax-1.c: New test. * gcc.target/loongarch/vector/lsx/lsx-vmax-2.c: New test. * gcc.target/loongarch/vector/lsx/lsx-vmaxi-1.c: New test. * gcc.target/loongarch/vector/lsx/lsx-vmaxi-2.c: New test.

[PATCH v4 12/23] LoongArch: Add tests for SX vector vabsd/vmskgez/vmskltz/vmsknz/vsigncov instructions.

gcc/testsuite/ChangeLog: * gcc.target/loongarch/vector/lsx/lsx-vabsd-1.c: New test. * gcc.target/loongarch/vector/lsx/lsx-vabsd-2.c: New test. * gcc.target/loongarch/vector/lsx/lsx-vmskgez.c: New test. * gcc.target/loongarch/vector/lsx/lsx-vmskltz.c: New test.

[PATCH v4 13/23] LoongArch: Add tests for SX vector vdiv/vmod instructions.

gcc/testsuite/ChangeLog: * gcc.target/loongarch/vector/lsx/lsx-vdiv-1.c: New test. * gcc.target/loongarch/vector/lsx/lsx-vdiv-2.c: New test. * gcc.target/loongarch/vector/lsx/lsx-vmod-1.c: New test. * gcc.target/loongarch/vector/lsx/lsx-vmod-2.c: New test. --- .../

[PATCH v4 09/23] LoongArch: Add tests for SX vector vavg/vavgr instructions.

gcc/testsuite/ChangeLog: * gcc.target/loongarch/vector/lsx/lsx-vavg-1.c: New test. * gcc.target/loongarch/vector/lsx/lsx-vavg-2.c: New test. * gcc.target/loongarch/vector/lsx/lsx-vavgr-1.c: New test. * gcc.target/loongarch/vector/lsx/lsx-vavgr-2.c: New test. --- ..

[PATCH v4 07/23] LoongArch: Add tests for SX vector addition vsadd instructions.

gcc/testsuite/ChangeLog: * gcc.target/loongarch/vector/lsx/lsx-vsadd-1.c: New test. * gcc.target/loongarch/vector/lsx/lsx-vsadd-2.c: New test. --- .../loongarch/vector/lsx/lsx-vsadd-1.c| 335 + .../loongarch/vector/lsx/lsx-vsadd-2.c| 345 +++

[PATCH v4 00/23] Add tests for SX vector instructions.

v3 -> v4: Modify the name of the patch file. In order to better test the function of the vector instruction, the 128 bit test cases are further split according to the function of the instruction. Xiaolong Chen (23): LoongArch: Add tests of -mstrict-align option. LoongArch: Add testsuite

[PATCH v4 03/23] LoongArch: Add tests for Loongson SX builtin functions.

gcc/testsuite/ChangeLog: * gcc.target/loongarch/vector/lsx/lsx-builtin.c: New test. --- .../loongarch/vector/lsx/lsx-builtin.c| 1461 + 1 file changed, 1461 insertions(+) create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-builtin.c diff --git a/

[PATCH v4 02/23] LoongArch: Add testsuite framework for Loongson SX/ASX.

gcc/testsuite/ChangeLog: * gcc.target/loongarch/vector/loongarch-vector.exp: New test. * gcc.target/loongarch/vector/simd_correctness_check.h: New test. --- .../loongarch/vector/loongarch-vector.exp | 42 +++ .../loongarch/vector/simd_correctness_check.h | 54 +

[PATCH v4 01/23] LoongArch: Add tests of -mstrict-align option.

gcc/testsuite/ChangeLog: * gcc.target/loongarch/strict-align.c: New test. --- gcc/testsuite/gcc.target/loongarch/strict-align.c | 12 1 file changed, 12 insertions(+) create mode 100644 gcc/testsuite/gcc.target/loongarch/strict-align.c diff --git a/gcc/testsuite/gcc.target/

[committed] RISC-V: Remove redundant ABI test

We only support and report warning for RVV types. We don't report warning for GNU vectors. So this testcase checking is incorrect and the FAIL is bogus. Remove it and commit it. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vector-abi-9.c: Removed. --- .../gcc.target/riscv/rvv/

[PATCH] LoongArch: Change the value of branch_cost from 2 to 6.

gcc/ChangeLog: * config/loongarch/loongarch-def.c: Modify the default value of branch_cost. gcc/testsuite/ChangeLog: * gcc.target/loongarch/cmov_ii.c: New test. --- gcc/config/loongarch/loongarch-def.c | 4 ++-- gcc/testsuite/gcc.target/loongarch/cmov_ii.c | 16

[PING][PATCH v2] Add clang's invalid-noreturn warning flag

Second desperate ping for patch https://gcc.gnu.org/pipermail/gcc-patches/2023-August/627913.html

Re: [PATCH] Checking undefined_p before using the vr

Hi, Richard Biener writes: > On Thu, 7 Sep 2023, Jiufu Guo wrote: > >> Hi, >> >> As discussed in PR111303: >> >> For pattern "(X + C) / N": "div (plus@3 @0 INTEGER_CST@1) INTEGER_CST@2)", >> Even if "X" has value-range and "X + C" does not overflow, "@3" may still >> be undefined. Like below

[PATCH v2] LoongArch: Fix bug of 'di3_fake'.

PR 111334 gcc/ChangeLog: * config/loongarch/loongarch.md: Fix bug of 'di3_fake'. gcc/testsuite/ChangeLog: * gcc.target/loongarch/pr111334.c: New test. --- v1 -> v2: Modify the template "*3", the SI type division operation is not supported under t

Re: [PATCH] aarch64: Add SVE instruction types

Hi, Kyrill. I wonder if the regression that you noticed was the same that I did. Overall, thus far, there’s no significant regression that I can say is due to scheduling. However, there is one benchmark, 507.cactuBSSN_r/607.cactuBSSN_s in SPEC2017, that regressed by more than 10%. Upon close

[PATCH] c++: always check arity before deduction

Bootstrpaped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk? -- >8 -- This simple patch extends the r12-3271-gf1e73199569287 optimization to apply to deduction without explicit template arguments as well. The motivation for this is to accept testcases such as conv20.C and ttp40

[PATCH] MATCH: Simplify `(X % Y) < Y` pattern.

This merges the two patterns to catch `(X % Y) < Y` and `Y > (X % Y)` into one by using :c on the comparison operator. It does not change any code generation nor anything else. It is more to allow for better maintainability of this pattern. OK? Bootstrapped and tested on x86_64-linux-gnu. gcc/Cha

[PING][PATCH 2/2 v2] Ada: Finalization of constrained subtypes of unconstrained synchronized private extensions

> On Aug 23, 2023, at 10:24, Richard Wai wrote: > > Somehow an error worked its way into the original diff (the diff itself), > making the previous patch fail to apply. > > Fixed version attached. > > Richard Wai > ANNEXI-STRAYLINE > > From: Richard Wai

[PATCH 1/2 v2] Ada: Synchronized private extensions are always limited

Hi Arno, No worries, and sorry for the trouble. I’m going to try using a different client for the gcc mailing list, it doesn’t seem to like Outlook. Thanks for catching that mistake! Please advise how I can get this patch actually applied, given my lack of commit privilege. Revised patch atta

Re: [PATCH v3] c++: Move consteval folding to cp_fold_r

On 9/8/23 14:24, Marek Polacek wrote: On Thu, Sep 07, 2023 at 02:32:51PM -0400, Jason Merrill wrote: On 9/7/23 11:23, Marek Polacek wrote: On Tue, Sep 05, 2023 at 04:36:34PM -0400, Jason Merrill wrote: On 9/5/23 15:59, Marek Polacek wrote: On Tue, Sep 05, 2023 at 10:52:04AM -0400, Jason Merri

Re: libgo: Consider '--with-build-sysroot=[...]' for target libraries' build-tree testing (instead of build-time 'CC' etc.) [PR109951] (was: [PATCH 3/4] libgo/test: Fix compilation for build sysroot)

On Tue, Sep 12, 2023 at 4:16 AM Thomas Schwinge wrote: > > As we've found, this is conceptually problematic, as discussed in > > "Consider '--with-build-sysroot=[...]' for target libraries' build-tree > testing (instead of bu

Re: [PATCH] preprocessor: c++: Support `#pragma GCC target' macros [PR87299]

On Tue, Aug 8, 2023 at 5:53 PM Jason Merrill wrote: > > On 7/31/23 22:22, Lewis Hyatt via Gcc-patches wrote: > > `#pragma GCC target' is not currently handled in preprocess-only mode (e.g., > > when running gcc -E or gcc -save-temps). As noted in the PR, this means that > > if the target pragma de

Re: [PATCH V6] RISC-V: Enable vec_int testsuite for RVV VLA vectorization

> Most (all?) of those are due to: > f951: Warning: command-line option '-Wno-psabi' is valid for > C/C++/D/LTO/ObjC/ObjC++ but not for Fortran > so no real bug. When pushing this, I'd take the liberty of enabling the recently merged vector ABI so we don't require -Wno-psabi anymore. All Fortran

Re: [PATCH] ggc, jit: forcibly clear GTY roots in jit

I added it to bugzilla here: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111396 Since this only reproduces part of the issue, please let me test again with rustc_codegen_gcc after adding the missing fix. I confirmed that the fix is in https://github.com/antoyo/gcc/commit/9d5b6b20efa2082592619675

[V2] RISC-V: Replace not + bitwise_imm with li + bitwise_not

In the case when we have C code like this int foo (int a) { return 100 & ~a; } GCC generates the following instruction sequence foo: not a0,a0 andia0,a0,100 ret This patch replaces that with this sequence foo: li a5,100 andn a0,a5,a0 ret The profitabili

[PATCH] check_GNU_style.py: Skip .md square bracket linting

This testcase causes lots of false-positives for machine description files. contrib/ChangeLog: * check_GNU_style_lib.py: Skip machine description file bracket linting. Signed-off-by: Patrick O'Neill --- contrib/check_GNU_style_lib.py | 3 +++ 1 file changed, 3 insertions(+) diff --git

Re: [committed] libstdc++: Format Python code according to PEP8

On Tue, Sep 12, 2023 at 7:46 AM Jonathan Wakely via Gcc-patches wrote: > > Tested x86_64-linux. Pushed to trunk. > > -- >8 -- > > These files were filtered through autopep8 to reformat them more > conventionally. > Thanks for this; I'm wondering if it might be worthwhile to do likewise for other

Re: [PATCH] ggc, jit: forcibly clear GTY roots in jit

On Tue, 2023-09-12 at 13:36 -0400, Antoni Boucher wrote: > In the mean time, here's a (Rust) reproducer for the issue: > > fn main() { >     for _ in 0..5 { >     let context = Context::default(); >     context.add_command_line_option("-flto"); >     > context.set_optimization_level(Op

Re: [pushed] c++: __integer_pack with class argument [PR111357]

On Tue, Sep 12, 2023 at 01:34:43PM -0400, Marek Polacek via Gcc-patches wrote: > On Tue, Sep 12, 2023 at 01:27:44PM -0400, Jason Merrill via Gcc-patches wrote: > > Tested x86_64-pc-linux-gnu, applying to trunk. > > > > -- 8< -- > > > > The argument might not already be an integer. > > > > PR

Re: [PATCH] ggc, jit: forcibly clear GTY roots in jit

In the mean time, here's a (Rust) reproducer for the issue: fn main() { for _ in 0..5 { let context = Context::default(); context.add_command_line_option("-flto"); context.set_optimization_level(OptimizationLevel::Aggressive); context.add_driver_option("-nostdli

Re: [pushed] c++: __integer_pack with class argument [PR111357]

On Tue, Sep 12, 2023 at 01:27:44PM -0400, Jason Merrill via Gcc-patches wrote: > Tested x86_64-pc-linux-gnu, applying to trunk. > > -- 8< -- > > The argument might not already be an integer. > > PR c++/111357 > > gcc/cp/ChangeLog: > > * pt.cc (expand_integer_pack): Convert argument

[PATCH RFC] diagnostic: add permerror variants with opt

Tested x86_64-pc-linux-gnu. Does this approach make sense to you? Or do you have another idea? Perhaps the warn_system_headers adjustment should also be part of this? -- 8< -- In the discussion of promoting some pedwarns to be errors by default, rather than move them all into -fpermissive it s

[pushed] c++: __integer_pack with class argument [PR111357]

Tested x86_64-pc-linux-gnu, applying to trunk. -- 8< -- The argument might not already be an integer. PR c++/111357 gcc/cp/ChangeLog: * pt.cc (expand_integer_pack): Convert argument to int. gcc/testsuite/ChangeLog: * g++.dg/ext/integer-pack7.C: New test. --- gcc/cp/p

Re: [PATCH] small _BitInt tweaks

On Tue, 12 Sep 2023, Jakub Jelinek via Gcc-patches wrote: > And by ensuring we never create 1-bit signed BITINT_TYPE e.g. the backends > don't need to worry about them. > > But I admit I don't feel strongly about that. > > Joseph, what do you think about this? I think it's appropriate to avoid

[pushed] c++: ICE with -fno-exceptions and array init [PR107198]

Tested x86_64-pc-linux-gnu, applying to trunk. -- 8< -- The removed line no longer has an effect on anew5.C error recovery, and removing it improves error recovery for this testcase. PR c++/107198 gcc/cp/ChangeLog: * typeck2.cc (process_init_constructor_array): Use VEC_INIT_EXP

Re: [PATCH v2 08/11] Native complex ops: Add explicit vector of complex

On Tue, 12 Sep 2023, Sylvain Noiry via Gcc-patches wrote: > Summary: > Allow the creation and usage of builtins vectors of complex > in C, using __attribute__ ((vector_size ())) If you're adding a new language feature like this, you need to update extend.texi to explain the valid uses of the att

Re: RFC: RISC-V sign extension dead code elimination

On 8/29/23 08:40, Joern Rennecke wrote: In the patch call we talked about sign extsnsion elimination, so I dug up this patch set that I did a while ago. It is still lacking some documentation and testing in a more recent base version; I only adjusted the common.opt part context for the patch to

Re: [PATCH][_GLIBCXX_INLINE_VERSION] Fix friend declarations

On Tue, 12 Sept 2023 at 17:47, Jonathan Wakely wrote: > > On Wed, 23 Aug 2023 at 18:35, François Dumont via Libstdc++ > wrote: > > > > Hi > > > > The few tests that are failing in versioned namespace mode are due to > > those friend declarations. > > > > This is a fix proposal even if I considere

Re: [PATCH][_GLIBCXX_INLINE_VERSION] Fix friend declarations

On Wed, 23 Aug 2023 at 18:35, François Dumont via Libstdc++ wrote: > > Hi > > The few tests that are failing in versioned namespace mode are due to > those friend declarations. > > This is a fix proposal even if I considered 2 other options: > > 1. Make __format::_Arg_store a struct and so do not

Re: [PATCH 00/19] aarch64: Fix -fstack-protector issue

On 2023-09-12 11:25, Richard Sandiford via Gcc-patches wrote: This series of patches fixes deficiencies in GCC's -fstack-protector implementation for AArch64 when using dynamically allocated stack space. This is CVE-2023-4039. See: While this is a legitimate missed hardening, I'm not sure if

[PATCH v1] rs6000: unnecessary clear after vctzlsbb in vec_first_match_or_eos_index

This patch removes zero extension from vctzlsbb as it already zero extends. Bootstrapped and regtested on powerpc64-linux-gnu. Thanks & Regards Ajit rs6000: unnecessary clear after vctzlsbb in vec_first_match_or_eos_index For rs6000 target we dont need zero_extend after vctzlsbb as vctzlsbb alre

[OG13][committed] libgomp, nvptx, amdgcn: parallel reverse offload

Here's the same patch, but backported to the OG13 branch. There was one "difficult" conflict, but after reading around the problem I don't think that any actual code changes are required and I've updated the comment to explain (see second patch). Both patches committed to devel/omp/gcc-13. A

[PATCH] RISC-V: Support cond vmulh.vv and vmulu.vv

This patch adds combine patterns to combine vmulh[u].vv + vcond_mask to mask vmulh[u].vv. For vmulsu.vv, it can not be produced in midend currently. We will send another patch to take this issue. gcc/ChangeLog: * config/riscv/autovec-opt.md (*cond_3_highpart): New combine pattern.

[PATCH] RISC-V: Support cond vnsrl/vnsra

This patch add combine patterns to combine vnsra.w[vxi] + vcond_mask to a mask vnsra.w[vxi]. gcc/ChangeLog: * config/riscv/autovec-opt.md (*cond_vtrunc): New combine pattern. (*cond_trunc): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/cond/cond

[PATCH] RISC-V: Support cond vfsgnj.vv autovec pattern

This patch add combine patterns to combine vfsgnj.vv + vcond_mask to mask vfsgnj.vv. For vfsgnjx.vv, it can not be produced in midend currently. We will send another patch to take this issue. gcc/ChangeLog: * config/riscv/autovec-opt.md (*copysign_neg): Move. (*cond_copysign): New

Re: [PATCH] [11/12/13/14 Regression] ABI break in _Hash_node_value_base since GCC 11 [PR 111050]

On Mon, 11 Sept 2023 at 18:19, François Dumont wrote: > > > On 11/09/2023 13:51, Jonathan Wakely wrote: > > On Sun, 10 Sept 2023 at 14:57, François Dumont via Libstdc++ > > wrote: > >> Following confirmation of the fix by TC here is the patch where I'm > >> simply adding a 'constexpr' on _M_next(

Re: [PATCH] ggc, jit: forcibly clear GTY roots in jit

It seems to not be enough to fix the issue. Let me find out what's missing from my patch. On Tue, 2023-09-12 at 11:35 +0200, Richard Biener via Jit wrote: > On Wed, Sep 6, 2023 at 3:41 PM David Malcolm via Gcc-patches > wrote: > > > > As part of Antoyo's work on supporting LTO in rustc_codegen_g

Re: [PATCH V6] RISC-V: Enable vec_int testsuite for RVV VLA vectorization

The current status (for rv64gcv) is: === gcc tests === Running target unix/-march=rv64gcv XPASS: gcc.dg/vect/bb-slp-subgroups-3.c -flto -ffat-lto-objects scan-tree-dump-times slp2 "optimized: basic block" 2 XPASS: gcc.dg/vect/bb-slp-subgroups-3.c scan-tree-dump-times slp2 "optim

[PATCH 2/2] MATCH: Move `X <= MAX(X, Y)` before `MIN (X, C1) < C2` pattern

Since matching C1 as C2 here will decrease how much other simplifications will need to happen to get the final answer. OK? Bootstrapped and tested on x86_64-linux-gnu. gcc/ChangeLog: * match.pd (`X <= MAX(X, Y)`): Move before `MIN (X, C1) < C2` pattern. --- gcc/match.pd | 15 +++

[PATCH 17/19] aarch64: Explicitly record probe registers in frame info

The stack frame is currently divided into three areas: A: the area above the hard frame pointer B: the SVE saves below the hard frame pointer C: the outgoing arguments If the stack frame is allocated in one chunk, the allocation needs a probe if the frame size is >= guard_size - 1KiB. In additio

[PATCH 19/19] aarch64: Make stack smash canary protect saved registers

AArch64 normally puts the saved registers near the bottom of the frame, immediately above any dynamic allocations. But this means that a stack-smash attack on those dynamic allocations could overwrite the saved registers without needing to reach as far as the stack smash canary. The same thing co

[PATCH 16/19] aarch64: Simplify probe of final frame allocation

Previous patches ensured that the final frame allocation only needs a probe when the size is strictly greater than 1KiB. It's therefore safe to use the normal 1024 probe offset in all cases. The main motivation for doing this is to simplify the code and remove the number of special cases. gcc/

[PATCH 08/19] aarch64: Rename locals_offset to bytes_above_locals

locals_offset was described as: /* Offset from the base of the frame (incomming SP) to the top of the locals area. This value is always a multiple of STACK_BOUNDARY. */ This is implicitly an “upside down” view of the frame: the incoming SP is at offset 0, and anything N bytes below

[PATCH 18/19] aarch64: Remove below_hard_fp_saved_regs_size

After previous patches, it's no longer necessary to store saved_regs_size and below_hard_fp_saved_regs_size in the frame info. All measurements instead use the top or bottom of the frame as reference points. gcc/ * config/aarch64/aarch64.h (aarch64_frame::saved_regs_size) (aarch64_

[PATCH 14/19] aarch64: Tweak stack clash boundary condition

The AArch64 ABI says that, when stack clash protection is used, there can be a maximum of 1KiB of unprobed space at sp on entry to a function. Therefore, we need to probe when allocating >= guard_size - 1KiB of data (>= rather than >). This is what GCC does. If an allocation is exactly guard_siz

[PATCH 04/19] aarch64: Add bytes_below_saved_regs to frame info

The frame layout code currently hard-codes the assumption that the number of bytes below the saved registers is equal to the size of the outgoing arguments. This patch abstracts that value into a new field of aarch64_frame. gcc/ * config/aarch64/aarch64.h (aarch64_frame::bytes_below_saved

[PATCH 15/19] aarch64: Put LR save probe in first 16 bytes

-fstack-clash-protection uses the save of LR as a probe for the next allocation. The next allocation could be: * another part of the static frame, e.g. when allocating SVE save slots or outgoing arguments * an alloca in the same function * an allocation made by a callee function However, whe

[PATCH 13/19] aarch64: Minor initial adjustment tweak

This patch just changes a calculation of initial_adjust to one that makes it slightly more obvious that the total adjustment is frame.frame_size. gcc/ * config/aarch64/aarch64.cc (aarch64_layout_frame): Tweak calculation of initial_adjust for frames in which all saves are S

[PATCH 10/19] aarch64: Tweak frame_size comment

This patch fixes another case in which a value was described with an “upside-down” view. gcc/ * config/aarch64/aarch64.h (aarch64_frame::frame_size): Tweak comment. --- gcc/config/aarch64/aarch64.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/config/aarch64/

[PATCH 03/19] aarch64: Explicitly handle frames with no saved registers

If a frame has no saved registers, it can be allocated in one go. There is no need to treat the areas below and above the saved registers as separate. And if we allocate the frame in one go, it should be allocated as the initial_adjust rather than the final_adjust. This allows the frame size to g

[PATCH 11/19] aarch64: Measure reg_offset from the bottom of the frame

reg_offset was measured from the bottom of the saved register area. This made perfect sense with the original layout, since the bottom of the saved register area was also the hard frame pointer address. It became slightly less obvious with SVE, since we save SVE registers below the hard frame point

[PATCH 09/19] aarch64: Rename hard_fp_offset to bytes_above_hard_fp

Similarly to the previous locals_offset patch, hard_fp_offset was described as: /* Offset from the base of the frame (incomming SP) to the hard_frame_pointer. This value is always a multiple of STACK_BOUNDARY. */ poly_int64 hard_fp_offset; which again took an “upside-down” view: h

[PATCH 1/2] MATCH: [PR111364] Add some more minmax cmp operand simplifications

This adds a few more minmax cmp operand simplifications which were missed before. `MIN(a,b) < a` -> `a > b` `MIN(a,b) >= a` -> `a <= b` `MAX(a,b) > a` -> `a < b` `MAX(a,b) <= a` -> `a >= b` OK? Bootstrapped and tested on x86_64-linux-gnu. Note gcc.dg/pr96708-negative.c needed to updated to remov

[PATCH 06/19] aarch64: Tweak aarch64_save/restore_callee_saves

aarch64_save_callee_saves and aarch64_restore_callee_saves took a parameter called start_offset that gives the offset of the bottom of the saved register area from the current stack pointer. However, it's more convenient for later patches if we use the bottom of the entire frame as the reference po

[PATCH 02/19] aarch64: Avoid a use of callee_offset

When we emit the frame chain, i.e. when we reach Here in this statement of aarch64_expand_prologue: if (emit_frame_chain) { // Here ... } the stack is in one of two states: - We've allocated up to the frame chain, but no more. - We've allocated the whole frame, and the fra

[PATCH 12/19] aarch64: Simplify top of frame allocation

After previous patches, it no longer really makes sense to allocate the top of the frame in terms of varargs_and_saved_regs_size and saved_regs_and_above. gcc/ * config/aarch64/aarch64.cc (aarch64_layout_frame): Simplify the allocation of the top of the frame. --- gcc/config/aarch

[PATCH 07/19] aarch64: Only calculate chain_offset if there is a chain

After previous patches, it is no longer necessary to calculate a chain_offset in cases where there is no chain record. gcc/ * config/aarch64/aarch64.cc (aarch64_expand_prologue): Move the calculation of chain_offset into the emit_frame_chain block. --- gcc/config/aarch64/aarch64.c

[PATCH 05/19] aarch64: Add bytes_below_hard_fp to frame info

Following on from the previous bytes_below_saved_regs patch, this one records the number of bytes that are below the hard frame pointer. This eventually replaces below_hard_fp_saved_regs_size. If a frame pointer is not needed, the epilogue adds final_adjust to the stack pointer before restoring re

[PATCH 01/19] aarch64: Use local frame vars in shrink-wrapping code

aarch64_layout_frame uses a shorthand for referring to cfun->machine->frame: aarch64_frame &frame = cfun->machine->frame; This patch does the same for some other heavy users of the structure. No functional change intended. gcc/ * config/aarch64/aarch64.cc (aarch64_save_callee_saves): U

[PATCH 00/19] aarch64: Fix -fstack-protector issue

This series of patches fixes deficiencies in GCC's -fstack-protector implementation for AArch64 when using dynamically allocated stack space. This is CVE-2023-4039. See: https://developer.arm.com/Arm%20Security%20Center/GCC%20Stack%20Protector%20Vulnerability%20AArch64 https://github.com/metaredt

gcc-patches From rewriting mailman settings (Was: [Linaro-TCWG-CI] gcc patch #75674: FAIL: 68 regressions)

Hi Maxim, Adding Jeff to CC who is the official gcc-patches mailinglist admin. On Tue, 2023-09-12 at 11:08 +0400, Maxim Kuvyrkov wrote: > Normally, notifications from Linaro TCWG precommit CI are sent only to > patch author and patch submitter. In this case the sender was rewritten > to "Benjami

[PATCH] libgomp, nvptx, amdgcn: parallel reverse offload

Hi all, This patch implements parallel execution of OpenMP reverse offload kernels. The first problem was that GPU device kernels may request reverse offload (via the "ancestor" clause) once for each running offload thread -- of which there may be thousands -- and the existing implementation

[PATCH 14/13] libstdc++: Re-initialize static data files used by tests

This fixes the problem observed with some filebuf tests. The "@require@" string seems a bit hacky, as I don't know why that string is in the tests in the first palce ... but it is there, so this works. -- > 8-- Some tests rely on text files with specific content being present in the test directo

Re: [PATCH V2] RISC-V: Support VECTOR BOOL vcond_mask optab[PR111337]

The PR thing needs to be moved but I can commit it. Regards Robin

Re: Re: [PATCH] RISC-V: Support VECTOR BOOL vcond_mask optab[PR111337]

Ok add it in V2: https://gcc.gnu.org/pipermail/gcc-patches/2023-September/630048.html juzhe.zh...@rivai.ai From: Robin Dapp Date: 2023-09-12 21:29 To: Juzhe-Zhong; gcc-patches CC: rdapp.gcc; kito.cheng; kito.cheng; jeffreyalaw Subject: Re: [PATCH] RISC-V: Support VECTOR BOOL vcond_mask optab

[PATCH V2] RISC-V: Support VECTOR BOOL vcond_mask optab[PR111337]

PR target/111337 As this PR: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111337 We support VECTOR BOOL vcond_mask to fix this following ICE: 0x1a9e309 gimple_expand_vec_cond_expr ../../../../gcc/gcc/gimple-isel.cc:283 0x1a9ea56 execute ../../../../gcc/gcc/gimple-isel.cc:390 g

Re: [PATCH] RISC-V: Support VECTOR BOOL vcond_mask optab[PR111337]

Maybe you want to add PR target/111337 to the changelog? The rest LGTM. Regards Robin

RE: [PATCH v1] RISC-V: Remove unused structure in cost model

Committed, thanks Jeff. Pan -Original Message- From: Jeff Law Sent: Tuesday, September 12, 2023 9:12 PM To: Li, Pan2 ; gcc-patches@gcc.gnu.org Cc: Wang, Yanzhang ; kito.ch...@gmail.com; juzhe.zh...@rivai.ai Subject: Re: [PATCH v1] RISC-V: Remove unused structure in cost model On 9/1

[PATCH] RISC-V: Support VECTOR BOOL vcond_mask optab[PR111337]

As this PR: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111337 We support VECTOR BOOL vcond_mask to fix this following ICE: 0x1a9e309 gimple_expand_vec_cond_expr ../../../../gcc/gcc/gimple-isel.cc:283 0x1a9ea56 execute ../../../../gcc/gcc/gimple-isel.cc:390 gcc/ChangeLog:

Re: [PATCH 3/3] libstdc++: Fix std::not_fn perfect forwarding [PR111327]

On Tue, 12 Sept 2023 at 02:11, Patrick Palka via Libstdc++ wrote: > > The previous patch fixed perfect forwarding for std::bind_front. > This patch fixes the same issue for std::not_fn. > > Tested on x86_64-pc-linux-gnu, does this look OK for trunk and > perhaps 13? Yes for both, thanks. > >

Re: [PATCH 2/3] libstdc++: Fix std::bind_front perfect forwarding [PR111327]

On Tue, 12 Sept 2023 at 02:09, Patrick Palka via Libstdc++ wrote: > > In order to properly implement a perfect forwarding call wrapper > (before 'deducing this' at least) we need a total of 8 operator() > overloads, 4 main ones and 4 deleted ones for each const/ref qual pair, > as described in sec

Re: [PATCH 1/3] libstdc++: Remove std::bind_front specialization for no bound args

On Tue, 12 Sept 2023 at 13:46, Patrick Palka via Libstdc++ wrote: > > On Mon, 11 Sep 2023, Patrick Palka wrote: > > > This specialization for the case of no bound args, added by > > r13-4214-gcbd05ca5ab1231, seems to be mostly obsoleted by > > r13-5033-ge2eab3c4edb6aa which added [[no_unique_addre

Re: [PATCH v1] RISC-V: Remove unused structure in cost model

On 9/12/23 07:02, Pan Li via Gcc-patches wrote: From: Pan Li The struct range is unused, remove it. gcc/ChangeLog: * config/riscv/riscv-vector-costs.h (struct range): Removed. OK jeff

Re: [PATCH 00/13] libstdc++: Add support for running tests with multiple -std options

On Mon, 11 Sept 2023 at 17:37, Jonathan Wakely via Libstdc++ wrote: > > This patch series replicates the behaviour of the g++ testsuite, so that > libstdc++ tests can easily be run for multiple different -std options in > a single testsuite run. As described in the updated docs, the -std > option

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