ok
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-07-31 14:52
To: gcc-patches; kito.cheng; juzhe.zhong; rdapp.gcc; pan2.li
CC: Kito Cheng
Subject: [PATCH] RISC-V: Return machine_mode rather than opt_machine_mode for
get_mask_mode, NFC
We always want get_mask_mode return a valid mode, it's s
Hi Carl,
on 2023/7/28 23:00, Carl Love wrote:
> GCC maintainers:
>
> The following patch cleans up the definition for the
> __builtin_altivec_vcmpnet. The current implementation implies that the
s/__builtin_altivec_vcmpnet/__builtin_altivec_vcmpne[bhw]/
> built-in is only supported on Power 9
We always want get_mask_mode return a valid mode, it's something wrong
if it failed, so I think we could just move the `.require ()` into
get_mask_mode, instead of calling that every call-site.
The only exception is riscv_get_mask_mode, it might put supported mode
into get_mask_mode, so added a ch
> +;; -
> +;; Duplicate Operations
> +;; -
> +
> +(define_insn_and_split "@vec_duplicate"
> + [(set (match_operand:VLS 0 "register_operand")
> +(vec_duplicat
ChangeLog:
* MAINTAINERS (Write After Approval): Add myself.
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 49aa6bae73b..90e2c81f0c2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -460,6 +460,7 @@ Matthew Hiller
Hi Haochen,
on 2023/7/25 10:10, HAO CHEN GUI wrote:
> Hi,
> This patch modifies vsx extract expand and generates mfvsrwz/stxsiwx
> for all subtargets when the mode is V4SI and the index of extracted element
> is 1 for BE and 2 for LE. Also this patch adds a insn pattern for mfvsrwz
> which helps
Even though these are done by combine_comparisons, we can add them to match
to allow simplifcations during match rather than just during reassoc/ifcombine.
OK? Bootstrapped and tested on x86_64-linux-gnu with no regressions.
gcc/ChangeLog:
PR tree-optimization/106164
* match.pd (
I noticed that there are patterns that optimize
`(X CMP1 CST1) AND/IOR (X CMP2 CST2)` and we can easily extend
them to support the `(X CMP1 Y) AND/IOR (X CMP2 Y)` by saying they
compare equal. This allows for this kind of optimization for integral
and pointer types (which have the same semantics).
Committed, thanks Kito.
Pan
-Original Message-
From: Kito Cheng
Sent: Monday, July 31, 2023 10:58 AM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
Subject: Re: [PATCH v1] RISC-V: Bugfix for RVV floating-point rm suffix sequence
lgtm
On Mon, Jul 31,
lgtm
On Mon, Jul 31, 2023 at 10:56 AM wrote:
>
> From: Pan Li
>
> According to below RVV intrinsic doc, the RVV floating-point intrinsic name
> with rounding mode should be:
>
> _rm_m
>
> instead of:
>
> _m_rm
>
> https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/226
>
> This patch fix thi
From: Pan Li
According to below RVV intrinsic doc, the RVV floating-point intrinsic name
with rounding mode should be:
_rm_m
instead of:
_m_rm
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/226
This patch fix this naming sequence issue and adjust the test cases.
Signed-off-by: Pan
Committed, thanks Kito.
Pan
-Original Message-
From: Gcc-patches On Behalf
Of Kito Cheng via Gcc-patches
Sent: Monday, July 31, 2023 10:42 AM
To: Juzhe-Zhong
Cc: gcc-patches@gcc.gnu.org; kito.ch...@sifive.com; jeffreya...@gmail.com;
rdapp@gmail.com
Subject: Re: [PATCH V2] RISC-V:
LGTM, thanks :)
On Mon, Jul 31, 2023 at 10:14 AM Juzhe-Zhong wrote:
>
> Consider this following case:
> void
> foo (int8_t *in, int8_t *out, int8_t x)
> {
> for (int i = 0; i < 16; i++)
> in[i] = x;
> }
>
> Compile option: --param=riscv-autovec-preference=scalable -fno-builtin
>
> Before th
> Which test case do you see this for? The two tests in the patch still
> seem to report correct latencies for me if I make the change above.
Not the newly added tests. It is still the existing case causing the previous
ICE (i.e. assertion problem): gcc.target/aarch64/sve/cost_model_13.c.
It's
Address comment V2:
https://gcc.gnu.org/pipermail/gcc-patches/2023-July/625799.html
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-07-31 09:55
To: Juzhe-Zhong
CC: gcc-patches; kito.cheng; rdapp.gcc; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Enable basic VLS auto-vectorization
Hi Juzhe:
>
Consider this following case:
void
foo (int8_t *in, int8_t *out, int8_t x)
{
for (int i = 0; i < 16; i++)
in[i] = x;
}
Compile option: --param=riscv-autovec-preference=scalable -fno-builtin
Before this patch:
foo:
li a5,16
csrra4,vlenb
vsetvli a3,zero,e8,m1
Hi Juzhe:
> * config/riscv/riscv.cc (riscv_estimated_poly_value): Fix incorrect
> poly estimation.
Is it a necessary change for the VLS autovectorizaion or could it be a
separate change??
From: xuli
Signed-off-by: Li Xu
ChangeLog:
* MAINTAINERS: Add myself.
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index e9b11b43a0f..49aa6bae73b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -712,6 +712,7 @@ Jonathan Wright
---
htdocs/gcc-4.5/changes.html | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/htdocs/gcc-4.5/changes.html b/htdocs/gcc-4.5/changes.html
index 2e8f56a7..3d645bb3 100644
--- a/htdocs/gcc-4.5/changes.html
+++ b/htdocs/gcc-4.5/changes.html
@@ -18,7 +18,7 @@
GCC now r
Also introduce -m[no-]mmxfp-with-sse option to disable trapping V2SF
named patterns in order to avoid generation of partial vector V4SFmode
trapping instructions.
The new option is enabled by default, because even with sanitization,
a small but consistent speed up of 2 to 3% with Polyhedron capaci
Committed as obvious.
libstdc++: Fix several preprocessor directives
A wrong usage of #define in place of a #error seems to have been
replicated
at different places in source files.
libstdc++-v3/ChangeLog:
* src/c++11/compatibility-ldbl-facets-aliases.h: Replace
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