On Tue, Jul 11, 2023 at 06:02:18PM +0200, Christoph Müllner wrote:
> Hi Kito,
>
> I take some of the blame because I have sent a series
> that consisted of fixes followed by new features.
>
> You have ack'ed patches 1-9 from the series.
> The last two patches (for XTheadMemIdx and XTheadFMemIdx)
From: Sun Haiyong
gcc/ChangeLog:
* config.gcc: Add some include file in tm_file.
---
gcc/config.gcc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 51ca5311fa4..b901aa8e5dc 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -24
+regnum_definition_p (rtx_insn *insn, unsigned int regno)I prefer it to be
reg_set_p.
+insn_asm_p (rtx_insn *insn)asm_insn_p
+global_vxrm_state_unknown_pvxrm_unknown_p
+global_frm_state_unknown_p (rtx_insn *insn)FRM of CALL function is not
"UNKNOWN" unlike VXRM.It just change into another unknown
I understand your concern. I CC Richards to see whether this piece of codes is
unsafe.
Hi, Richard and Richi:
Jeff is worrying about this codes in "expand_gather_scatter" of supporting
len_mask_gather_load/len_mask_scatter_store in RISC-V port.
The codes are as follows:
+/* Return true if i
> -Original Message-
> From: Mo, Zewei
> Sent: Wednesday, July 12, 2023 1:56 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Liu, Hongtao ; ubiz...@gmail.com
> Subject: [PATCH] Initial Granite Rapids D Support
>
> Hi all,
>
> This patch is to add initial support for Granite Rapids D for GCC.
>
Hi all,
This patch is to add initial support for Granite Rapids D for GCC.
The link of related information is listed below:
https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html
Also, the patch of removing AMX-COMPLEX fr
From: Pan Li
When investigate the FRM dynmaic rounding mode, we find the global
unknown status is quite different between the fixed-point and
floating-point. Thus, we separate the unknown function with extracting
some inner common functions.
We will also prepare more test cases in another PATCH.
From: Pan Li
When investigate the FRM dynmaic rounding mode, we find the global
unknown status is quite different between the fixed-point and
floating-point. Thus, we separate the unknown function with extracting
some inner common functions.
We will also prepare more test cases in another PATCH.
On 7/11/23 20:34, juzhe.zh...@rivai.ai wrote:
Hi, Jeff.
>> Hmm, I'm not sure this is safe, especially if gimple->rtl expansion is
complete. While you might be able to get REG_EXPR, I would not really
expect SSA_NAME_DEF_STMT to be correct. At the least it'll need some
way to make sure it'
This patch is depending on the following patch on Vectorizer:
https://gcc.gnu.org/pipermail/gcc-patches/2023-July/624179.html
With this patch, we can handle operations may trap on elements outside the loop.
These 2 following cases will be addressed by this patch:
1. integer division:
#define
On 10/07/2023 07:23, Ken Matsui via Libstdc++ wrote:
This patch implements built-in trait for std::is_pointer.
gcc/cp/ChangeLog:
* cp-trait.def: Define __is_pointer.
* constraint.cc (diagnose_trait_expr): Handle CPTK_IS_POINTER.
* semantics.cc (trait_expr_value): Likew
From: Ju-Zhe Zhong
Hi, Richard and Richi.
As we disscussed before, COND_LEN_* patterns were added for multiple situations.
This patch apply CON_LEN_* for the following situation:
Support for the situation that in "vectorizable_operation":
/* If operating on inactive elements could generate spu
Hi,
This tiny patch add --append option to mklog.py that support add generated
ChangeLog to the corresponding patch file. With this option there is no need
to manually copy the generated ChangeLog to the patch file. e.g.:
Run `mklog.py -a /path/to/this/patch` will add the generated ChangeLog
```
LGTM
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-07-12 11:27
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; kito.cheng; palmer; jeffreyalaw
Subject: [PATCH] RISC-V: Throw compilation error for unknown sub-extension or
supervisor extension
Hi,
This tiny patch add a check for extension star
Hi,
This tiny patch add a check for extension starts with 'z' or 's' in `-march`
option. Currently this unknown extension will be passed to the assembler, which
then reports an error. With this patch, the compiler will throw a compilation
error if the extension starts with 'z' or 's' is not a stan
PR #104914
When work with
int val;
((unsigned char*)&val)[0] = *buf;
The RTX mode is obtained from REG instead of SUBREG,
which make D is used instead of .
Thus something wrong happens on sign-extend default architectures,
like MIPS64.
gcc/ChangeLog:
PR: 104914.
* expmed.cc(st
Hi, Jeff.
>> Hmm, I'm not sure this is safe, especially if gimple->rtl expansion is
>> complete. While you might be able to get REG_EXPR, I would not really
>> expect SSA_NAME_DEF_STMT to be correct. At the least it'll need some
>> way to make sure it's not called at an inappropriate time.
I thi
On 7/10/23 22:44, Christoph Muellner wrote:
From: Christoph Müllner
Recently, two identical XTheadCondMov tests have been added, which both fail.
Let's fix that by changing the following:
* Merge both files into one (no need for separate tests for rv32 and rv64)
* Drop unrelated attribute ch
On 7/7/23 08:32, Juzhe-Zhong wrote:
This patch fully support gather_load/scatter_store:
1. Support single-rgroup on both RV32/RV64.
2. Support indexed element width can be same as or smaller than Pmode.
3. Support VLA SLP with gather/scatter.
4. Fully tested all gather/scatter with LMUL = M1/M
On Wed, Jul 12, 2023 at 4:57 AM Roger Sayle wrote:
>
>
> > From: Hongtao Liu
> > Sent: 28 June 2023 04:23
> > > From: Roger Sayle
> > > Sent: 27 June 2023 20:28
> > >
> > > I've also come up with an alternate/complementary/supplementary
> > > fix of generating the PTEST during RTL expansion, rat
Committed, thanks Jeff.
Pan
-Original Message-
From: Gcc-patches On Behalf
Of Jeff Law via Gcc-patches
Sent: Wednesday, July 12, 2023 7:19 AM
To: juzhe.zh...@rivai.ai; gcc-patches@gcc.gnu.org
Cc: kito.ch...@gmail.com; kito.ch...@sifive.com; rdapp@gmail.com
Subject: Re: [PATCH] RISC-
May I please ping this patch again? I think it would be worthwhile to
close this gap in the support for UTF-8 sources. Thanks!
https://gcc.gnu.org/pipermail/gcc-patches/2023-March/613247.html
-Lewis
On Fri, Jun 2, 2023 at 9:45 AM Lewis Hyatt wrote:
>
> Hello-
>
> Ping please? Thanks.
> https://g
On 7/11/23 00:38, juzhe.zh...@rivai.ai wrote:
From: Ju-Zhe Zhong
This patch is to recognize specific permutation pattern which can be applied
compress approach.
Consider this following case:
#include
typedef int8_t vnx64i __attribute__ ((vector_size (64)));
#define MASK_64
On 7/11/23 04:37, Andre Vieira (lists) via Gcc-patches wrote:
Hi,
This patch fixes PR110610 by including OPTABS_H in the INTERNAL_FN_H
list, as insn-opinit.h is now required by internal-fn.h. This will lead
to insn-opinit.h, among the other OPTABS_H header files, being installed
in the plu
This patch updates btfout.cc to be aware of BTF_KIND_DECL_TAG types and
output them appropriately.
gcc/
* btfout.cc (funcs_map): New hash map.
(btf_emit_preprocess): ... Initialize it here...
(btf_collect_datasec): ... Populate it here...
(btf_finalize): ... And fr
Add the "btf_decl_tag" attribute to the attribute table, along with
a simple handler for it.
gcc/c-family/
* c-attribs.cc (c_common_attribute_table): Add btf_decl_tag.
(handle_btf_decl_tag_attribute): Handle new attribute.
---
gcc/c-family/c-attribs.cc | 23 ++
This patch adds tests for the btf_decl_tag attribute, in both DWARF
and BTF.
gcc/testsuite/
* gcc.dg/debug/btf/btf-decltag-func.c: New test.
* gcc.dg/debug/btf/btf-decltag-sou.c: New test.
* gcc.dg/debug/btf/btf-decltag-var.c: New test.
* gcc.dg/debug/dwarf2/annota
This patch makes the DWARF-to-CTF conversion process aware of the new
DW_TAG_GNU_annotation DIEs. The DIEs are converted to CTF_K_DECL_TAG
types and added to the compilation unit CTF container to be translated
to BTF and output.
gcc/
* dwarf2ctf.cc (handle_btf_tags): New function.
Add documentation for the btf_decl_tag attribute.
gcc/
* doc/extend.texi (Common Function Attributes): Document btf_decl_tag.
(Common Variable Attributes): Likewise.
---
gcc/doc/extend.texi | 47 +
1 file changed, 47 insertions(+)
diff
Expose get_die_parent () so it can be used outside of dwarf2out.cc
gcc/
* dwarf2out.cc (get_die_parent): Make non-static.
* dwarf2out.h (get_die_parent): Add extern declaration here.
---
gcc/dwarf2out.cc | 2 +-
gcc/dwarf2out.h | 1 +
2 files changed, 2 insertions(+), 1 deletion
The "btf_decl_tag" attribute is handled by constructing a
DW_TAG_GNU_annotation DIE for each occurrence to record the argument
string in debug information. The DIEs are children of the declarations
they annotate, with the following format:
DW_TAG_GNU_annotation
DW_AT_name "btf_decl_tag"
BTF generation currently relies on the internal CTF representation to
convert debug info from DWARF dies. This patch adds a new internal
header, "ctf-int.h", which defines CTF kinds to be used internally to
represent BTF tags which must pass through the CTF container. It also
adds a new type for re
Add definitions for btf_decl_tag and the DW_TAG_GNU_annotation
DWARF extension.
include/
* btf.h (struct btf_type): Update comment.
(BTF_KIND_DECL_TAG): New define.
(struct btf_decl_tag): New.
* dwarf2.def (DW_TAG_GNU_annotation): New DW_TAG extension.
---
include
Hello,
This series adds support for a new attribute, "btf_decl_tag" in GCC.
The same attribute is already supported in clang, and is used by various
components of the BPF ecosystem.
The purpose of the attribute is to allow to associate (to "tag")
declarations with arbitrary string annotations, wh
Hi Andre,
I forgot to answer your other question:
Am 11.07.23 um 18:23 schrieb Andre Vehreschild via Gcc-patches:
I tried to use a pdt within a derived type as a component. Is that not allowed
by the standard? I know, I could hunt in the standard for it, but when someone
knows out of his head,
> From: Hongtao Liu
> Sent: 28 June 2023 04:23
> > From: Roger Sayle
> > Sent: 27 June 2023 20:28
> >
> > I've also come up with an alternate/complementary/supplementary
> > fix of generating the PTEST during RTL expansion, rather than rely on
> > this being caught/optimized later during STV.
>
Attached is v2 that does not switch to uint64_t but stays within
32 bits by shifting the optab by 20 and the mode(s) by 10 bits.
Regards
Robin
Upcoming changes for RISC-V will have us exceed 255 modes or 8 bits.
This patch increases the limit to 10 bits and adjusts the hashing
function for the g
Hi Andre,
this looks much better now!
This looks mostly good to me, except for a typo in the testcase:
+ if (p% ci% len /= 42) stop 4
There is no component "ci", only "c". The testsuite would fail.
Regarding the memleak: replacing
// TODO: Fix leaking expr tmp, when simplify is done
The recent change in TImode parameter passing on x86_64 results in the
FAIL of pr91681-1.c. The issue is that with the extra flexibility,
the combine pass is now spoilt for choice between using either the
*add3_doubleword_concat or the *add3_doubleword_zext
patterns, when one operand is a *concat
On Tue, Jul 11, 2023 at 09:39:31PM +0200, Harald Anlauf via Fortran wrote:
> Dear all,
>
> for intrinsic procedures we derive the typespec of the formal symbol
> attributes from the actual arguments. This can have an undesired
> effect for character actual arguments, as the argument passing
> con
Dear all,
for intrinsic procedures we derive the typespec of the formal symbol
attributes from the actual arguments. This can have an undesired
effect for character actual arguments, as the argument passing
conventions differ for deferred-length (length is passed by reference)
and otherwise (leng
This patch fixes the regression PR target/110598 caused by my recent
addition of a peephole2. The intention of that optimization was to
simplify zeroing a register, followed by an IOR, XOR or PLUS operation
on it into a move, or as described in the comment:
;; Peephole2 rega = 0; rega op= regb in
GCC maintainers:
Ver 4, Removed extra space in subject line. Added comment to commit
log comments about new __SET_FPSCR_RN_RETURNS_FPSCR__ define. Changed
Added to Add and Renamed to Rename in ChangeLog. Updated define_expand
"rs6000_set_fpscr_rn" per Peter's comments to use new temporary
regis
On Tue, 2023-07-11 at 13:54 +0800, Kewen.Lin wrote:
> Hi Carl,
>
> Excepting for Peter's review comments, some nits are inline below.
>
> on 2023/7/11 03:18, Carl Love wrote:
> > GCC maintainers:
> >
> >
> >
> > -
> > rs6000, Add return value
On Tue, 11 Jul 2023, Michael Matz wrote:
> Hey,
>
> On Tue, 11 Jul 2023, Alexander Monakov via Gcc-patches wrote:
>
> > > > > * nosseclobber: claims (and ensures) that xmm8-15 aren't clobbered
> > > >
> > > > This is the weak/active form; I'd suggest "preserve_high_sse".
> > >
> > > But it
Also change some internal variables from int to bool.
gcc/ChangeLog:
* cfghooks.cc (verify_flow_info): Change "err" variable to bool.
* cfghooks.h (struct cfg_hooks): Change return type of
verify_flow_info from integer to bool.
* cfgrtl.cc (can_delete_note_p): Change return type f
Hi Harald,
attached is a new version of the patch. This now also respects inquiry-LEN.
Btw, there is a potential memory leak in the simplify for inquiry functions. I
have added a note into the code.
I tried to use a pdt within a derived type as a component. Is that not allowed
by the standard? I
Robin Dapp writes:
> Ok so the consensus seems to rather stay with 32 bits and only
> change the shift to 10/20?
Yeah. The check would then be:
if (NUM_OPTABS > 0xfff || NUM_MACHINE_MODES > 0x3ff)
fatal ("genopinit range assumptions invalid");
> As MACHINE_MODE_BITSIZE is already
> 16 we
Hi Kito,
I take some of the blame because I have sent a series
that consisted of fixes followed by new features.
You have ack'ed patches 1-9 from the series.
The last two patches (for XTheadMemIdx and XTheadFMemIdx) were
later reviewed by Jeff and need a bit rework and more testing.
If it helps,
Hi Christoph:
Ooops, I thought Philipp will push those patches, does here any other
patches got approved but not committed? I can help to push those
patches tomorrow.
On Tue, Jul 11, 2023 at 11:42 PM Christoph Müllner
wrote:
>
> Hi Cooper,
>
> I addressed this in April this year.
> It even got a
Hi Cooper,
I addressed this in April this year.
It even got an "ok", but nobody pushed it:
https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616972.html
BR
Christoph
On Tue, Jul 11, 2023 at 5:39 PM Xianmiao Qu wrote:
>
> The frame related load/store instructions should not been
> scheduled
The frame related load/store instructions should not been
scheduled bewteen echo other, and the REG_FRAME_RELATED_EXPR
expression note should should be added to those instructions
to prevent this.
This bug cause ICE during GCC bootstap, and it will also ICE
in the simplified case mempair-4.c, compi
Hey,
On Tue, 11 Jul 2023, Alexander Monakov via Gcc-patches wrote:
> > > > * nosseclobber: claims (and ensures) that xmm8-15 aren't clobbered
> > >
> > > This is the weak/active form; I'd suggest "preserve_high_sse".
> >
> > But it preserves only the low parts :-) You swapped the two in your
* Richard Earnshaw:
> On 11/07/2023 10:37, Florian Weimer via Gcc-patches wrote:
>> libgcc/
>> * config/aarch64/aarch64-unwind.h
>> (aarch64_cie_signed_with_b_key):
>> Add missing const qualifier. Cast from const unsigned char *
>> to const char *. Use __builtin_strchr to avoid an
On Tue, 11 Jul 2023, Michael Matz wrote:
> > > To that end I introduce actually two related attributes (for naming
> > > see below):
> > > * nosseclobber: claims (and ensures) that xmm8-15 aren't clobbered
> >
> > This is the weak/active form; I'd suggest "preserve_high_sse".
>
> But it preser
On 11/07/2023 15:54, Richard Earnshaw (lists) via Gcc-patches wrote:
On 11/07/2023 10:37, Florian Weimer via Gcc-patches wrote:
libgcc/
* config/aarch64/aarch64-unwind.h (aarch64_cie_signed_with_b_key):
Add missing const qualifier. Cast from const unsigned char *
to const char *.
On Fri, 7 Jul 2023, Richard Biener wrote:
> > The pr97428.c test assumes support for vectors of doubles, but some
> > targets only support vectors of floats, causing this test to fail with
> > such targets. Limit this test to targets that support vectors of
> > doubles then.
>
> OK.
Applied, t
On Fri, 7 Jul 2023, Richard Biener wrote:
> > The bb-slp-pr95839.c test assumes quad-single float vector support, but
> > some targets only support pairs of floats, causing this test to fail
> > with such targets. Limit this test to targets that support at least
> > 128-bit vectors then, and add
On Fri, 7 Jul 2023, Richard Biener wrote:
> > Similarly to checks for vectors of 32 bits and 64 bits being supported
> > add one for vectors of 128 bits.
>
> OK
Thanks for the review, however this is only needed for 2/3 at this point,
so I'll only push it if 2/3 gets a go-ahead (and still need
Hello,
On Mon, 10 Jul 2023, Alexander Monakov wrote:
> I think the main question is why you're going with this (weak) form
> instead of the (strong) form "may only clobber the low XMM regs":
I want to provide both. One of them allows more arbitrary function
definitions, the other allows more r
On 11/07/2023 10:37, Florian Weimer via Gcc-patches wrote:
libgcc/
* config/aarch64/aarch64-unwind.h (aarch64_cie_signed_with_b_key):
Add missing const qualifier. Cast from const unsigned char *
to const char *. Use __builtin_strchr to avoid an implicit
function
I have now committed this (mostly .texi) patch as Rev.
r14-2434-g8c2fc744a25ec4
Changes to my previously posted version: Fixed a typo in .texi and in
the changelog, tweaked the wording for {nearest} to sound better and to
provide more details.
Tobias
On 11.07.23 00:07, Tobias Burnus wrote:
I n
Hello,
On Tue, 11 Jul 2023, Jan Hubicka wrote:
> > > > When a function doesn't contain calls to
> > > > unknown functions we can be a bit more lenient: we can make it so that
> > > > GCC simply doesn't touch xmm8-15 at all, then no save/restore is
> > > > necessary.
>
> One may also take into ac
On Tue, 11 Jul 2023, Richard Biener wrote:
> > > If a function contains calls then GCC can't know which
> > > parts of the XMM regset is clobbered by that, it may be parts
> > > which don't even exist yet (say until avx2048 comes out), so we must
> > > restrict ourself to only save/restore the S
On Tue, Jul 11, 2023 at 3:08 PM Jakub Jelinek wrote:
>
> On Thu, Jul 06, 2023 at 03:00:28PM +0200, Richard Biener via Gcc-patches
> wrote:
> > On Wed, Jul 5, 2023 at 3:42 PM Drew Ross via Gcc-patches
> > wrote:
> > >
> > > Adds a simplification for (~X | Y) ^ X to be folded into ~(X & Y).
>
On 7/11/23 03:39, Florian Weimer via Gcc-patches wrote:
libgcc/
* config/or1k/linux-unwind.h (or1k_fallback_frame_state): Add
missing cast.
OK
jeff
On 7/11/23 03:39, Florian Weimer via Gcc-patches wrote:
libgcc/
* config/arc/linux-unwind.h (arc_fallback_frame_state): Add
missing cast.
OK
jeff
On 7/11/23 03:38, Florian Weimer via Gcc-patches wrote:
libgcc/
* config/riscv/linux-unwind.h (riscv_fallback_frame_state): Add
missing cast.
OK
jeff
On 7/11/23 03:38, Florian Weimer via Gcc-patches wrote:
libgcc/
* config/csky/linux-unwind.h (csky_fallback_frame_state): Add
missing cast.
OK
jeff
Sorry for sending incorrect email.
Forget about this:).
juzhe.zh...@rivai.ai
From: 钟居哲
Date: 2023-07-11 21:55
To: rdapp.gcc; gcc-patches; Jeff Law; richard.sandiford; rguenther
CC: rdapp.gcc
Subject: Re: [PATCH] genopinit: Allow more than 256 modes.
For example:
https://godbolt.org/z/1d6v
For example:
https://godbolt.org/z/1d6v5WKhY
Clang can vectorize but GCC failed even with -ffast-math.
So I think conversions should be well checked again to make sure every variant
can vectorize.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-07-11 21:31
To: Robin Dapp via Gcc-p
On 7/11/23 03:38, Florian Weimer via Gcc-patches wrote:
libgcc/
* config/m68k/fpgnulib.c (__cmpdf2): Declare.
OK.
jeff
Ok.
On Tue, Jul 11, 2023, 9:16 AM Patrick Palka wrote:
> Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for
> trunk?
>
> -- >8 --
>
> Here during ahead of time coercion of the variable template-id v1,
> since we pass only the innermost arguments to coerce_template_parms (an
Antony Polukhin 2023-07-11 09:51:58 UTC
There's a typo at
https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=gcc/testsuite/g%2B%2B.target/i386/pr110170.C;h=e638b12a5ee2264ecef77acca86432a9f24b103b;hb=d41a57c46df6f8f7dae0c0a8b349e734806a837b#l87
It should be `|| !test3() || !test3r()` rather than `|| !te
Ok so the consensus seems to rather stay with 32 bits and only
change the shift to 10/20? As MACHINE_MODE_BITSIZE is already
16 we would need an additional check independent of that.
Wouldn't that also be a bit confusing?
Attached is a "v2" with unsigned long long changed to
uint64_t and checking
> > > When a function doesn't contain calls to
> > > unknown functions we can be a bit more lenient: we can make it so that
> > > GCC simply doesn't touch xmm8-15 at all, then no save/restore is
> > > necessary.
One may also take into account that first 8 registers are cheaper to
encode than the l
Hi Mikhail,
That's more than OK by me.
Thanks for attacking this PR.
I have a couple more of Steve's orphans waiting to be packaged up -
91960 and 104649. I'll submit them this evening.100607 is closed-fixed
and 103796 seems to be fixed.
Regards
Paul
On Tue, 11 Jul 2023 at 13:08, Mikael Morin
On Thu, Jul 06, 2023 at 03:00:28PM +0200, Richard Biener via Gcc-patches wrote:
> On Wed, Jul 5, 2023 at 3:42 PM Drew Ross via Gcc-patches
> wrote:
> >
> > Adds a simplification for (~X | Y) ^ X to be folded into ~(X & Y).
> > Tested successfully on x86_64 and x86 targets.
> >
> >
On Tue, 11 Jul 2023, Jan Hubicka wrote:
> > > By now we did CCP and FRE so we likely optimized out most of constant
> > > conditionals exposed by inline.
> >
> > So maybe we should simply delay re-propagation of the profile? I
> > think cunrolli doesn't so much care about the profile - cunrolli
On Tue, 11 Jul 2023, ??? wrote:
> Thanks for fixing it.
> CC Richards to see whether it is appropriate.
I agree with Richard S., but generally please avoid
'long long' and use stdint types when you need specific
precision.
Richard.
>
>
> juzhe.zh...@rivai.ai
>
> From: Robin Dapp
> Date: 202
> if (NUM_OPTABS > 0x
> || MAX_MACHINE_MODE >= ((1 << MACHINE_MODE_BITSIZE) - 1))
> fatal ("genopinit range assumptions invalid");
>
> so it would be a case of changing those instead.
Thanks, right at the beginning of the file and I didn't see it ;)
MACHINE_MODE_BITSIZE is already 1
On Mon, Jul 10, 2023 at 9:08 PM Alexander Monakov via Gcc-patches
wrote:
>
>
> On Mon, 10 Jul 2023, Michael Matz via Gcc-patches wrote:
>
> > Hello,
> >
> > the ELF psABI for x86-64 doesn't have any callee-saved SSE
> > registers (there were actual reasons for that, but those don't
> > matter anym
Hi,
this patch improves profile update in loop-ch to handle situation where
duplicated header
has loop invariant test. In this case we konw that all count of the exit edge
belongs to
the duplicated loop header edge and can update probabilities accordingly.
Since we also do all the work to track
Committed, thanks Richard.
Pan
-Original Message-
From: Gcc-patches On Behalf
Of Richard Biener via Gcc-patches
Sent: Tuesday, July 11, 2023 7:01 PM
To: Ju-Zhe Zhong
Cc: gcc-patches@gcc.gnu.org; richard.sandif...@arm.com
Subject: Re: [PATCH V2] VECT: Add COND_LEN_* operations for loop
> > By now we did CCP and FRE so we likely optimized out most of constant
> > conditionals exposed by inline.
>
> So maybe we should simply delay re-propagation of the profile? I
> think cunrolli doesn't so much care about the profile - cunrolli
> is (was) about abstraction removal. Jump threadi
Richard Sandiford writes:
> Robin Dapp via Gcc-patches writes:
>> Hi,
>>
>> upcoming changes for RISC-V will have us exceed 256 modes or 8 bits. The
>> helper functions in gen* rely on the opcode as well as two modes fitting
>> into an unsigned int (a signed int even if we consider the qsort defa
Robin Dapp via Gcc-patches writes:
> Hi,
>
> upcoming changes for RISC-V will have us exceed 256 modes or 8 bits. The
> helper functions in gen* rely on the opcode as well as two modes fitting
> into an unsigned int (a signed int even if we consider the qsort default
> comparison function). This
> MASK4 0, 5, 6, 7 also works definitely
Sure :) My remark was that the tests are all(?)
evenly split and a bit more variation would have been nice.
Not that it doesn't work, I'm OK with it as is.
Regards
Robin
MASK4 0, 5, 6, 7 also works definitely.
The optimization is generic as long as the permutation index matches the
compress insn on RVV ISA SPEC.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-07-11 20:24
To: 钟居哲; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; Jeff Law
Subject: Re: [PATC
> The compress optimization pattern has included all variety.
> It's not necessary to force split (half/half), we can apply this compress
> pattern to any variety of compress pattern.
Yes, that's clear. I meant the testcases are mostly designed
like
MASK4 1, 2, 6, 7
instead of variation like
M
The compress optimization pattern has included all variety.
It's not necessary to force split (half/half), we can apply this compress
pattern to any variety of compress pattern.
You can apply this patch to see.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-07-11 20:17
To: juzhe.zh
Hi Juzhe,
looks good from my side, thanks. While going through it I
thought of some related cases that we could still handle
differently but I didn't bother to formalize them for now.
Most likely we already handle them in the shortest way
anyway. I'm going to check on that when I find some time
Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk?
-- >8 --
Here during ahead of time coercion of the variable template-id v1,
since we pass only the innermost arguments to coerce_template_parms (and
outer arguments are still dependent at this point), substitution of
Hello,
I saw the light regarding this PR after Paul posted a comment yesterday.
Regression test in progress on x86_64-pc-linux-gnu.
I plan to push in the next hours.
Mikael
-- >8 --
Release symbols in reversed order wrt the order they were allocated.
This fixes an error recovery ICE in the cas
Thanks for fixing it.
CC Richards to see whether it is appropriate.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-07-11 19:51
To: gcc-patches
CC: rdapp.gcc; jeffreyalaw; juzhe.zh...@rivai.ai
Subject: [PATCH] genopinit: Allow more than 256 modes.
Hi,
upcoming changes for RISC-V will have u
Hi,
upcoming changes for RISC-V will have us exceed 256 modes or 8 bits. The
helper functions in gen* rely on the opcode as well as two modes fitting
into an unsigned int (a signed int even if we consider the qsort default
comparison function). This patch changes the type of the index/hash
from u
On Mon, 10 Jul 2023, Tamar Christina wrote:
> > > - *type_out = STMT_VINFO_VECTYPE (stmt_info);
> > > + if (cond_cst)
> > > +{
> > > + append_pattern_def_seq (vinfo, stmt_info, pattern_stmt, vectype);
> > > + pattern_stmt
> > > + = gimple_build_cond (gimple_cond_code (cond_stmt),
>
On Mon, 10 Jul 2023, juzhe.zh...@rivai.ai wrote:
> From: Ju-Zhe Zhong
>
> Hi, Richard and Richi.
>
> This patch is adding cond_len_* operations pattern for target support loop
> control with length.
>
> These patterns will be used in these following case:
>
> 1. Integer division:
>void
>
On Fri, 7 Jul 2023, Tamar Christina wrote:
> Hi All,
>
> This patch builds on the previous patch by fixing another issue with the
> way ifcvt currently picks which branches to test.
>
> The issue with the current implementation is while it sorts for
> occurrences of the argument, it doesn't chec
On Fri, 7 Jul 2023, Tamar Christina wrote:
> Hi All,
>
> Following on from Jakub's patch in g:de0ee9d14165eebb3d31c84e98260c05c3b33acb
> these two patches finishes the work fixing the regression and improves
> codegen.
>
> As explained in that commit, ifconvert sorts PHI args in increasing numb
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