Re: [PATCH] rs6000: Don't use TFmode for 128 bits fp constant in toc [PR110011]

on 2023/6/11 10:04, David Edelsohn wrote: > On Tue, Jun 6, 2023 at 5: 20 AM Kewen. Lin wrote: > Hi, As PR110011 shows, when encoding 128 bits fp constant into toc, we adopts > REAL_VALUE_TO_TARGET_LONG_DOUBLE which is to find the first float mode with > LONG_DOUBLE_TYPE_SIZE > ZjQcmQRYFpfptBann

Re: [PATCH] rs6000: Guard __builtin_{un, }pack_vector_int128 with vsx [PR109932]

on 2023/6/12 02:39, David Edelsohn wrote: > On Tue, Jun 6, 2023 at 5: 19 AM Kewen. Lin wrote: > Hi, As PR109932 shows, builtins __builtin_{un,}pack_vector_int128 should be > guarded under vsx rather than power7, as their corresponding bif patterns > have the conditions > ZjQcmQRYFpfptBannerStar

Re: [PATCH] Make sure SCALAR_INT_MODE_P before invoke try_const_anchors

Richard Biener writes: > On Fri, 9 Jun 2023, Jiufu Guo wrote: > >> >> Hi, >> >> Richard Biener writes: >> >> > On Fri, 9 Jun 2023, Jiufu Guo wrote: >> > >> >> >> >> Hi, >> >> >> >> Richard Biener writes: >> >> >> >> > On Fri, 9 Jun 2023, Richard Sandiford wrote: >> >> > >> >> >> guojiufu

[PATCH V2] VECT: Support LEN_MASK_ LOAD/STORE to support flow control for length loop control

From: Ju-Zhe Zhong Target like ARM SVE in GCC has an elegant way to handle both loop control and flow control simultaneously: loop_control_mask = WHILE_ULT flow_control_mask = comparison control_mask = loop_control_mask & flow_control_mask; MASK_LOAD (control_mask) MASK_STORE (control_mask) How

Re: [PATCH] In the pipeline, UNRECOG INSN is not executed in advance if it starts a live range.

> On 5/29/23 04:51, Jin Ma wrote: > >Unrecog insns (such as CLOBBER, USE) does not represent real > > instructions, but in the > > process of pipeline optimization, they will wait for transmission in ready > > list like > > other insns, without considering resource conflicts and cycles. This

RE: [PATCH v1] RISC-V: Support RVV FP16 MISC vlmul ext intrinsic API

Committed, thanks Kito and Juzhe. Pan From: Kito Cheng Sent: Monday, June 12, 2023 11:33 AM To: 钟居哲 Cc: Li, Pan2 ; gcc-patches ; rdapp.gcc ; Jeff Law ; Wang, Yanzhang Subject: Re: [PATCH v1] RISC-V: Support RVV FP16 MISC vlmul ext intrinsic API Lgtm too :) 钟居哲 mailto:juzhe.zh...@rivai.ai>>

RE: [PATCH v1] RISC-V: Add test cases for RVV FP16 undefined and vlmul trunc

Committed, thanks Kito and Juzhe. Pan From: Kito Cheng Sent: Monday, June 12, 2023 11:32 AM To: 钟居哲 Cc: Li, Pan2 ; gcc-patches ; Robin Dapp ; jeffreyalaw ; Wang, Yanzhang Subject: Re: [PATCH v1] RISC-V: Add test cases for RVV FP16 undefined and vlmul trunc LGTM juzhe.zh...@rivai.ai

Re: [PATCH v1] RISC-V: Support RVV FP16 MISC vlmul ext intrinsic API

Lgtm too :) 钟居哲 於 2023年6月12日 週一 05:48 寫道： > LGTM > > > > juzhe.zh...@rivai.ai > > From: pan2.li > Date: 2023-06-11 08:33 > To: gcc-patches > CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; > kito.cheng > Subject: [PATCH v1] RISC-V: Support RVV FP16 MISC vlmul ext intrinsic API >

Re: [PATCH v1] RISC-V: Add test cases for RVV FP16 undefined and vlmul trunc

LGTM juzhe.zh...@rivai.ai 於 2023年6月12日 週一 10:58 寫道： > LGTM. > > > > juzhe.zh...@rivai.ai > > From: pan2.li > Date: 2023-06-12 10:57 > To: gcc-patches > CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; > kito.cheng > Subject: [PATCH v1] RISC-V: Add test cases for RVV FP16 undefine

[r14-1624 Regression] FAIL: std/time/year_month_day_last/1.cc (test for excess errors) on Linux/x86_64

On Linux/x86_64, 28db36e2cfca1b7106adc8d371600fa3a325c4e2 is the first bad commit commit 28db36e2cfca1b7106adc8d371600fa3a325c4e2 Author: Jason Merrill Date: Wed Jun 7 05:15:02 2023 -0400 c++: allow NRV and non-NRV returns [PR58487] caused FAIL: 25_algorithms/minmax/constrained.cc (test

RE: [PATCH v4] RISC-V: Add vector psabi checking.

I reproduce the failure too. Because it returns early in get_arg_info for v-ext mode. I'll move the checking to the beginning. > -Original Message- > From: Kito Cheng > Sent: Friday, June 9, 2023 5:52 PM > To: Wang, Yanzhang > Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...

Re: [PATCH v1] RISC-V: Add test cases for RVV FP16 undefined and vlmul trunc

LGTM. juzhe.zh...@rivai.ai From: pan2.li Date: 2023-06-12 10:57 To: gcc-patches CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng Subject: [PATCH v1] RISC-V: Add test cases for RVV FP16 undefined and vlmul trunc From: Pan Li This patch would like to add more tests

[PATCH v1] RISC-V: Add test cases for RVV FP16 undefined and vlmul trunc

From: Pan Li This patch would like to add more tests for RVV FP16 undef and vlmul trunc, aka __riscv_vundefined_f16*(); __riscv_vlmul_trunc_v_f16*_f16*(); >From the user's perspective, it is reasonable to do above operation when only ZVFHMIN is enabled. This patch would like to add new test cas

[PATCH] RISC-V: Add RVV narrow shift right lowering auto-vectorization

From: Juzhe-Zhong Optimize the following auto-vectorization codes: void foo (int16_t * __restrict a, int32_t * __restrict b, int32_t c, int n) { for (int i = 0; i < n; i++) a[i] = b[i] >> c; } Before this patch: foo: ble a3,zero,.L5 .L3: vsetvli a5,a3,e32,m1,ta,ma

Re: [PATCH V2] Optimize '(X - N * M) / N' to 'X / N - M' if valid

Hi, Thanks for your comments! Segher Boessenkool writes: > Hi! > > On Wed, Jun 07, 2023 at 04:21:11PM +0800, Jiufu Guo wrote: >> This patch tries to optimize "(X - N * M) / N" to "X / N - M". >> For C code, "/" towards zero (trunc_div), and "X - N * M" maybe >> wrap/overflow/underflow. So, it

[PATCHv2, rs6000] Add two peephole2 patterns for mr. insn

Hi, This patch adds two peephole2 patterns which help convert certain insn sequences to "mr." instruction. These insn sequences can't be combined in combine pass. Compared to last version, it adds a new mode iterator "Q" which should be used for dot instruction. With "-m32/-mpowerpc64" set, th

Re: [PATCH] Add MinGW option -mcrtdll= for choosing C RunTime DLL library

在 2023/6/12 07:08, Jonathan Yong 写道: +preprocessor is done. MinGW import library @code{msvcrt} is just a +symlink (or file copy) to the other MinGW CRT import library I suggest a change to this line: symlink to (or a copy of) another MinGW CRT import library Also, as discussed earlier, l

[PATCH, AIX] Debugging does not require a stack frame.

The rs6000 port has allocated a stack frame when debugging is enabled on AIX since the earliest versions of the port. Apparently the earliest versions of the debuggers for AIX had difficulty with stackless frames. Both AIX DBX and GDB support stackless frames on AIX, and IBM XLC, OpenXL and LLVM

Re: [PATCH] Add MinGW option -mcrtdll= for choosing C RunTime DLL library

On 5/27/23 10:14, Pali Rohár wrote: It adjust preprocess, compile and link flags, which allows to change default -lmsvcrt library by another provided by MinGW runtime. gcc/ * config/i386/mingw-w64.h (CPP_SPEC): Adjust for -mcrtdll=. (REAL_LIBGCC_SPEC): New define. * config/i386

[PATCH] VECT: Add LEN_MASK_ LOAD/STORE to support flow control for length loop control

From: Ju-Zhe Zhong Target like ARM SVE in GCC has an elegant way to handle both loop control and flow control simultaneously: loop_control_mask = WHILE_ULT flow_control_mask = comparison control_mask = loop_control_mask & flow_control_mask; MASK_LOAD (control_mask) MASK_STORE (control_mask) How

Re: [PATCH v1] RISC-V: Support RVV FP16 MISC vlmul ext intrinsic API

LGTM juzhe.zh...@rivai.ai From: pan2.li Date: 2023-06-11 08:33 To: gcc-patches CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng Subject: [PATCH v1] RISC-V: Support RVV FP16 MISC vlmul ext intrinsic API From: Pan Li This patch support the intrinsic API of FP16 ZVFH

Re: [PATCH] rs6000: Guard __builtin_{un, }pack_vector_int128 with vsx [PR109932]

On Tue, Jun 6, 2023 at 5:19 AM Kewen.Lin wrote: > Hi, > > As PR109932 shows, builtins __builtin_{un,}pack_vector_int128 > should be guarded under vsx rather than power7, as their > corresponding bif patterns have the conditions TARGET_VSX > and VECTOR_MEM_ALTIVEC_OR_VSX_P (V1TImode). This patch

[PATCH] Avoid duplicate vector initializations during RTL expansion.

This middle-end patch avoids some redundant RTL for vector initialization during RTL expansion. For the simple test case: typedef __int128 v1ti __attribute__ ((__vector_size__ (16))); __int128 key; v1ti foo() { return (v1ti){key}; } the middle-end currently expands: (set (reg:V1TI 85) (co

Re: [RFC] Add stdckdint.h header for C23

Hi Jakup, two comments which may or may not be helpful: Clang extended _Generic in a similar way: https://github.com/llvm/llvm-project/commit/12728e144994efe84715f4e5dbb8c3104e9f0b5a Although for _Generic you can achieve the same with checking for compatiblilty of pointer to the type, and I do

Re: [PATCH] Fortran: add Fortran 2018 IEEE_{MIN,MAX} functions

Hi, > Running > nohup make -j7 check-fortran > RUNTESTFLAGS="--target_board=unix/-mabi=ieeelongdouble/-mcpu=power9"& > from the gcc subdirectory yielded only a single failure: I dug more into the code and I understand why all tests are running: since db630423a97ec6690a8eb0e5c3cb186c91e3740d and

Re: libgfortran: remove support for --enable-intermodule

> OK, thanks. Committed at https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=ecc96eb5d2a0e5dd93365ef76a58d7f754273934

Re: [pushed] diagnostics: ensure that .sarif files are UTF-8 encoded [PR109098]

On Fri, Mar 24, 2023 at 9:04 PM David Malcolm via Gcc-patches wrote: > > PR analyzer/109098 notes that the SARIF spec mandates that .sarif > files are UTF-8 encoded, but -fdiagnostics-format=sarif-file naively > assumes that the source files are UTF-8 encoded when quoting source > artefacts in the

[avr,committed] Tidy code for inverted bit insertions

Applied this no-op change that tidies up the code for inverted bit insertions. Johann -- Use canonical form for reversed single-bit insertions after reload. We now split almost all insns after reload in order to add clobber of REG_CC. If insns are coming from insn combiner and there is no c

Re: [PATCH] Fortran: add Fortran 2018 IEEE_{MIN,MAX} functions

Hi FX, >> The KIND=17 is a bit of a kludge. It is not visible for >> user programs, they use KIND=16, but this is then translated >> to library calls as if it was KIND=17 if the IEEE 128-bit floats >> are selected > > Can you check what the IEEE test results are when -mabi=ieeelongdouble is ena

Re: libgfortran: remove support for --enable-intermodule

Le 10/06/2023 à 22:28, FX Coudert via Fortran a écrit : See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109373 I don’t believe it is widely used, and it was removed from everywhere else in gcc. Bootstrapped and regtested on x86_64-pc-linux-gnu. OK to commit? FX OK, thanks.