On 5/24/23 17:14, Jivan Hakobyan via Gcc-patches wrote:
`This patch tries to prevent generating unnecessary sign extension
after *w instructions like "addiw" or "divw".
The main idea of it is to add SUBREG_PROMOTED fields during expanding.
I have tested on SPEC2017 there is no regression.
On
On 6/3/23 17:03, Andrew Pinski via Gcc-patches wrote:
On Sat, Jun 3, 2023 at 3:53 PM Takayuki 'January June' Suwa via
Gcc-patches wrote:
This patch optimizes both the boolean evaluation of and the branching of
EQ/NE against INT_MIN (-2147483648), by taking advantage of the specifi-
cation t
Committed, thanks Kito.
Pan
From: Kito Cheng
Sent: Sunday, June 4, 2023 9:01 AM
To: Li, Pan2
Cc: 钟居哲 ; gcc-patches ;
kito.cheng ; Wang, Yanzhang
Subject: Re: [PATCH] RISC-V: Support RVV zvfh{min} vfloat16*_t mov and spill
LGTM
Li, Pan2 via Gcc-patches
mailto:gcc-patches@gcc.gnu.org>> 於 202
LGTM
Li, Pan2 via Gcc-patches 於 2023年6月4日 週日 08:36 寫道：
> Great! Thanks Juzhe and let’s wait kito’s approval.
>
> Pan
>
> From: 钟居哲
> Sent: Sunday, June 4, 2023 7:36 AM
> To: Li, Pan2 ; gcc-patches
> Cc: kito.cheng ; Li, Pan2 ;
> Wang, Yanzhang
> Subject: Re: [PATCH] RISC-V: Support RVV zvfh{m
Great! Thanks Juzhe and let’s wait kito’s approval.
Pan
From: 钟居哲
Sent: Sunday, June 4, 2023 7:36 AM
To: Li, Pan2 ; gcc-patches
Cc: kito.cheng ; Li, Pan2 ; Wang,
Yanzhang
Subject: Re: [PATCH] RISC-V: Support RVV zvfh{min} vfloat16*_t mov and spill
LGTM. Hope FP16 vector can be committed soon
LGTM. Hope FP16 vector can be committed soon.
Since I would like to wait for FP16 vector and then start to support FP16 FP32
FP64 autovec together.
Thanks.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-03 22:37
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang
Subject: [P
On Sat, Jun 3, 2023 at 3:53 PM Takayuki 'January June' Suwa via
Gcc-patches wrote:
>
> This patch optimizes both the boolean evaluation of and the branching of
> EQ/NE against INT_MIN (-2147483648), by taking advantage of the specifi-
> cation the ABS machine instruction on Xtensa returns INT_MIN
This patch optimizes both the boolean evaluation of and the branching of
EQ/NE against INT_MIN (-2147483648), by taking advantage of the specifi-
cation the ABS machine instruction on Xtensa returns INT_MIN iff INT_MIN,
otherwise non-negative value.
/* example */
int test0(int x) {
r
This patch is the latest revision of my patch to add support for the
STC (set carry flag), CLC (clear carry flag) and CMC (complement
carry flag) instructions to the i386 backend, incorporating Uros'
previous feedback. The significant changes are (i) the inclusion
of CMC, (ii) the use of UNSPEC f
Hi Thomas,
> Will you, Maciej, please test that this doesn't break your setting?
Umm, this was implemented for my Western Digital development environment,
which I don't have access to anymore. I'll see what I can do, but it may
be neither easy nor quick. It's been long ago and I don't have a
Hi Paul,
I want to get something approaching correct finalization to the
distros, which implies 12-branch at present. Hopefully I can do the
same with associate in a month or two's time.
OK by me then.
(I just wanted to be sure that we had this discussion :-)
Best regards
Thomas
Hi Paul,
On 6/3/23 07:48, Paul Richard Thomas via Gcc-patches wrote:
Hi Harald,
It looks good to me. Thanks to you and Steve for the fix. I suggest
that it is such and obvious one that it deserved back-porting.
alright, I'll check how far this makes sense.
Cheers,
Harald
Cheers
Paul
On F
Hi Paul, all,
On 6/3/23 15:16, Paul Richard Thomas via Gcc-patches wrote:
Hi Thomas,
I want to get something approaching correct finalization to the
distros, which implies 12-branch at present. Hopefully I can do the
same with associate in a month or two's time.
IMHO it is not only distros, b
Am 03.06.23 um 17:53 schrieb Jeff Law:
On 6/2/23 02:46, Georg-Johann Lay wrote:
There is the following bug in postreload that can be traced back
to v5 at least:
In postreload.cc::reload_cse_move2add() there is a loop over all
insns. If it encounters a SET, the next insn is analyzed if it
On Linux/x86_64,
3635e8c67e13e3da7e1e23a617dd9952218e93e0 is the first bad commit
commit 3635e8c67e13e3da7e1e23a617dd9952218e93e0
Author: Roger Sayle
Date: Thu Jun 1 15:10:09 2023 +0100
PR target/109973: CCZmode and CCCmode variants of [v]ptest on x86.
caused
FAIL: gcc.dg/torture/fp-int-
This patch fixes PR target/110083, an ICE-on-valid regression exposed by
my recent PTEST improvements (to address PR target/109973). The latent
bug (admittedly mine) is that the scalar-to-vector (STV) pass doesn't update
or delete REG_EQUAL notes attached to COMPARE instructions. As a result
the
On 5/31/23 09:13, Hans-Peter Nilsson via Gcc-patches wrote:
Tested cris-elf, bootstrapped & checked native
x86_64-pc-linux-gnu for good measure. Ok to commit?
If it wasn't for there already being an auto_inc_dec pass,
this looks like a good place to put it, considering the
framework data. (
On 6/2/23 04:42, Fei Gao wrote:
This patch fixes a cfi issue introduced by
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=60524be1e3929d83e15fceac6e2aa053c8a6fb20
Test code:
char my_getchar();
float getf();
int test_f0()
{
int s0 = my_getchar();
float f0 = getf();
int b = my_getchar()
On 6/1/23 23:56, Die Li wrote:
There are 2 small changes in this patch, but they do not affect the result.
1. Remove unnecessary md pattern for TARGET_XTHEADCONDMOV in thead.md. The
operands[4]
in "if_then_else" are always comparison operations, so the generated rtl does
not match
the patte
On 6/2/23 07:20, Lehua Ding wrote:
Hi,
This patch adds some missed ForEachMacros to the contrib/clang-format file,
which allows the clang-format tool to format gcc code correctly.
Best,
Lehua
---
contrib/clang-format | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
Thanks
On 6/2/23 02:46, Georg-Johann Lay wrote:
There is the following bug in postreload that can be traced back
to v5 at least:
In postreload.cc::reload_cse_move2add() there is a loop over all
insns. If it encounters a SET, the next insn is analyzed if it
is a single_set.
After next has been anal
On 6/2/23 09:20, Maxim Kuvyrkov via Gcc-patches wrote:
This patch adds tracking of current testsuite "tool" and "exp"
to the processing of .sum files. This avoids aliasing between
tests from different testsuites with same name+description.
E.g., this is necessary for testsuite/c-c++-common,
On Fri, 2 Jun 2023, YunQiang Su wrote:
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 4a7c963914b..c8b787b6e1e 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -91,7 +91,7 @@ m68k port Andreas Schwab
>
> m68k-motorola-sysv port Philippe De Muyter
> mcore port
From: Pan Li
This patch would like to allow the mov and spill operation for the RVV
vfloat16*_t types. The involved machine mode includes VNx1HF, VNx2HF,
VNx4HF, VNx8HF, VNx16HF, VNx32HF and VNx64HF.
Signed-off-by: Pan Li
Co-Authored by: Juzhe-Zhong
gcc/ChangeLog:
* config/riscv/risc
On 5/24/23 12:55, Jason Merrill via Gcc-patches wrote:
Middle-end folks: any thoughts about how best to make the change described in
the last paragraph below?
Library folks: any thoughts on the changes to __cxa_call_terminate?
-- 8< --
[except.handle]/7 says that when we enter std::terminat
On 3 June 2023 15:46:02 CEST, Xi Ruoyao wrote:
>Unfortunately __builtin_cpu_is performs CPU detection on runtime, not
>compile time.
Right, you were talking about configure, sorry.
On Sat, 2023-06-03 at 14:53 +0200, Bernhard Reutner-Fischer wrote:
> On 3 June 2023 13:25:32 CEST, Xi Ruoyao via Gcc-patches
> wrote:
>
> > There seems no good way to check if the CPU is Intel or AMD from
> > the built-in macros (maybe we can check every known model like
> > __skylake,
> > __bdve
Hi Thomas,
I want to get something approaching correct finalization to the
distros, which implies 12-branch at present. Hopefully I can do the
same with associate in a month or two's time.
I am dithering about changing the F2003/08 part of finalization since
the default is 2018 compliance. That s
On 3 June 2023 13:25:32 CEST, Xi Ruoyao via Gcc-patches
wrote:
>There seems no good way to check if the CPU is Intel or AMD from
>the built-in macros (maybe we can check every known model like __skylake,
>__bdver2, ..., but it will be very error-prune and require an update
>whenever we add the s
Hi Richard,
> On 3 Jun 2023, at 12:20, Richard Biener wrote:
>
>> Am 02.06.2023 um 21:12 schrieb Iain Sandoe via Gcc-patches
>> :
>>
>> --- 8< ---
>>
>> This bug was essentially that darwin_rs6000_special_round_type_align()
>> was ignoring externally-imposed capping of field alignment.
>>
>
We used to skip ifunc check when CX16 is available. But now we use
CX16+AVX+Intel/AMD for the "perfect" 16b load implementation, so CX16
alone is not a sufficient reason not to use ifunc (see PR104688).
This causes a subtle and annoying issue: when GCC is built with a
higher -march= setting in CF
> Am 02.06.2023 um 21:12 schrieb Iain Sandoe via Gcc-patches
> :
>
> @David: I am not sure what sets the ABI on AIX (for Darwin, it is effectively
> "whatever the system compiler [Apple gcc-4] does") but from an inspection of
> the code, it seems that (if the platform should honour #pragma pa
This patch optimizes the boolean evaluation of EQ/NE against zero
by adding two insn_and_split patterns similar to SImode conditional
store:
"eq_zero":
op0 = (op1 == 0) ? 1 : 0;
op0 = clz(op1) >> 5; /* optimized (requires TARGET_NSA) */
"movsicc_ne0_reg_0":
op0 = (op1 !=
On Sat, Jun 03, 2023 at 07:50:19AM +0200, Thomas Koenig via Fortran wrote:
> Hi Paul,
>
> > I propose to backport
> > r13-6747-gd7caf313525a46f200d7f5db1ba893f853774aee to 12-branch very
> > soon.
>
> Is this something that we usually do?
>
> While finalization was basically broken before, some
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