Some tests hard-coded specific allocations for temporary registers,
whereas the RA should be free to pick anything that doesn't force
unnecessary moves or spills.
gcc/testsuite/
* gcc.target/aarch64/asimd-mul-to-shl-sub.c: Allow any register
allocation for temporary results, rather
There were many tests that used [0-9] to match an FP or vector register,
but that should allow any of 0-31 instead.
asm-x-constraint-1.c required s0-s7, but that's the range for "y"
rather than "x". "x" allows s0-s15.
sve/pcs/return_9.c required z2-z7 (the initial set of available
call-clobbered
Some ACLE intrinsics map to instructions that tie the output
operand to an input operand. If all the operands are allocated
to different registers, and if MOVPRFX can't be used, we will need
a move either before the instruction or after it. Many tests only
matched the "before" case; this patch ma
Most governing predicate operands require p0-p7, but some
instructions also allow p8-p15. Non-gp uses of predicates
often also allow all of p0-p15.
This patch fixes up cases where we required p0-p7 unnecessarily.
In some cases we match the definition (typically a comparison,
PFALSE or PTRUE), som
Some of the SVE ACLE asm tests tried to be agnostic about the
instruction order, but only one of the alternatives was exercised
in practice. This patch fixes latent typos in the other versions.
gcc/testsuite/
* gcc.target/aarch64/sve2/acle/asm/aesd_u8.c: Fix expected register
allo
Some of the svdup tests expand to a SEL between two constant vectors.
This patch allows the constants to be formed in either order.
gcc/testsuite/
* gcc.target/aarch64/sve/acle/asm/dup_s16.c: When using SEL to select
between two constant vectors, allow the constant moves to appear
I have a patch that seems to improve register allocation for SIMD
lane operations, and for similar instructions that require a reduced
register range. However, it showed that a lot of asm tests are
sensitive to the current register allocation. This patch series
tries to correct the affected cases
Bootstrapped and regression tested on x86-64.
Fix ICE related to implicit access attributes for VLA arguments [PR105660]
When constructing the specifier string when merging an access attribute
that encodes information about VLA arguments, the string was constructed
in ran
On Tue, May 9, 2023 at 12:27 AM Eugene Rozenfeld via Gcc-patches
wrote:
>
> Todo from early_inliner needs to be propagated so that
> cleanup_tree_cfg () is called if necessary.
>
> This bug was causing an assert in get_loop_body during
> ipa-sra in autoprofiledbootstrap build since loops weren't
>
Update the memory allocated bytes for both the all 12-bits patch and code
8-bits + mode 16-bits.
Bytes allocated with O2:
---
Benchmark
This patch try to introduce the rwlock and split the read/write to
unit_root tree and unit_cache with rwlock instead of the mutex to
increase CPU efficiency. In the get_gfc_unit function, the percentage
to step into the insert_unit function is around 30%, in most instances,
we can get the unit in t
On 1/1/1970 8:00 AM, Bernhard Reutner-Fischer wrote:
On Mon, 8 May 2023 17:44:43 +0800
Lipeng Zhu wrote:
This patch try to introduce the rwlock and split the read/write to
unit_root tree and unit_cache with rwlock instead of the mutex to
increase CPU efficiency. In the get_gfc_unit functio
From: Juzhe-Zhong
This patch is fix dead loop in vsetvl intrinsic avl checking.
vsetvli->get_def () has vsetvli->get_def () has vsetvli.
Then it will keep looping in the vsetvli avl checking which is a dead loop.
PR target/109773
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.
From: Juzhe-Zhong
Rebase to trunk and send V3 patch for:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/617821.html
This patch is fixing: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109743.
This issue happens is because we are currently very conservative in
optimization of user vsetvli.
Ping.
This patch rebases cleanly as of right now. No new changes to review.
Have a lovely day!
--
Arsen Arsenović
signature.asc
Description: PGP signature
Todo from early_inliner needs to be propagated so that
cleanup_tree_cfg () is called if necessary.
This bug was causing an assert in get_loop_body during
ipa-sra in autoprofiledbootstrap build since loops weren't
fixed up and one of the loops had num_nodes set to 0.
Tested on x86_64-pc-linux-gnu.
On 5/8/23 08:44, Takayuki 'January June' Suwa via Gcc-patches wrote:
On 2023/05/08 22:43, Richard Biener wrote:
[snip]
-mlra
If they were in any released compiler options should be kept
(doing nothing) for backward compatibility. Use for example
mlra
Target WarnRemoved
Removed in GCC 14.
On 5/8/23 02:54, Pan Li via Gcc-patches wrote:
From: Pan Li
The VMSET simplification RVV integer comparision has merged already.
This patch would like to update the comments for the cases that the
define_split will act on.
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/vecto
On 5/8/23 00:43, Richard Biener wrote:
On Sat, May 6, 2023 at 8:46 PM Jeff Law via Gcc-patches
wrote:
On 5/6/23 06:57, Roger Sayle wrote:
Following up on posts/reviews by Segher and Uros, there's some question
over why the middle-end's lower subreg pass emits a clobber (of a
multi-word
On 5/8/23 08:12, Raphael Moreira Zinsly wrote:
Changes since v1:
- Remove subreg from operand 1.
-- >8 --
We were not able to match the CTZ sign extend pattern on RISC-V
because it gets optimized to zero extend and/or to ANDI patterns.
For the ANDI case, combine scrambles the RTL and
On 5/8/23 08:11, Raphael Moreira Zinsly wrote:
Changes since v1:
- Removed name clash change.
- Fix new pattern indentation.
-- >8 --
When (a & (1 << bit_no)) is tested inside an IF we can use a bit extract.
gcc/ChangeLog:
* config/riscv/bitmanip.m
Hi!
Ping: OK to push to newlib main branch the attached
"For GCC, newlib combined tree, newlib build-tree testing, use standard search
paths"?
Or, has anybody got adverse comments/insight into this?
Grüße
Thomas
On 2023-04-14T22:03:28+0200, I wrote:
> Hi!
>
> OK to push to newlib main branch
Steve,
On 5/8/23 02:13, Steve Kargl via Gcc-patches wrote:
Harald,
Thanks for keeping us honest. I didn't check what other
separators might cause a problem.
After 2 decades of working on gfortran, I've come to conclusion
that -std=f2018 should be the default. When f2023 is ratified,
the defau
> Am 08.05.2023 um 20:14 schrieb Alexander Monakov via Gcc-patches
> :
>
> I'm trying to study match.pd/genmatch with the eventual goal of
> improving match-and-simplify code generation. Here's some trivial
> cleanups for the recent refactoring in the meantime.
>
> Alexander Monakov (3):
>
Eliminate boolean parameters of emit_func. The first ('open') just
prints 'extern' to generated header, which is unnecessary. Introduce a
separate function to use when finishing a declaration in place of the
second ('close').
Rename emit_func to 'fp_decl' (matching 'fprintf' in length) to unbreak
get_out_file did not follow the coding conventions (mixing three-space
and two-space indentation, missing linebreak before function name).
Take that as an excuse to reimplement it in a more terse manner and
rename as 'choose_output', which is hopefully more descriptive.
gcc/ChangeLog:
*
Display usage more consistently and get rid of camelCase.
gcc/ChangeLog:
* genmatch.cc (showUsage): Reimplement as ...
(usage): ...this. Adjust all uses.
(main): Print usage when no arguments. Add missing 'return 1'.
---
gcc/genmatch.cc | 21 ++---
1 fil
I'm trying to study match.pd/genmatch with the eventual goal of
improving match-and-simplify code generation. Here's some trivial
cleanups for the recent refactoring in the meantime.
Alexander Monakov (3):
genmatch: clean up emit_func
genmatch: clean up showUsage
genmatch: fixup get_out_file
I had missed when converting this
testcase to Gimple that there was a define
for int/unsigned type specifically to get
an INT32 type. This means when using a
literal integer constant you need to use the
`_Literal (type)` to form the types correctly on the
constants.
This fixes the issue and has be
On Mon, 8 May 2023 12:42:33 +0200
Thomas Schwinge wrote:
> >> +if [info exists ::env(GCC_RUNTEST_PARALLELIZE_DIR)] {
> >> +load_file ../libgomp-test-support.exp
> >> +} else {
> >> +load_file libgomp-test-support.exp
> >> +}
> >
> > Do we have to re-read those? Other
On Mon, May 08, 2023 at 06:23:54AM +, Richard Biener wrote:
> I wonder if we should defer some of the choices to a langhook
> like make the tree_invariant_p_1 a langhook invocation with the
> default to call tree_invariant_p_1. After lowering we can reset
> the langhook to the default.
We cer
On 2023/05/08 22:43, Richard Biener wrote:
[snip]
>> -mlra
>
> If they were in any released compiler options should be kept
> (doing nothing) for backward compatibility. Use for example
>
> mlra
> Target WarnRemoved
> Removed in GCC 14. This switch has no effect.
>
> or
>
> mlra
> Target Igno
Ok. Address comment and V2 patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/617821.html
Thanks.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-05-08 17:53
To: juzhe.zh...@rivai.ai
CC: gcc-patches
Subject: Re: [PATCH] RISC-V: Optimize vsetvli of LCM INSERTED edge for user
vsetvli [
From: Juzhe-Zhong
This patch is fixing: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109743.
This issue happens is because we are currently very conservative in
optimization of user vsetvli.
Consider this following case:
bb 1:
vsetvli a5,a4... (demand AVL = a4).
bb 2:
RVV insn use a5 (dem
stdint.h will require having corresponding multi-lib existing, so using
stdint-gcc.h instead, also added a riscv_vector.h wrapper to
gcc.target/riscv/rvv/autovec/.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.h: Change
stdint.h to stdint-gcc.h.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (pass_vsetvl::get_vector_info):
New.
(pass_vsetvl::get_block_info): New.
(pass_vsetvl::update_vector_info): New.
(pass_vsetvl::simple_vsetvl): Use get_vector_info.
(pass_vsetvl::compute_local_backward_inf
Today's build of xstormy16-elf failed due to a branch to an out of range
target. Manual inspection of the assembly code for the affected
function (divdi3) showed that the zero-extension patterns were claiming
a length of 2, but clearly assembled into 4 bytes.
This patch adds an explicit len
Changes since v1:
- Remove subreg from operand 1.
-- >8 --
We were not able to match the CTZ sign extend pattern on RISC-V
because it gets optimized to zero extend and/or to ANDI patterns.
For the ANDI case, combine scrambles the RTL and generates the
extension by using subregs.
Changes since v1:
- Removed name clash change.
- Fix new pattern indentation.
-- >8 --
When (a & (1 << bit_no)) is tested inside an IF we can use a bit extract.
gcc/ChangeLog:
* config/riscv/bitmanip.md
(branch_bext): New split pattern.
Hi!
On 2023-04-14T13:49:20+0100, Gaius Mulley via Gcc-patches
wrote:
> Thomas Schwinge writes:
>> Separately, given that plain 'autoreconf' works, why have 'autogen.sh' at
>> all?
>
> If autoreconf does the same as autogen.sh then yes this can be removed
Pushed to master branch commit bd6dbdb1
On Mon, May 8, 2023 at 3:39 PM Takayuki 'January June' Suwa via
Gcc-patches wrote:
>
> gcc/ChangeLog:
>
> * config/xtensa/constraints.md (R, T, U):
> Change define_constraint to define_memory_constraint.
> * config/xtensa/xtensa.cc
> (xtensa_lra_p, TARGET_LRA_P): Re
gcc/ChangeLog:
* config/xtensa/constraints.md (R, T, U):
Change define_constraint to define_memory_constraint.
* config/xtensa/xtensa.cc
(xtensa_lra_p, TARGET_LRA_P): Remove.
(xtensa_emit_move_sequence): Remove "if (reload_in_progress)"
clause as it
Hello,
Ping https://gcc.gnu.org/pipermail/gcc-patches/2022-November/606450.html
Thanks,
Lorenzo Salvadore
> From f8e2c2ee89a7d8741bb65163d1f1c20edcd546ac Mon Sep 17 00:00:00 2001
> From: Lorenzo Salvadore develo...@lorenzosalvadore.it
>
> Date: Wed, 16 Nov 2022 11:27:38 +0100
> Subject: [PATCH]
On 5/5/23 12:59, Richard Sandiford wrote:
This patch follows on from g:9f635bd13fe9e85872e441b6f3618947f989909a
("the previous patch"). To start by quoting that:
If an insn requires two operands to be tied, and the input operand dies
in the insn, IRA acts as though there were a copy from the
Status
==
The gcc-12 branch is again open for regression and documentation fixes.
Quality Data
Priority # Change from last report
--- ---
P10
P2 501 - 1
P3 54 + 5
P4
On Fri, Feb 3, 2023 at 8:34 AM Richard Biener
wrote:
>
> On Thu, Feb 2, 2023 at 6:39 PM Michael Meissner via Gcc-patches
> wrote:
> >
> > The new __dmr type that is being added as a possible future PowerPC
> > instruction
>
> "is being added" means this feature is already in GCC 13?
>
> > set bu
Just pinging in case this fix has fallen through the cracks.
https://gcc.gnu.org/pipermail/gcc-patches/2023-March/614811.html
On Wed, Mar 29, 2023 at 1:33 PM Nathaniel Shead
wrote:
>
> This is an update of the patch series at
> https://gcc.gnu.org/pipermail/gcc-patches/2023-March/614759.html
>
>
Hi Bernhard!
Thanks for your comments.
On 2023-05-06T16:15:45+0200, Bernhard Reutner-Fischer via Gcc-patches
wrote:
> On Fri, 5 May 2023 10:55:41 +0200
> Thomas Schwinge wrote:
>
>> >> > with a minimal change
>> >> > to libgomp.exp so the generated libgomp-test-support.exp file is found
>> >>
On Mon, 8 May 2023 17:44:43 +0800
Lipeng Zhu wrote:
> This patch try to introduce the rwlock and split the read/write to
> unit_root tree and unit_cache with rwlock instead of the mutex to
> increase CPU efficiency. In the get_gfc_unit function, the percentage
> to step into the insert_unit func
On Mon, 8 May 2023 17:31:27 +0800
"Zhu, Lipeng" wrote:
> > BTW, did you look at the RELEASE semantics, respectively the note that one
> > day (and now is that very
> > day), we might improve on the release semantics? Can of course be
> > incremental AFAIC
> >
> Not quite understand your ques
I am wondering if it is possible to do this on
local_eliminate_vsetvl_insn? I feel this is sort of local elimination,
so putting them together would be better than handling that in many
different places.
On Mon, May 8, 2023 at 9:35 AM juzhe.zh...@rivai.ai
wrote:
>
> Gentle ping this patch.
>
> Is
This patch try to introduce the rwlock and split the read/write to
unit_root tree and unit_cache with rwlock instead of the mutex to
increase CPU efficiency. In the get_gfc_unit function, the percentage
to step into the insert_unit function is around 30%, in most instances,
we can get the unit in t
On 1/1/1970 8:00 AM, Bernhard Reutner-Fischer wrote:
Hi!
[please do not top-post]
Sure, thanks for the reminder.
On Thu, 20 Apr 2023 21:13:08 +0800
"Zhu, Lipeng" wrote:
Hi Bernhard,
Thanks for your questions and suggestions.
The rwlock could allow multiple threads to have concurrent r
-msave-restore is a different story; it's only enabled when the user
requests, but `-march` describes the capability of the target
architecture, not specify the preference of performance or size, which
should be determined by -O1~-O3/-Ofast or -Os/-Oz.
On Mon, May 8, 2023 at 4:54 PM Fei Gao wrote
From: Pan Li
The VMSET simplification RVV integer comparision has merged already.
This patch would like to update the comments for the cases that the
define_split will act on.
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/vector.md: Add comments for simplifying to vmset.
Signed
On 2023-05-08 16:05 Kito Cheng wrote:
>
>> > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
>> > index 45a63cab9c9..629e5e45cac 100644
>> > --- a/gcc/config/riscv/riscv.cc
>> > +++ b/gcc/config/riscv/riscv.cc
>> > @@ -5729,7 +5729,8 @@ riscv_get_separate_components (void)
>> >
Hi, Kewen.
I have tried to implement "decrement IV" feature and incorporate into
"vect_set_loop_controls_directly".
Since the implementation is quite different from
vect_set_loop_controls_directly, it will make vect_set_loop_controls_directly
very complicated sometimes it makes me very hard to
After the bits patch like below.
rtx_def code 16 => 8 bits.
rtx_def mode 8 => 16 bits.
tree_base code unchanged.
The structure layout of both the rtx_def and tree_base will be something
similar as below. As I understand, the lower 8-bits of tree_base will be
inspected when 'dv' is a tree for th
> > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> > index 45a63cab9c9..629e5e45cac 100644
> > --- a/gcc/config/riscv/riscv.cc
> > +++ b/gcc/config/riscv/riscv.cc
> > @@ -5729,7 +5729,8 @@ riscv_get_separate_components (void)
> >
> >if (riscv_use_save_libcall (&cfun->machi
Hi Juzhe,
> Hi, Kewen.
>
>>> Sorry for chiming in, I had some concern here.
>>> We already have some handlings for partial vector in length in
>>> vect_set_loop_controls_directly
>>>(actually it deals with both mask and length), the proposed
>>>vect_set_loop_controls_by_select_vl
>>>for select_
On Sat, May 6, 2023 at 1:41 AM Fei Gao wrote:
>
> zcmp aims to reduce code size, while shrink-wrap-separate prefers
> speed to code size. So disable shrink-wrap-separate if zcmp
> enabled, just like what save-restore has done.
>
> author: Zhangjin Liao liaozhang...@eswincomputing.com
>
> gcc/Chang
On 2023-05-08 10:41 Kito Cheng wrote:
>
>shrink-wraping already gated by Os so I think we don't need add more
>gate here, unless we are trying to claim force optimize for size if
>zcmp is present.
>
hi Kito
Zcmp is added here just like save-restore.
Either we add them both, or delete.
BR,
F
On Mon, 8 May 2023, Li, Pan2 wrote:
> return !dv || (int) GET_CODE ((rtx) dv) != (int) VALUE; } is able to fix
> this ICE after mode bits change.
Can you check which bits this will inspect when 'dv' is a tree after your
patch? VALUE is 1 and would map to IDENTIFIER_NODE on the tree side
when th
On Mon, May 8, 2023 at 9:09 AM Andrew Pinski wrote:
>
> On Sun, May 7, 2023 at 11:53 PM Richard Biener via Gcc-patches
> wrote:
> >
> > On Mon, May 8, 2023 at 8:51 AM Richard Biener
> > wrote:
> > >
> > > On Sun, May 7, 2023 at 7:05 AM Andrew Pinski via Gcc-patches
> > > wrote:
> > > >
> > > >
On Sun, May 7, 2023 at 11:53 PM Richard Biener via Gcc-patches
wrote:
>
> On Mon, May 8, 2023 at 8:51 AM Richard Biener
> wrote:
> >
> > On Sun, May 7, 2023 at 7:05 AM Andrew Pinski via Gcc-patches
> > wrote:
> > >
> > > So the function factor_out_conditional_conversion already supports
> > > di
Committed to trunk
On Thu, May 4, 2023 at 4:03 PM Kito Cheng via Gcc-patches
wrote:
>
> RISC-V Linux encodes the ABI into the path, so in theory, we can only use that
> to select multi-lib paths, and no way to use different multi-lib paths between
> `rv32i/ilp32` and `rv32ima/ilp32`, we'll mappin
Committed to trunk, thanks!
On Mon, May 8, 2023 at 11:42 AM wrote:
>
> From: Juzhe-Zhong
>
> 1. Add movmisalign pattern for TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
>targethook, current RISC-V has supported this target hook, we can't make
>it supported without movmisalign pattern.
>
return !dv || (int) GET_CODE ((rtx) dv) != (int) VALUE; } is able to fix this
ICE after mode bits change. I will re-trigger the memory allocate bytes test
with below changes for X86.
rtx_def code 16 => 8 bits.
rtx_def mode 8 => 16 bits.
tree_base code unchanged.
Pan
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