[PATCH, V2] PR target/70243: Do not generate vmaddfp and vnmsubfp

This is version 2 of the patch. The first version was posted on April 6th. In this version, I eliminated the changes to Altivec.md that added checks to altivec_fmav4sf4 and altivec_vnmsubfp. After writing the code, I remembered that VECTOR_UNIT_ALTIVEC_P that is used by those insns will not be t

Re: PR target/70243: Do not generate fmaddfp and fnmsubfp

On Thu, Apr 06, 2023 at 03:37:59PM -0500, Segher Boessenkool wrote: > Hi! > > On Thu, Apr 06, 2023 at 11:12:11AM -0400, Michael Meissner wrote: > > The Altivec instructions fmaddfp and fnmsubfp have different rounding > > behaviors > > Those are not existing instructions. You mean "vmaddfp" etc

[PATCH] PR target/109402: v850 (not v850e) variant of __muldi3() moves sp in reversed direction [PR109402]

Where I talk about is: /libgcc/config/v850/lib1funcs.S L2214, L2259 - in a commit 8b1204d7. There are stack-pointer operations. I think these operations: shrink before, grow after --- may reversed way. There is one more consideration; this version of __muldi3() does not use local storage in stack

Re: [PATCH] [testsuite] [ppc] expect vectorization in gen-vect-11c.c

On Apr 6, 2023, "Kewen.Lin" wrote: > on 2023/4/6 13:20, Alexandre Oliva wrote: >> I confirm I observe the problem with gcc-12 targeting ppc64-vx7r2, >> containing the backported patch, and that the loop is vectorized, >> failing the test. I take that back. My notes indicate I looked into this

Re: [PATCH] [testsuite] [ppc] skip ppc-fortran if fortran is disabled

Hello, Kewen, On Apr 6, 2023, "Kewen.Lin" wrote: > on 2023/4/6 14:19, Alexandre Oliva wrote: >> Skip ppc-fortran.exp if a trivial fortran program cannot be compiled. > IIUC, without this patch and under the configuration disabling fortran, > all the cases in this sub-testsuite would fail? Th

[PATCH V2] RISC-V: Modified validation information for contracts-tmpl-spec2.C

From: yulong This patch fixes the problem of the contracts-tmpl-spec2.c running failure. When run the dejagnu test, I find that the output is inconsistent with that verified in the testcase. So I try to modify it, and then it can be passed. gcc/testsuite/ChangeLog: * g++.dg/contracts/c

[PATCH V4] RISC-V: Fix a redefinition bug for the fd-4.c

From: yulong This patch fix a redefinition bug. There are have a definition about mode_t in the fd-4.c, but it duplicates the definition in types.h that be included by stdio.h. gcc/testsuite/ChangeLog: * gcc.dg/analyzer/fd-4.c: delete the definition of mode_t. --- gcc/testsuite/gcc.d

RE: [PATCH] VECT: Add WHILE_LEN pattern for decrement IV support for auto-vectorization

The bootstrap in X86 passed with this patch applied, target commit id a8c8351cf4fedb842988eed4f73304019c361e86 (13.0.1 20230407). Pan -Original Message- From: Gcc-patches On Behalf Of juzhe.zh...@rivai.ai Sent: Friday, April 7, 2023 9:48 AM To: gcc-patches@gcc.gnu.org Cc: richard.sandi

Re: [PATCH] [PR99708] [rs6000] don't expect __ibm128 with 64-bit long double

On Apr 6, 2023, "Kewen.Lin" wrote: > The reason why personally I preferred to fix it with xfail is that: Got it. I'm convinced, and I agree. I tried an xfail in the initial dg-do, but that is no good for a compile error, so I went for a dg-bogus xfail. I hope that will still have the intende

[PATCH] VECT: Add WHILE_LEN pattern for decrement IV support for auto-vectorization

From: Juzhe-Zhong This patch is to add WHILE_LEN pattern. It's inspired by RVV ISA simple "vvaddint32.s" example: https://github.com/riscv/riscv-v-spec/blob/master/example/vvaddint32.s More details are in "vect_set_loop_controls_by_while_len" implementation and comments. Consider such following

Re: Re: [PATCH 2/3] RISC-V: Enable basic RVV auto-vectorization and support WHILE_LEN/LEN_LOAD/LEN_STORE pattern

Address all comments, and fix all of them in these splitted patches: These 5 patches only including RISC-V port changes: https://patchwork.sourceware.org/project/gcc/patch/20230407011143.46004-1-juzhe.zh...@rivai.ai/ https://patchwork.sourceware.org/project/gcc/patch/20230407012129.63142-1-juzhe

[PATCH] RISC-V: Add testcases for RVV auto-vectorization

From: Juzhe-Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/rvv.exp: Add auto-vectorization testing. * gcc.target/riscv/rvv/vsetvl/vsetvl-17.c: Adapt testcase. * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.c: New test. * gcc.target/riscv/rvv/autov

[PATCH] RISC-V: Add local user vsetvl instruction elimination

From: Juzhe-Zhong This patch is to enhance optimization for auto-vectorization. Before this patch: Loop: vsetvl a5,a2... vsetvl zero,a5... vle After this patch: Loop: vsetvl a5,a2 vle gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (local_eliminate_vsetvl_insn): New function.

[PATCH] RISC-V: Enable basic RVV auto-vectorization support

From: Juzhe-Zhong Enable basic auto-vectorization support of WHILE_LEN/LEN_LOAD/LEN_STORE. gcc/ChangeLog: * config/riscv/riscv-protos.h (preferred_simd_mode): New function. (expand_while_len): Ditto. * config/riscv/riscv-v.cc (autovec_use_vlmax_p): Ditto. (preferr

[PATCH] RISC-V: Add RVV auto-vectorization compile option

From: Juzhe-Zhong The next patch to enable basic RVV auto-vectorization of VLA auto-vectorization (RVV_SCALABLE) and fixed-length VLS auto-vectorization (RVV_FIXED_VLMAX). We will support RVV_FIXED_VLMIN in the future. gcc/ChangeLog: * config/riscv/riscv-opts.h (enum riscv_autovec_pre

[PATCH] RISC-V: Fix incorrect condition of EEW = 64 mode

From: Juzhe-Zhong This patch should be merged before this patch: https://gcc.gnu.org/pipermail/gcc-patches/2023-March/614935.html According to RVV ISA, the EEW = 64 is enable only when -march=*zve64* Current condition is incorrect, since -march=*zve32*_zvl64b will enable EEW = 64 which is incor

Re: [PATCHv4] [AARCH64] Fix PR target/103100 -mstrict-align and memset on not aligned buffers

On Tue, Apr 4, 2023 at 10:48 AM Richard Sandiford via Gcc-patches wrote: > > Andrew Pinski via Gcc-patches writes: > > The problem here is that aarch64_expand_setmem does not change the alignment > > for strict alignment case. > > This is version 4 of the fix, major changes from the last version

Re: 'g++.dg/modules/modules.exp': don't leak local 'unsupported' proc [PR108899]

On Apr 6, 2023, Thomas Schwinge wrote: > Eh, given your "Ooh, nice, I didn't know [...]" comment in > : Oh my, you're right, I apologize, I misremembered. When I wrote "before I saw your patch" yesterday, I meant the formal, al

Re: PR target/70243: Do not generate fmaddfp and fnmsubfp

Hi! On Thu, Apr 06, 2023 at 11:12:11AM -0400, Michael Meissner wrote: > The Altivec instructions fmaddfp and fnmsubfp have different rounding > behaviors Those are not existing instructions. You mean "vmaddfp" etc. > than the VSX xvmaddsp and xvnmsubsp instructions. In particular, generating

Re: 'g++.dg/modules/modules.exp': don't leak local 'unsupported' proc [PR108899]

Hi Alexandre! On 2023-04-05T23:38:43-0300, Alexandre Oliva via Gcc-patches wrote: > On Apr 5, 2023, Thomas Schwinge wrote: >> With... > >> Co-authored-by: Thomas Schwinge > >> ... added, I suppose. > > I wrote the patch based on your report, before even seeing your patch Eh, given your "

[patch] 'omp scan' struct block seq update for OpenMP 5.x

That's scheduled for GCC 13 and was found by Sandra and Frederik, 'omp scan' has undergone quite some transformation: In 5.0 it was added with a preceding and succeeding structured block. In 5.1, 'structured block' was replaced by 'structured-block-sequence' defined as "...a sequence of two or

[committed][testsuite] arm: remove unused variables from test

Hi all, This is just a minor issue I found with a previous test of mine that caused it to fail in C++ mode due to these unused const variables being uninitialised. I forgot to remove these after removing some test cases that did use them. I removed the test cases, because I came to the conclusion

Ping: [PATCH v2][RFC] vect: Verify that GET_MODE_NUNITS is greater than one for vect_grouped_store_supported

May I ping this patch? https://gcc.gnu.org/pipermail/gcc-patches/2023-March/614700.html Any suggestions and comments would be appreciated. Thank you! Sincerely, Kevin Lee

Re: [PATCH 2/3] RISC-V: Enable basic RVV auto-vectorization and support WHILE_LEN/LEN_LOAD/LEN_STORE pattern

Is changes for riscv-vsetvl.cc necessary for autovec? or is it additional optimization for the autovec use case? I would suggest splitting that if it's later one. And plz split out fixed-vlmax part into separated patch, that would be easier to review. On Thu, Apr 6, 2023 at 10:44 PM wrote: > > F

Re: [PATCH] RISC-V: Add RVV auto-vectorization testcase

You included asm output by accidently :P On Thu, Apr 6, 2023 at 10:45 PM wrote: > > From: Juzhe-Zhong > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/rvv.exp: Add testing for RVV > auto-vectorization. > * gcc.target/riscv/rvv/vsetvl/vsetvl-17.c: Adapt testcase. >

[committed] arm: mve: fix auto-inc generation [PR107674]

My change r13-416-g485a0ae0982abe caused the compiler to stop generating auto-inc operations on mve loads and stores. The fix is to check whether there is a replacement register available when in strict mode and the register is still a pseudo. gcc: PR target/107674 * config/arm/

PR target/70243: Do not generate fmaddfp and fnmsubfp

The Altivec instructions fmaddfp and fnmsubfp have different rounding behaviors than the VSX xvmaddsp and xvnmsubsp instructions. In particular, generating these instructions seems to break Eigen. GCC has generated the Altivec fmaddfp and fnmsubfp instructions on VSX systems as an alternative to

Re: [PATCH] combine: Fix simplify_comparison AND handling for WORD_REGISTER_OPERATIONS targets [PR109040]

On 4/6/23 04:31, Jakub Jelinek wrote: If we want to fix it in the combiner, I think the fix would be following. The optimization is about (and:SI (subreg:SI (reg:HI xxx) 0) (const_int 0x84c)) and IMHO we can only optimize it into (subreg:SI (and:HI (reg:HI xxx) (const_int 0x84c)) 0) if we kn

Re: [PATCH] RISC-V: Fix regression of -fzero-call-used-regs=all

> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc > index 2e91d019f6c..90c69b52bb4 100644 > --- a/gcc/config/riscv/riscv-v.cc > +++ b/gcc/config/riscv/riscv-v.cc > @@ -43,6 +43,7 @@ > #include "optabs.h" > #include "tm-constrs.h" > #include "rtx-vector-builder.h" > +#include

Re: [PATCH] dse: Handle SUBREGs of word REGs differently for WORD_REGISTER_OPERATIONS targets [PR109040]

On 4/6/23 04:15, Eric Botcazou wrote: Originally I didn't really see this as an operation. But the more and more I ponder it feels like it's an operation and thus should be subject to WORD_REGISTER_OPERATIONS. While it's not really binding on RTL semantics, if we look at how some architectur

Re: [PATCH] dse: Handle SUBREGs of word REGs differently for WORD_REGISTER_OPERATIONS targets [PR109040]

On 4/6/23 03:37, Li, Pan2 wrote: Yes, RISC-V riscv.h defined the WORD_REGISTER_OPERATIONS to be 1, while aarch64.h defined it as 0, with below comments. No idea this can fit RISC-V or not. I don't see any fundamental reason why it won't work. Most of the expansion code already has code to

Re: [PATCH] dse: Handle SUBREGs of word REGs differently for WORD_REGISTER_OPERATIONS targets [PR109040]

On 4/6/23 03:31, Richard Sandiford wrote: Jeff Law writes: On 4/5/23 10:48, Jakub Jelinek wrote: On Wed, Apr 05, 2023 at 10:17:59AM -0600, Jeff Law wrote: It is true that an instruction like (insn 8 7 9 2 (set (reg:HI 141) (subreg:HI (reg:SI 142) 0)) "aauu.c":6:18 181 {*movhi_in

[PATCH] RISC-V: Add RVV auto-vectorization testcase

From: Juzhe-Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/rvv.exp: Add testing for RVV auto-vectorization. * gcc.target/riscv/rvv/vsetvl/vsetvl-17.c: Adapt testcase. * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.c: New test. * gcc.target/riscv/r

[PATCH 2/3] RISC-V: Enable basic RVV auto-vectorization and support WHILE_LEN/LEN_LOAD/LEN_STORE pattern

From: Juzhe-Zhong gcc/ChangeLog: * config/riscv/riscv-opts.h (enum riscv_autovec_preference_enum): Add compile option for RVV auto-vectorization. (enum riscv_autovec_lmul_enum): Ditto. * config/riscv/riscv-protos.h (get_vector_mode): Remove unused global function.

[PATCH 0/3] RISC-V:Enable basic auto-vectorization for RVV

From: Juzhe-Zhong PATCH 1: Add WHILE_LEN pattern in Loop Vectorizer to support decrement IV for RVV. PATCH 2: Enable basic auto-vectorization for RVV in RISC-V port. PATCH 3: Add testcases for basic RVV auto-vectorization of WHILE_LEN pattern includeing single rgroup test and multiple

[PATCH 1/3] VECT: Add WHILE_LEN pattern to support decrement IV manipulation for loop vectorizer.

From: Juzhe-Zhong This patch is to add WHILE_LEN pattern. It's inspired by RVV ISA simple "vvaddint32.s" example: https://github.com/riscv/riscv-v-spec/blob/master/example/vvaddint32.s More details are in "vect_set_loop_controls_by_while_len" implementation and comments. Consider such followin

Re: [PATCH] combine: Fix simplify_comparison AND handling for WORD_REGISTER_OPERATIONS targets [PR109040]

On 4/6/23 04:31, Jakub Jelinek wrote: As before, I unfortunately can't test it on riscv-linux (could perhaps try that on sparc-solaris on GCC Farm which is another WORD_REGISTER_OPERATIONS target, but last my bootstrap attempt there failed miserably because of the Don't bootstrap at midnight

Re: [PATCH] combine: Fix simplify_comparison AND handling for WORD_REGISTER_OPERATIONS targets [PR109040]

> If the > (and:SI (subreg:SI (reg:HI xxx) 0) (const_int 0x84c)) > to > (subreg:SI (and:HI (reg:HI xxx) (const_int 0x84c)) 0) > transformation is kosher for WORD_REGISTER_OPERATIONS, then I guess the > invalid operation is then in > simplify_context::simplify_binary_operation_1 > case AND: > ..

Re: [PATCH] riscv: Fix genrvv-type-indexer dependencies

LGTM, thanks :) On Thu, Apr 6, 2023 at 5:46 PM Jakub Jelinek via Gcc-patches wrote: > > Hi! > > I've noticed > make: Circular build/genrvv-type-indexer.o <- gtype-desc.h dependency dropped. > > The following patch fixes that. The RTL_BASE_H variable includes a lot of > headers which the generato

[PATCH] gcov: add info about "calls" to JSON output format

Patch can bootstrap on x86_64-linux-gnu and survives regression tests. Ready to be installed after stage1 opens? Thanks, Martin gcc/ChangeLog: * doc/gcov.texi: Document the new "calls" field and document the API bump. * gcov.cc (output_intermediate_json_line): Output inf

Re: [PATCH] RISC-V: Fix regression of -fzero-call-used-regs=all

--- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -7317,6 +7317,12 @@ riscv_shamt_matches_mask_p (int shamt, HOST_WIDE_INT mask) #undef TARGET_DWARF_POLY_INDETERMINATE_VALUE #define TARGET_DWARF_POLY_INDETERMINATE_VALUE riscv_dwarf_poly_indeterminate_value +namespace riscv_ve

[PATCH] RISC-V: Fix regression of -fzero-call-used-regs=all

From: Yanzhang Wang This patch registers a riscv specific function to TARGET_ZERO_CALL_USED_REGS instead of default in targhooks.cc. It will clean gpr and vector relevant registers. PR 109104 gcc/ChangeLog: * config/riscv/riscv-v.cc (default_zero_call_used_regs): (riscv

Re: [PATCH 1/7] openmp: Add Fortran support for "omp unroll" directive

Hi Thomas, On 01.04.23 10:42, Thomas Schwinge wrote: ... I see FAIL for x86_64-pc-linux-gnu '-m32' (thus, host, not offloading), '-O0' (only): [...] FAIL: libgomp.fortran/loop-transforms/unroll-1.f90 -O0 execution test [...] FAIL: libgomp.fortran/loop-transforms/unroll-simd-

Re: [PATCH] Add ssp_nonshared to link commandline for musl targets

On Thu, Apr 06, 2023 at 05:03:22PM +0530, Yash Shinde via Gcc-patches wrote: > When -fstack-protector options are enabled we need to > link with ssp_shared on musl since it does not provide > the __stack_chk_fail_local() so essentially it provides > libssp but not libssp_nonshared something like >

[PATCH] Search target sysroot gcc version specific dirs with multilib.

From: Khem Raj We install the gcc libraries (such as crtbegin.p) into //5.2.0/ which is a default search path for GCC (aka multi_suffix in the code below). is 'machine' in gcc's terminology. We use these directories so that multiple gcc versions could in theory co-exist on target. We only want

[PATCH] gcc: armv4: pass fix-v4bx to linker to support EABI.

The LINK_SPEC for linux gets overwritten by linux-eabi.h which means the value of TARGET_FIX_V4BX_SPEC gets lost and as a result the option is not passed to linker when chosing march=armv4 This patch redefines this in linux-eabi.h and reinserts it for eabi defaulting toolchains. Signed-off-by: Khe

Re: [PATCH] combine: Fix simplify_comparison AND handling for WORD_REGISTER_OPERATIONS targets [PR109040]

On Thu, Apr 06, 2023 at 12:51:20PM +0200, Eric Botcazou wrote: > > If we want to fix it in the combiner, I think the fix would be following. > > The optimization is about > > (and:SI (subreg:SI (reg:HI xxx) 0) (const_int 0x84c)) > > and IMHO we can only optimize it into > > (subreg:SI (and:HI (reg:

[PATCH] Add ssp_nonshared to link commandline for musl targets

From: Khem Raj When -fstack-protector options are enabled we need to link with ssp_shared on musl since it does not provide the __stack_chk_fail_local() so essentially it provides libssp but not libssp_nonshared something like TARGET_LIBC_PROVIDES_SSP_BUT_NOT_SSP_NONSHARED where-as for glibc the

Re: [aarch64] Use dup and zip1 for interleaving elements in initializing vector

On Thu, 6 Apr 2023 at 16:05, Richard Sandiford wrote: > > Prathamesh Kulkarni writes: > > On Tue, 4 Apr 2023 at 23:35, Richard Sandiford > > wrote: > >> > diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc > >> > b/gcc/config/aarch64/aarch64-sve-builtins-base.cc > >> > index cd9cace3c

[PATCH 2/3] RFC - match.pd: simplify debug dump checks

Hi All, Just sending these so people can test the series This is a small improvement in QoL codegen for match.pd to save time not re-evaluating the condition for printing debug information in every function. There is a small but consistent runtime and compile time win here. The runtime win come

[PATCH 1/3] RFC match.pd: don't emit label if not needed

Hi All, Just sending these so people can test the series. This is a small QoL codegen improvement for match.pd to not emit labels when they are not needed. The codegen is nice and there is a small (but consistent) improvement in compile time. Bootstrapped Regtested on aarch64-none-linux-gnu and

Re: [PATCH] combine: Fix simplify_comparison AND handling for WORD_REGISTER_OPERATIONS targets [PR109040]

> If we want to fix it in the combiner, I think the fix would be following. > The optimization is about > (and:SI (subreg:SI (reg:HI xxx) 0) (const_int 0x84c)) > and IMHO we can only optimize it into > (subreg:SI (and:HI (reg:HI xxx) (const_int 0x84c)) 0) > if we know that the upper bits of the REG

[PATCH v2] ree: Improve ree pass for rs6000 target.

Hello All: Eliminate unnecessary redundant extension within basic and across basic blocks. For rs6000 target we see redundant zero and sign extension and done to improve ree pass to eliminate such redundant zero and sign extension. Bootstrapped and regtested on powerpc64-linux-gnu. Thanks & Re

Re: [PATCH] PR tree-optimization/109417 - Check if dependency is valid before using in may_recompute_p.

On Wed, Apr 05, 2023 at 04:10:25PM -0400, Andrew MacLeod via Gcc-patches wrote: > When a statement is first processed, any SSA_NAMEs that are dependencies are > cached for quick future access. > > if we ;later rewrite the statement (say propagate a constant into it), its > possible the ssa-name in

[PATCH] update_web_docs_git: Add updated Texinfo to PATH

maintainer-scripts/ChangeLog: * update_web_docs_git: Add updated Texinfo to PATH --- Hi, I'm posting this as a ping and a patch necessary to get the wwwdocs building with the new Texinfo version that's installed on gcc.gnu.org. It would be nice to do this ahead of the GCC 13 release. I m

Re: [aarch64] Use dup and zip1 for interleaving elements in initializing vector

Prathamesh Kulkarni writes: > On Tue, 4 Apr 2023 at 23:35, Richard Sandiford > wrote: >> > diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc >> > b/gcc/config/aarch64/aarch64-sve-builtins-base.cc >> > index cd9cace3c9b..3de79060619 100644 >> > --- a/gcc/config/aarch64/aarch64-sve-buil

[PATCH] combine: Fix simplify_comparison AND handling for WORD_REGISTER_OPERATIONS targets [PR109040]

On Thu, Apr 06, 2023 at 12:15:51PM +0200, Eric Botcazou wrote: > > Originally I didn't really see this as an operation. But the more and > > more I ponder it feels like it's an operation and thus should be subject > > to WORD_REGISTER_OPERATIONS. > > > > While it's not really binding on RTL seman

Re: [aarch64] Use dup and zip1 for interleaving elements in initializing vector

On Tue, 4 Apr 2023 at 23:35, Richard Sandiford wrote: > > Prathamesh Kulkarni writes: > > On Mon, 13 Mar 2023 at 13:03, Richard Biener wrote: > >> On GIMPLE it would be > >> > >> _1 = { a, ... }; // (a) > >> _2 = { _1, ... }; // (b) > >> > >> but I'm not sure if (b), a VL CTOR of fixed len(?)

Re: [PATCH] dse: Handle SUBREGs of word REGs differently for WORD_REGISTER_OPERATIONS targets [PR109040]

> Originally I didn't really see this as an operation. But the more and > more I ponder it feels like it's an operation and thus should be subject > to WORD_REGISTER_OPERATIONS. > > While it's not really binding on RTL semantics, if we look at how some > architectures implement reg->reg copies, t

[PATCH] riscv: Fix genrvv-type-indexer dependencies

Hi! I've noticed make: Circular build/genrvv-type-indexer.o <- gtype-desc.h dependency dropped. The following patch fixes that. The RTL_BASE_H variable includes a lot of headers which the generator doesn't include, including gtype-desc.h. I've preprocessed it and checked all gcc/libiberty header

RE: [PATCH] dse: Handle SUBREGs of word REGs differently for WORD_REGISTER_OPERATIONS targets [PR109040]

Yes, RISC-V riscv.h defined the WORD_REGISTER_OPERATIONS to be 1, while aarch64.h defined it as 0, with below comments. No idea this can fit RISC-V or not. /* WORD_REGISTER_OPERATIONS does not hold for AArch64. The assigned word_mode is DImode but operations narrower than SImode behave as

Re: [PATCH] dse: Handle SUBREGs of word REGs differently for WORD_REGISTER_OPERATIONS targets [PR109040]

Jeff Law writes: > On 4/5/23 10:48, Jakub Jelinek wrote: >> On Wed, Apr 05, 2023 at 10:17:59AM -0600, Jeff Law wrote: It is true that an instruction like (insn 8 7 9 2 (set (reg:HI 141) (subreg:HI (reg:SI 142) 0)) "aauu.c":6:18 181 {*movhi_internal} (nil))

Re: Rust front-end update 2023-04-05

Sigh thank you :) I'll blame this on the construction work going on in the building /s I have rebased the commits, built them and tested them, and they are now properly pushed. Thanks Thomas :) On 4/6/23 09:59, Thomas Schwinge wrote: Hi Arthur! On 2023-04-05T16:02:43+0200, arthur.co...

Re: [PATCH] LoongArch: Add built-in functions description of LoongArch BASE instruction set instructions.

On Thu, 2023-04-06 at 16:19 +0800, Lulu Cheng wrote: > gcc/ChangeLog: > > * doc/extend.texi: Add section for LoongArch BASE Built-in functions. > --- >  gcc/doc/extend.texi | 89 + >  1 file changed, 89 insertions(+) > > diff --git a/gcc/doc/exte

Re: [PATCH] [testsuite] [ppc] skip ppc-fortran if fortran is disabled

Hi Alexandre, on 2023/4/6 14:19, Alexandre Oliva wrote: > > Skip ppc-fortran.exp if a trivial fortran program cannot be compiled. > IIUC, without this patch and under the configuration disabling fortran, all the cases in this sub-testsuite would fail? Thanks for fixing! > Regstrapped on x86_6

Re: [PATCHv3, rs6000] rs6000: correct vector sign extend built-ins on Big Endian [PR108812]

Hi Haochen, on 2023/4/6 13:35, HAO CHEN GUI wrote: > Hi, > This patch removes byte reverse operation before vector integer sign > extension on big endian. These built-ins require to sign extend the element > of the input vector that would fall in the least significant portion of the > result ele

[PATCH] LoongArch: Add built-in functions description of LoongArch BASE instruction set instructions.

gcc/ChangeLog: * doc/extend.texi: Add section for LoongArch BASE Built-in functions. --- gcc/doc/extend.texi | 89 + 1 file changed, 89 insertions(+) diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 3adb67aa47a..417af6c368d 100644 -

Re: Rust front-end update 2023-04-05

Hi Arthur! On 2023-04-05T16:02:43+0200, arthur.co...@embecosm.com wrote: > This patchset contains around 80 commits concerning the Rust frontend. Did you not intend to actually 'git push' those? ;-P Grüße Thomas > We have been hard at work trying to get the Rust core library to > compile, a

[Committed] MAINTAINERS: Add myself as CTF and BTF reviewer

Looks like I did this only in my head back then. Finally pushed. Thanks! ChangeLog: * MAINTAINERS: Add myself. --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index c8045d49861..cebf45d49e5 100644 --- a/MAINTAINERS +++ b/MAI