> -Original Message-
> From: Richard Biener
> Sent: Saturday, November 5, 2022 11:33 AM
> To: Tamar Christina
> Cc: gcc-patches@gcc.gnu.org; nd ; rguent...@suse.de
> Subject: Re: [PATCH 1/8]middle-end: Recognize scalar reductions from
> bitfields and array_refs
>
> On Mon, Oct 31, 2022 a
在 2022/11/7 15:03, Andrew Pinski 写道:
The win32 thread model does not have `std::mutex`; but there is no
`pthread_mutex_t` either, so it
does not build either way.
Oh, but I would assume it will later on right?
There has been effort on C++11 threading support for win32 thread model, but I ha
On Sun, Nov 6, 2022 at 10:51 PM LIU Hao wrote:
>
> 在 2022-11-07 12:37, Andrew Pinski 写道:
> >
> > The original code which used pthread was added in GCC 5 way before GCC
> > moved to being written in C++11 which was only in the last 3 years.
> > pthread_* functions were the best choice at the time (
在 2022-11-07 12:37, Andrew Pinski 写道:
The original code which used pthread was added in GCC 5 way before GCC
moved to being written in C++11 which was only in the last 3 years.
pthread_* functions were the best choice at the time (2014) but now
GCC is written in C++11, I don't see any reason not
Hi,
For scalar extract/insert instructions, exponent field can be stored in a
32-bit register. So this patch changes the mode of exponent field from DI to
SI. So these instructions can be generated in a 32-bit environment. The patch
removes TARGET_64BIT check for these instructiions.
The instr
On Mon, Nov 7, 2022 at 9:41 AM Haochen Jiang via Gcc-patches
wrote:
>
> gcc/ChangeLog:
>
> * common/config/i386/i386-common.cc
> (processor_names): Add grandridge.
> (processor_alias_table): Ditto.
> * common/config/i386/i386-cpuinfo.h:
> (enum processor_typ
gcc/ChangeLog:
* config/i386/i386-options.cc (m_CORE_ATOM): New.
* config/i386/x86-tune.def
(X86_TUNE_SCHEDULE): Initial tune for CORE_ATOM.
(X86_TUNE_PARTIAL_REG_DEPENDENCY): Ditto.
(X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY): Ditto.
(X86_TUNE_SSE_PARTIAL
gcc/ChangeLog:
* common/config/i386/i386-common.cc
(processor_names): Add grandridge.
(processor_alias_table): Ditto.
* common/config/i386/i386-cpuinfo.h:
(enum processor_types): Add INTEL_GRANDRIDGE.
* config.gcc: Add -march=grandridge.
* co
Hi all,
These patches aimed to add initial Granite Rapids support for GCC.
Also we added a new m_CORE_ATOM for future atom core tune. They need
to be checked in after RAO-INT patch.
The information for Granite Rapids comes following:
https://www.intel.com/content/www/us/en/develop/download/intel-
On Sun, Nov 6, 2022 at 8:56 PM Kong, Lingling via Gcc-patches
wrote:
>
> Hi,
> The patches aimed to add Intel RAO-INT.
>
> The information is based on newly released
> Intel Architecture Instruction Set Extensions and Future Features.
>
> The document comes following:
> https://www.intel.com/conte
On Sun, Nov 6, 2022 at 9:00 PM Kong, Lingling via Gcc-patches
wrote:
>
> Hi
>
> The patch is to add flag -mprefer-remote-atomic to control whether to
> generate raoint insn for atomic operations.
> Ok for trunk?
Ok with below 2 little adjustments.
>
> BRs,
> Lingling
>
> gcc/ChangeLog:
>
>
On Fri, Nov 4, 2022 at 3:47 PM Haochen Jiang via Gcc-patches
wrote:
>
> Hi all,
>
> We will take back the patches which add a new parameter on original
> builtin_prefetch and implement instruction prefetch on that.
>
> Also we consider that since we will only do that on specific backend,
> no need
On Fri, Nov 4, 2022 at 4:14 PM Haochen Jiang via Gcc-patches
wrote:
>
> From: "Hu, Lin1"
>
> Hi all,
>
> This patch aimed to add initial Granite Rapids support for GCC.
> It needs to be checked in after prefetchit0/t1 patch.
>
> The information for Granite Rapids comes following:
> https://www.in
Hello,
On 06.11.22 21:32, Mikael Morin wrote:
Le 05/11/2022 à 23:28, Tobias Burnus a écrit :
OK for mainline?
The trans-array.c part looks good.
A couple of nits for the trans-expr.cc part:
- /* Use the rhs string length and the lhs element size. */
- size = string_length;
-
Hello,
Le 05/11/2022 à 23:28, Tobias Burnus a écrit :
Prior to the attached patch, there is a problem with realloc on assignment
with kind=4 characters as the string length was compared with the byte
size,
which was always true.
(...)
OK for mainline?
The trans-array.c part looks good.
A
On Sat, Nov 5, 2022 at 12:25 PM Richard Biener
wrote:
>
> On Wed, Nov 2, 2022 at 1:46 PM Uros Bizjak wrote:
> >
> > On Wed, Nov 2, 2022 at 1:45 PM Robin Dapp wrote:
> > >
> > > > IIRC, I was trying to "fix" modeless operand by giving it a mode, but
> > > > since it made no difference for x86, I
After Jakub and Richi's suggestion of using the same representation
for tracking known bits as we do in CCP, I took a peek at the code and
realized there's a plethora of bit-tracking code there that we could
be sharing with range-ops. For example, the multiplication
optimizations are way better th
Hi
The patch is to add flag -mprefer-remote-atomic to control whether to generate
raoint insn for atomic operations.
Ok for trunk?
BRs,
Lingling
gcc/ChangeLog:
* config/i386/i386.opt:Add -mprefer-remote-atomic.
* config/i386/sync.md (atomic_):
New define_expand.
Hi,
The patches aimed to add Intel RAO-INT.
The information is based on newly released
Intel Architecture Instruction Set Extensions and Future Features.
The document comes following:
https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programmin
From: Ju-Zhe Zhong
This patch support RVV scalable register spilling.
prologue && epilogue handling pick up prototype from Monk Chiang
.
Co-authored-by: Monk Chiang
gcc/ChangeLog:
* config/riscv/riscv-v.cc (emit_pred_move): Adjust for scalable
register spilling.
(legitimize_m
On Sun, 2022-11-06 at 09:46 +0800, Lulu Cheng wrote:
> I think it should be here:
>
> if (!increment && !decrement)
> continue;
>
> + if ((increment && rhs == HOST_WIDE_INT_MAX)
> + || (decrement && rhs == HOST_WIDE_INT_MIN))
> +
Perhaps rvv.exp should add -I. so that the wrapper is found regardless?
--
Andreas Schwab, sch...@linux-m68k.org
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510 2552 DF73 E780 A9DA AEC1
"And now for something completely different."
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