RE: [PATCH] PR tree-optimization/64992: (B << 2) != 0 is B when B is Boolean.

Hi Richard, > -Original Message- > From: Richard Biener > Sent: 08 August 2022 12:49 > Subject: Re: [PATCH] PR tree-optimization/64992: (B << 2) != 0 is B when B is > Boolean. > > On Mon, Aug 8, 2022 at 11:06 AM Roger Sayle > wrote: > > > > This patch resolves both PR tree-optimization/

Re: [PATCH] RISC-V: Avoid redundant sign-extension for SImode SGE, SGEU, SLE, SLEU

On Thu, 11 Aug 2022, Kito Cheng wrote: > LGTM, but with a nit, I don't get set.w but get an andi like below, so > maybe we should also scan-assembler-not andi? feel free to commit that > directly with that fix > > ```asm > sleu: >sgtua0,a0,a1# 9 [c=4 l=4] *sgtu_disi >

[PATCH take #2] PR tree-optimization/71343: Optimize (X<

Hi Richard, Many thanks for the review and useful suggestions. I (think I) agree that handling non-canonical forms in value_numbering makes more sense, so this revised patch is just the first (non-controversial) part of the original submission, that incorporates your observation that it doesn't n

[x86 PATCH take #2] Move V1TI shift/rotate lowering from expand to pre-reload split.

Hi Uros, As requested, here's an updated version of my patch that introduces a new const_0_to_255_not_mul_8_operand as you've requested. I think in this instance, having mutually exclusive patterns that can appear in any order, without imposing implicit ordering constraints, is slightly preferabl

Re: Rust frontend patches v1

On Aug 10, 2022, at 11:56 AM, Philip Herron wrote: > > For my v2 of the patches, I've been spending a lot of time ensuring > each patch is buildable. It would end up being simpler if it was > possible if each patch did not have to be like this so I could split > up the front-end in more patches.

[x86 PATCH] PR target/106577: force_reg may clobber operands during split.

This patch fixes PR target/106577 which is a recent ICE on valid regression caused by my introduction of a *testti_doubleword pre-reload splitter in i386.md. During the split pass before reload, this converts the virtual *testti_doubleword into an *andti3_doubleword and *cmpti_doubleword, checkin

[r13-2029 Regression] FAIL: gcc.dg/analyzer/torture/pr93451.c -Os (test for excess errors) on Linux/x86_64

On Linux/x86_64, 7e3b45befdbbf1a1f9ff728fa2bac31b4756907c is the first bad commit commit 7e3b45befdbbf1a1f9ff728fa2bac31b4756907c Author: Tim Lange Date: Fri Aug 12 10:27:16 2022 +0200 analyzer: out-of-bounds checker [PR106000] caused FAIL: gcc.dg/analyzer/torture/pr93451.c -O0 (test

Re: [PATCH v2] rs6000: Rework ELFv2 support for -fpatchable-function-entry* [PR99888]

Hi! On Fri, Aug 12, 2022 at 05:40:06PM +0800, Kewen.Lin wrote: > This patch is to update the NOPs patched before and after > local entry, it looks like: As I said before, please don't say NOPs. I know some documentation does. That docvumentation needs fixing. This is not an acronym or similar:

RE: [GCC][PATCH v2] arm: Add support for Arm Cortex-M85 CPU.

Hi, This patch adds the -mcpu support for the Arm Cortex-M85 CPU which is an Armv8.1-M Mainline CPU supporting MVE and PACBTI by default. -mpcu=cortex-m85 switch by default matches to -march=armv8.1-m.main+pacbti+mve.fp+fp.dp. Also following options are provided to disable default features. +no

[PATCH 13/15] arm: Add pacbti related multilib support for armv8.1-m.main.

Hi, This patch supports following -march/-mbranch-protection combination by linking them to existing pacbti multilibs. $ -march=armv8.1-m.main+pacbti+fp.dp+mve.fp -mbranch-protection=standard -mfloat-abi=hard -mthumb $ -march=armv8.1-m.main+pacbti+fp.dp+mve -mbranch-protection=standard -mfloa

Re: [PATCH 0/15] arm: Enables return address verification and branch target identification on Cortex-M

Andrea Corallo via Gcc-patches writes: > Hi all, > > as I respinned few patches, dropped one and added another, I'm reposting > this series thant enables return address verification and branch target > identification based on Armv8.1-M Pointer Authentication and Branch > Target Identification Ext

Re: [PATCH] Support threading of just the exit edge

On Fri, Aug 12, 2022 at 2:01 PM Richard Biener wrote: > > This started with noticing we add ENTRY_BLOCK to our threads > just for the sake of simplifying the conditional at the end of > the first block in a function. That's not really threading > anything but it ends up duplicating the entry bloc

[PATCH 12/15] arm: implement bti injection

Hi all, this patch enables Branch Target Identification Armv8.1-M Mechanism [1]. This is achieved by using the bti pass made common with Aarch64. The pass iterates through the instructions and adds the necessary BTI instructions at the beginning of every function and at every landing pads target

[PATCH 11/15] aarch64: Make bti pass generic so it can be used by the arm backend

Hi all, this patch splits and restructures the aarch64 bti pass code in order to have it usable by the arm backend as well. These changes have no functional impact. The original patch was approved here: . After that Richard E. note

[PATCH 10/15] arm: Implement cortex-M return signing address codegen

Hi all, this patch enables address return signature and verification based on Armv8.1-M Pointer Authentication [1]. To sign the return address, we use the PAC R12, LR, SP instruction upon function entry. This is signing LR using SP and storing the result in R12. R12 will be pushed into the stac

[PATCH 9/15] arm: Set again stack pointer as CFA reg when popping if necessary

Hi all, this patch enables 'arm_emit_multi_reg_pop' to set again the stack pointer as CFA reg when popping if this is necessary. /gcc/ * config/arm/arm.cc (arm_emit_multi_reg_pop): If the frame pointer was set define again the stack pointer as CFA reg when popping. diff --git a/

[PATCH 8/15] arm: Introduce multilibs for PACBTI target feature

This patch add the following new multilibs. thumb/v8.1-m.main+pacbti/mbranch-protection/nofp thumb/v8.1-m.main+pacbti+dp/mbranch-protection/soft thumb/v8.1-m.main+pacbti+dp/mbranch-protection/hard thumb/v8.1-m.main+pacbti+fp/mbranch-protection/soft thumb/v8.1-m.main+pacbti+fp/mbranch-protection/ha

[Committed] arm: Document +no options for Cortex-M55 CPU.

Hi, This patch documents the following options for Arm Cortex-M55 CPU under -mcpu= list. +nomve.fp (disables MVE single precision floating point instructions) +nomve (disables MVE integer and single precision floating point instructions) +nodsp (disables dsp, MVE integer and single precision flo

[PATCH 7/15] arm: Emit build attributes for PACBTI target feature

This patch emits assembler directives for PACBTI build attributes as defined by the ABI. gcc/ChangeLog: * config/arm/arm.c (arm_file_start): Emit EABI attributes for Tag_PAC_extension, Tag_BTI_extensi

[PATCH 6/15] arm: Add pointer authentication for stack-unwinding runtime

Hi all, this patch adds authentication for when the stack is unwound when an exception is taken. All the changes here are done to the runtime code in libgcc's unwinder code for Arm target. All the changes are guarded under defined (__ARM_FEATURE_PAC_DEFAULT) and activated only if the +pacbti feat

Re: [PATCH] tree-optimization/106593 - fix ICE with backward threading

On Fri, Aug 12, 2022 at 1:36 PM Richard Biener wrote: > > On Fri, 12 Aug 2022, Aldy Hernandez wrote: > > > On Fri, Aug 12, 2022 at 12:59 PM Richard Biener wrote: > > > > > > With the last re-org I failed to make sure to not add SSA names > > > nor supported by ranger into m_imports which then tri

[PATCH 5/15] arm: Implement target feature macros for PACBTI

This patch implements target feature macros when PACBTI is enabled through the -march option or -mbranch-protection. The target feature macros __ARM_FEATURE_PAC_DEFAULT and __ARM_FEATURE_BTI_DEFAULT are specified in ARM ACLE

[PATCH 4/15] arm: Add testsuite library support for PACBTI target

Hi all, this adds targeting-checking entities for PACBTI in testsuite framework. Pre-approved with the requested changes here . gcc/testsuite/ChangeLog: * testsuite/lib/target-supports.exp: (check_effective_tar

[PATCH 3/15] arm: Add option -mbranch-protection

Hi all, this adds -mbranch-protection option. This option enables the code-generation of pointer signing and authentication instructions in function prologues and epilogues. gcc/ChangeLog: * config/arm/arm.c (arm_configure_build_target): Parse and validate -mbranch-protection op

[PATCH 2/15] arm: Add Armv8.1-M Mainline target feature +pacbti

This patch adds the -march feature +pacbti to Armv8.1-M Mainline. This feature enables pointer signing and authentication instructions on M-class architectures. Pre-approved here . gcc/Changelog: * config/arm/arm.h (TAR

[PATCH 1/15] arm: Make mbranch-protection opts parsing common to AArch32/64

Hi all, This change refactors all the mbranch-protection option parsing code and types to make it common to both AArch32 and AArch64 backends. This change also pulls in some supporting types from AArch64 to make it common (aarch_parse_opt_result). The significant changes in this patch are the mo

Re: [PATCH] tree-optimization/106593 - fix ICE with backward threading

In that case Richi, go right ahead with your original patch. I for one am happy we can use range_on_entry, which always seemed cleaner. Aldy On Fri, Aug 12, 2022, 16:07 Andrew MacLeod wrote: > > On 8/12/22 09:38, Andrew MacLeod wrote: > > > > On 8/12/22 07:31, Aldy Hernandez wrote: > >> On Fri,

[PATCH] s390: Implement vec_set with vec_merge and, vec_duplicate.

Hi, similar to other backends this patch implements vec_set via vec_merge and vec_duplicate instead of an unspec. This opens up more possibilites to combine instructions. Bootstrapped and regtested. No regressions. Is it OK? Regards Robin gcc/ChangeLog: * config/s390/s390.md: Implem

[PATCH 0/15] arm: Enables return address verification and branch target identification on Cortex-M

Hi all, as I respinned few patches, dropped one and added another, I'm reposting this series thant enables return address verification and branch target identification based on Armv8.1-M Pointer Authentication and Branch Target Identification Extension [1] for Arm Cortex-M. This feature is contro

Fix invalid devirtualization when combining final keyword and anonymous types

Hi, this patch fixes a wrong code issue where we incorrectly devirtualize to __builtin_unreachable. The problem occurs in combination of anonymous namespaces and final keyword used on methods. We do two optimizations here 1) when reacing final method we cut the search for possible new targets 2

[PATCH] s390: Implement vec_extract via vec_select.

Hi, vec_select can handle dynamic/runtime masks nowadays. Therefore we can get rid of the UNSPEC_VEC_EXTRACT that was preventing further optimizations like combining instructions with vec_extract patterns. Bootstrapped and regtested. No regressions. Is it OK? Regards Robin gcc/ChangeLog:

Re: [PATCH] tree-optimization/106593 - fix ICE with backward threading

On 8/12/22 09:38, Andrew MacLeod wrote: On 8/12/22 07:31, Aldy Hernandez wrote: On Fri, Aug 12, 2022 at 12:59 PM Richard Biener wrote: With the last re-org I failed to make sure to not add SSA names nor supported by ranger into m_imports which then triggers an ICE in range_on_path_entry bec

[committed] Improve comment for tree_niter_desc.{control,bound,cmp}

Fix typos and explain ERROR_MARK usage. gcc/ChangeLog: * tree-ssa-loop.h: Improve comment --- diff --git a/gcc/tree-ssa-loop.h b/gcc/tree-ssa-loop.h index 415f461c37e4cd7df0b49f6104f796c49cc830fa..6c70f795d171f22b3ed75873fec4920fea75255b 100644 --- a/gcc/tree-ssa-loop.h +++ b/gcc/tree

Re: [PATCH] tree-optimization/106593 - fix ICE with backward threading

On 8/12/22 07:31, Aldy Hernandez wrote: On Fri, Aug 12, 2022 at 12:59 PM Richard Biener wrote: With the last re-org I failed to make sure to not add SSA names nor supported by ranger into m_imports which then triggers an ICE in range_on_path_entry because range_of_expr returns false. I've no

[PATCH] Support threading of just the exit edge

This started with noticing we add ENTRY_BLOCK to our threads just for the sake of simplifying the conditional at the end of the first block in a function. That's not really threading anything but it ends up duplicating the entry block, and re-writing the result instead of statically fold the jump.

Re: [PATCH] tree-optimization/106593 - fix ICE with backward threading

On Fri, 12 Aug 2022, Aldy Hernandez wrote: > On Fri, Aug 12, 2022 at 12:59 PM Richard Biener wrote: > > > > With the last re-org I failed to make sure to not add SSA names > > nor supported by ranger into m_imports which then triggers an > > ICE in range_on_path_entry because range_of_expr return

Re: [PATCH] tree-optimization/106593 - fix ICE with backward threading

On Fri, Aug 12, 2022 at 12:59 PM Richard Biener wrote: > > With the last re-org I failed to make sure to not add SSA names > nor supported by ranger into m_imports which then triggers an > ICE in range_on_path_entry because range_of_expr returns false. I've > noticed that range_on_path_entry does

Re: [PATCH] vect: Don't allow vect_emulated_vector_p type in vectorizable_call [PR106322]

on 2022/8/12 19:14, Richard Biener wrote: > On Fri, Aug 12, 2022 at 11:41 AM Kewen.Lin wrote: >> >> Hi, >> >> As PR106322 shows, in some cases for some vector type whose >> TYPE_MODE is a scalar integral mode instead of a vector mode, >> it's possible to obtain wrong target support information whe

Re: [PATCH] vect: Don't allow vect_emulated_vector_p type in vectorizable_call [PR106322]

On Fri, Aug 12, 2022 at 11:41 AM Kewen.Lin wrote: > > Hi, > > As PR106322 shows, in some cases for some vector type whose > TYPE_MODE is a scalar integral mode instead of a vector mode, > it's possible to obtain wrong target support information when > querying with the scalar integral mode. For e

RE: [PATCH]AArch64 sve: Fix fcmuo combine patterns [PR106524]

> -Original Message- > From: Tamar Christina > Sent: Friday, August 12, 2022 11:21 AM > To: gcc-patches@gcc.gnu.org > Cc: nd ; Richard Earnshaw ; > Marcus Shawcroft ; Kyrylo Tkachov > ; Richard Sandiford > > Subject: [PATCH]AArch64 sve: Fix fcmuo combine patterns [PR106524] > > Hi All,

[PATCH] s390: Implement vec_revb(vector short)/bswapv8hi with, verllh.

Hi, this patch implements a byte swap for a V8HImode vector via an element rotate by 8 bits. Bootstrapped and regtested, no regressions. Is it OK? Regards Robin gcc/ChangeLog: PR target/100867 * config/s390/vector.md: Add special case for V8HImode. gcc/testsuite/ChangeLog:

[PATCH] tree-optimization/106593 - fix ICE with backward threading

With the last re-org I failed to make sure to not add SSA names nor supported by ranger into m_imports which then triggers an ICE in range_on_path_entry because range_of_expr returns false. I've noticed that range_on_path_entry does mightly complicated things that don't make sense to me and the co

Re: [PATCH] phiopt: Remove unnecessary checks from spaceship_replacement [PR106506]

On Thu, 11 Aug 2022, Jakub Jelinek wrote: > Hi! > > Those 2 checks were just me trying to be extra careful, the > (phires & 1) == phires and variants it is folded to of course make only sense > for the -1/0/1/2 result spaceship, for -1/0/1 one can just use comparisons of > phires. We only floati

[PATCH] s390: Recognize reverse/element swap permute patterns.

Hi, this adds functions to recognize reverse/element swap permute patterns for vler, vster as well as vpdi and rotate. Bootstrapped and regtested, no regressions. Is it OK? Regards Robin gcc/ChangeLog: * config/s390/s390.cc (expand_perm_with_vpdi): Recognize swap pattern. (is

GCC 12.1.1 Status Report (2022-08-12), branch frozen for release

Status == The gcc-12 branch is now frozen in preparation for a GCC 12.2 release candidate and the GCC 12.2 release next week. All changes now require release manager approval. Quality Data Priority # Change from last report --- --

[PATCH]AArch64 sve: Fix fcmuo combine patterns [PR106524]

Hi All, There's no encoding for fcmuo with zero. This restricts the combine patterns from accepting zero registers. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for master? and GCC 12 branch once unfrozen? Thanks, Tamar gcc/ChangeLog: PR target/106524 *

[PATCH] s390: Use vpdi and verllg in vec_reve.

Hi, swapping the two elements of a V2DImode or V2DFmode vector can be done with vpdi instead of using the generic way of loading a permutation mask from the literal pool and vperm. Analogous to the V2DI/V2DF case reversing the elements of a four-element vector can be done by first swapping the el

[PATCH] s390: Add z15 to s390_issue_rate.

Hi, this patch tries to be more explicit by mentioning z15 in s390_issue_rate. No changes in testsuite, bootstrap or SPEC obviously. Is it OK? Regards Robin gcc/ChangeLog: * config/s390/s390.cc (s390_issue_rate): Add z15. --- gcc/config/s390/s390.cc | 1 + 1 file changed, 1 insertio

[PATCH] s390: Add -munroll-only-small-loops.

Hi, inspired by Power we also introduce -munroll-only-small-loops. This implies activating -funroll-loops and -munroll-only-small-loops at -O2 and above. Bootstrapped and regtested. This introduces one regression in gcc.dg/sms-compare-debug-1.c but currently dumps for sms are broken as well. T

Re: [PATCH] rs6000: avoid ineffective replacement of splitters

Hi Jeff, on 2022/8/12 14:39, Jiufu Guo via Gcc-patches wrote: > Hi, > > As a comment in > https://gcc.gnu.org/pipermail/gcc-patches/2022-August/599556.html > > Those splitters call rs6000_emit_set_const directly, and the replacements > are never used. Using (pc) would be less misleading. Since

[PATCH] vect: Don't allow vect_emulated_vector_p type in vectorizable_call [PR106322]

Hi, As PR106322 shows, in some cases for some vector type whose TYPE_MODE is a scalar integral mode instead of a vector mode, it's possible to obtain wrong target support information when querying with the scalar integral mode. For example, for the test case in PR106322, on ppc64 32bit vectorizer

[PATCH v2] rs6000: Rework ELFv2 support for -fpatchable-function-entry* [PR99888]

Hi, As PR99888 and its related show, the current support for -fpatchable-function-entry on powerpc ELFv2 doesn't work well with global entry existence. For example, with one command line option -fpatchable-function-entry=3,2, it got below w/o this patch: .LPFE1: nop nop

[PATCH v6] LoongArch: add addr_global attribute

v5 -> v6: * still use "addr_global" as we don't have a better name. * add a test case with -mno-explicit-relocs. -- >8 -- A linker script and/or a section attribute may locate a local object in some way unexpected by the code model, leading to a link failure. This happens when the Linux kernel

[committed] testsuite: Fix up pr106243* tests on i686-linux [PR106243]

Hi! These 2 tests were FAILing on i686-linux or e.g. with --target_board=unix/-m32/-mno-sse on x86_64-linux due to -Wpsabi warnings. Tested with make check-gcc check-g++ RUNTESTFLAGS='--target_board=unix\{-m32,-m32/-mno-sse,-m64\} dg.exp=pr106243*' on x86_64-linux, committed to trunk as obvious.

[committed] testsuite: Fix up pr104992* tests on i686-linux [PR104992]

Hi! These 2 tests were FAILing on i686-linux or e.g. with --target_board=unix/-m32/-mno-sse on x86_64-linux due to -Wpsabi warnings and also because dg-options in the latter test has been ignored due to missing space, so even -O2 wasn't passed at all. Tested with make check-gcc check-g++ RUNTEST

[PATCH] phiopt: Remove unnecessary checks from spaceship_replacement [PR106506]

Hi! Those 2 checks were just me trying to be extra careful, the (phires & 1) == phires and variants it is folded to of course make only sense for the -1/0/1/2 result spaceship, for -1/0/1 one can just use comparisons of phires. We only floating point spaceship if nans aren't honored, so the 2 cas

Re: [PATCH v3] Modify combine pattern by a pseudo AND with its nonzero bits [PR93453]

Hi Segher, On 12/8/2022 上午 1:40, Segher Boessenkool wrote: > Yes, but combine will use splitters as well. Combine pass invokes combine_split_insns for 3-insn combine. If we want to do the split for 2-insn combine (like the test case in PR), we have to add a special case? > > You can use nonzero_