[PATCH] [AVX512]For vector compare to mask register, UNSPEC is needed instead of comparison operator [PR96243]

Hi: For rtx like (eq:HI (V8SI 90) (V8SI 91)), cse will take it as a boolean value and try to do some optimization. But it is not true for vector compare, also other places in rtl passes hold the same assumption. Bootstrap is ok, regression test is ok for i386 backend. 2020-07-20 Hongtao Liu

[patch] gcc/testsuite: Scale down long-running tree-prof.exp tests on slow targets

I was looking at some timeout failures in nios2-linux-gnu test results and found several tree-prof.exp tests were doing what appears to be an excessive number of iterations (350 million?). Even though this is hardware and not a simulator, I thought it would be reasonable to tell the test harne

Re: [PATCH 3/4] libstdc++: Add floating-point std::to_chars implementation

On Fri, 17 Jul 2020, Patrick Palka wrote: > On Fri, 17 Jul 2020, Patrick Palka wrote: > > > On Wed, 15 Jul 2020, Patrick Palka wrote: > > > > > On Tue, 14 Jul 2020, Patrick Palka wrote: > > > > > > > This implements the floating-point std::to_chars overloads for float, > > > > double and long d

gcc.dg/const-uniq-1.c: Adjust scanned pattern for mmix.

Apparently local labels end up in the gimple dumps. For mmix, local labels that for other targets look like ".LC0" or "LC.0" instead look like "LC:0". Committed as obvious. gcc/testsuite: * gcc.dg/const-uniq-1.c: Adjust scanned pattern for mmix. --- gcc/gcc/testsuite/gcc.dg/const-uniq-1

gcc.dg/cdce3.c: Skip for mmix.

The test is gated on effective-target hard_float but what it really requires is a sqrtf insn (SFmode, not DFmode). (It indeed passes for mmix-knuth-mmixware if the sqrtf is changed to sqrt and float to double; there is a DFmode sqrt insn.) Committed. gcc/testsuite: * gcc.dg/cdce3.c: Skip

Re: [PATCH 5/7 v7] vect: Support vector load/store with length in vectorizer

Hi Richard, on 2020/7/17 下午5:54, Richard Sandiford wrote: > Hi, > > Sorry for the slow review. > >> The new version v7 is attached which has addressed your review comments >> on v6. Could you have a further look? Many thanks in advance! >> >> Bootstrapped/regtested on aarch64-linux-gnu and pow

Re: [PATCH v2] [RISC-V] Add support for TLS stack protector canary access

Ping On 2020/7/13 下午4:15, cooper wrote: gcc/ * config/riscv/riscv-opts.h (stack_protector_guard): New enum. * config/riscv/riscv.c (riscv_option_override): Handle the new options. * config/riscv/riscv.md (stack_protect_set): New pattern to handle flexible

gcc.dg/pr87485.c: Require scheduling

Committed as obvious, fixing one failure for mmix-knuth-mmixware. gcc/testsuite: * gcc.dg/pr87485.c: Require scheduling. --- gcc/gcc/testsuite/gcc.dg/pr87485.c.orig Mon Jul 20 03:50:14 2020 +++ gcc/gcc/testsuite/gcc.dg/pr87485.c Mon Jul 20 03:50:31 2020 @@ -2,6 +2,7 @@ /* { dg-do co

mmix: When debug-dump, revert to "standard" pseudos for emitting integers

The sole purpose of not providing pseudos and forcing use of TARGET_ASM_INTEGER is to arrange for assembly output that people can, instead of using gas, usefullt feed to mmixal (Knuth's assembler). It uses pseudos with slightly different semantics (BYTE, WYDE, TETRA, OCTA). Nice when it works, bu

[PATCH PR95696] regrename creates overlapping register allocations for vliw

Hi， In most target, it is limited to issue two insns with change the same register. So a register is not realy unused if there is another insn, which set the register in the save VLIW. For example, The insn 73 start with insn:TI, so it will be issued together with others insns until a new insn

Re: [PATCH] config/debuginfod.m4: Use PKG_CHECK_MODULES

On 2020-07-16 6:37 p.m., Aaron Merey wrote: > On Fri, May 8, 2020 at 4:56 PM Tom Tromey wrote: >> >>> "Aaron" == Aaron Merey via Binutils writes: >> >> Aaron> * Makefile.in: Replace LIBDEBUGINFOD with DEBUGINFOD_LIBS. >> Aaron> * aclocal.m4: Rebuild. >> >> Instead of inlining

[patch, fortran, committed] Fix PR 96220, error with -fc-prototypes

Hello world, I have just committed the attached patch as simple and obvoius. The problem was that, for a test case like module f_global_vars_m use, intrinsic :: iso_c_binding, sp => c_float, dp => c_double implicit none real(dp), bind(c) :: one= 1.0_dp, four= 4.0_dp end module f_global_vars_m t

Re: [PATCH] x86: Add __cpuidex and include guard to

On Sun, Jul 19, 2020 at 12:19 AM Uros Bizjak wrote: > > > Add > > > > void __cpuidex (int __cpuid_info[4], int __leaf, int __subleaf); > > > > as well as include guard to . > > > > gcc/ > > > > PR target/95973 > > PR target/96238 > > * config/i386/cpuid.h: Add include guard. > > (__cpuidex): New.

[PATCH] middle-end: Simplify (sign_extend:HI (truncate:QI (ashiftrt:HI X 8)))

The combination of several my recent nvptx patches has revealed an interesting RTL optimization opportunity. This patch to simplify-rtx.c simplifies (sign_extend:HI (truncate:QI (?shiftrt:HI x 8))) to just (ashiftrt:HI x 8), as the inner shift already sets the high bits appropriately. The equiva

Re: [PATCH] x86: Add __cpuidex and include guard to

> Add > > void __cpuidex (int __cpuid_info[4], int __leaf, int __subleaf); > > as well as include guard to . > > gcc/ > > PR target/95973 > PR target/96238 > * config/i386/cpuid.h: Add include guard. > (__cpuidex): New. > > gcc/testsuite/ > > PR target/95973 > PR target/96238 > * gcc.target/i386/pr