[PATCH] MIPS: Default to --with-llsc for the R5900 Linux target as well

2018-10-05 Thread Fredrik Noring
The Linux kernel requires and emulates LL and SC for the R5900 too. The special --without-llsc default for the R5900 is therefore not applicable in that case. --- gcc/config.gcc | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/gcc/config.gcc b/gcc/config.gcc index 0c579d

Re: [nvptx] vector length patch series

2018-10-05 Thread Tom de Vries
On 9/18/18 10:04 PM, Cesar Philippidis wrote: > 591973d3c3a [nvptx] use user-defined vectors when possible If I drop this patch, I get the same test results. Can you find a testcase for which this patch has an effect? Thanks, - Tom

Re: [PATCH 2/2 v3][IRA,LRA] Fix PR86939, IRA incorrectly creates an interference between a pseudo register and a hard register

2018-10-05 Thread Peter Bergner
On 10/5/18 4:12 PM, Vladimir Makarov wrote: > On 10/05/2018 04:00 PM, Peter Bergner wrote: >> How about non_conflicting_reg_copy or non_conflicting_copy_insn? > OK. I like the first name more. Ok, I committed the patch using the first function name. Thank you very much for the patch reviews and ap

Re: [PATCHv3][PR 81376] Remove unnecessary float casts in comparisons

2018-10-05 Thread Yuri Gribov
On Wed, Oct 3, 2018 at 5:11 PM Jeff Law wrote: snip > OK. You've got commit privileges, right? Yup, will commit myself. -I

[PATCH] diagnose bogus assume_aligned attributes (PR 87533)

2018-10-05 Thread Martin Sebor
While working on tests for an enhancement in the area of attributes I noticed that the handler for attribute assume_aligned (among others) does only a superficial job of detecting meaningless specifications such as using the attribute on a function returning void or alignments that aren't powers o

Re: [PATCH, testsuite] memchr-1.c wide char and AIX

2018-10-05 Thread Martin Sebor
David, Attached is a patch to conditionalize the memchr-1.c test to pass even with 2-byte wchar_t's. It also adds a compile only test to verify memchr with -fnarrow-wchar. I verified the changes on LE x86_64-linux and BE powerpc64-linux but if you could confirm they also work on AIX that would

Re: [PATCH 2/2 v3][IRA,LRA] Fix PR86939, IRA incorrectly creates an interference between a pseudo register and a hard register

2018-10-05 Thread Vladimir Makarov
On 10/05/2018 04:00 PM, Peter Bergner wrote: On 10/5/18 1:32 PM, Vladimir Makarov wrote: On 10/05/2018 12:40 PM, Peter Bergner wrote: On 10/4/18 3:01 PM, Vladimir Makarov wrote: IMHO, the name copy_insn_p is too common and confusing (we already have functions copy_insn and copy_insn_1 in GCC).

Re: [PATCH] RISC-V: Fix unordered float compare for Signaling NaN.

2018-10-05 Thread Jim Wilson
On Fri, Oct 5, 2018 at 9:44 AM Jim Wilson wrote: > With a modified version of Andrew's patch, the testcase in Kito's > patch works, and I see the glibc testsuite failures drop from 151 to > 131, so there is still something wrong. Last time I ran the glibc > testsuite we were around 50-60 failures

[PATCH] RISC-V: Fix -fsignaling-nans for glibc testsuite.

2018-10-05 Thread Jim Wilson
This makes -fsignaling-nans work correctly, fixing 20 glibc testsuite failures. The FP quiet compare pattern is ignoring all exceptions, including for SNaNs. To make this work right when -fsignaling-nan, we need an extra eq compare to raise an exception, but only when HONOR_SNANS is true. So we ge

Re: Merge from trunk to gccgo branch

2018-10-05 Thread Ian Lance Taylor
On Fri, Oct 5, 2018 at 1:13 PM, Ian Lance Taylor wrote: > I merged trunk revision 264890 to the gccgo branch. Sorry, trunk revision was 264887. Ian

Re: Merge from trunk to gccgo branch

2018-10-05 Thread Ian Lance Taylor
I merged trunk revision 264890 to the gccgo branch. Ian

Re: [PATCH, testsuite] memchr-1.c wide char and AIX

2018-10-05 Thread Martin Sebor
On 10/05/2018 12:54 PM, David Edelsohn wrote: memchr-1.c tests for char (test_narrow) and wchar (test_wide). The wide character test assumes 32 bit wide character, while 32 bit AIX uses 16 bit wide character. This assumption causes the wide character part of the test to fail in 32 bit mode on A

Re: Default compute dimensions (runtime)

2018-10-05 Thread Julian Brown
Hi, Continuing the thread from here: https://gcc.gnu.org/ml/gcc-patches/2016-02/msg00198.html On Wed, 3 Feb 2016 19:52:09 +0300 Alexander Monakov wrote: > On Wed, 3 Feb 2016, Nathan Sidwell wrote: > > You can only override at runtime those dimensions that you said > > you'd override at runtime

Re: [PATCH 2/2 v3][IRA,LRA] Fix PR86939, IRA incorrectly creates an interference between a pseudo register and a hard register

2018-10-05 Thread Peter Bergner
On 10/5/18 1:32 PM, Vladimir Makarov wrote: > On 10/05/2018 12:40 PM, Peter Bergner wrote: >> On 10/4/18 3:01 PM, Vladimir Makarov wrote: >>> IMHO, the name copy_insn_p is too common and confusing (we already have >>> functions copy_insn and copy_insn_1 in GCC). The name does not reflect its >>> r

[PATCH] rs6000: Some mfcr pattern simplification

2018-10-05 Thread Segher Boessenkool
2018-10-05 Segher Boessenkool * config/rs6000/rs6000.md (unnamed mfcr scc_comparison_operator patterns): Merge SI and DI patterns to a GPR pattern. (unnamed define_insn and define_split for record form of that): Merge to a single define_insn_and_split pattern. -

Re: [PATCHv2] Handle not explicitly zero terminated strings in merge sections

2018-10-05 Thread Bernd Edlinger
On 10/05/18 20:15, Andreas Schwab wrote: > On Sep 14 2018, Bernd Edlinger wrote: > >> diff -Npur gcc/testsuite/gnat.dg/string_merge1.adb >> gcc/testsuite/gnat.dg/string_merge1.adb >> --- gcc/testsuite/gnat.dg/string_merge1.adb 1970-01-01 01:00:00.0 >> +0100 >> +++ gcc/testsuite/gnat.dg

Re: [PATCH v2, rs6000] 2/2 Add x86 SSE3 intrinsics to GCC PPC64LE target

2018-10-05 Thread Segher Boessenkool
On Fri, Oct 05, 2018 at 12:59:14PM -0500, Paul Clarke wrote: > This is part 2/2 for contributing PPC64LE support for X86 SSE3 > instrisics. This patch includes testsuite/gcc.target tests for the > intrinsics defined in pmmintrin.h. > > Tested on POWER8 ppc64le and ppc64 (-m64 and -m32, the latter

[PATCH, testsuite] memchr-1.c wide char and AIX

2018-10-05 Thread David Edelsohn
memchr-1.c tests for char (test_narrow) and wchar (test_wide). The wide character test assumes 32 bit wide character, while 32 bit AIX uses 16 bit wide character. This assumption causes the wide character part of the test to fail in 32 bit mode on AIX (it succeeds on 64 bit AIX). The testcase al

[PATCH, i386]: Remove cmp_*_cc_i387 FP compare patterns

2018-10-05 Thread Uros Bizjak
These are ineffective, since no pass considers compares inside PARALLELs. They just weather through all pre-reload passes and then split to fcom+fnstsw/sahf sequence. We can as well expand compares to the above sequence at expand time. 2018-10-05 Uros Bizjak * config/i386/i386.md (*cmpxf_c

Re: [PATCH 2/2 v3][IRA,LRA] Fix PR86939, IRA incorrectly creates an interference between a pseudo register and a hard register

2018-10-05 Thread Vladimir Makarov
On 10/05/2018 12:40 PM, Peter Bergner wrote: On 10/4/18 3:01 PM, Vladimir Makarov wrote: IMHO, the name copy_insn_p is too common and confusing (we already have functions copy_insn and copy_insn_1 in GCC). The name does not reflect its result meaning. I would call it something like non_conflic

Re: [PATCHv2] Handle not explicitly zero terminated strings in merge sections

2018-10-05 Thread Andreas Schwab
On Sep 14 2018, Bernd Edlinger wrote: > diff -Npur gcc/testsuite/gnat.dg/string_merge1.adb > gcc/testsuite/gnat.dg/string_merge1.adb > --- gcc/testsuite/gnat.dg/string_merge1.adb 1970-01-01 01:00:00.0 > +0100 > +++ gcc/testsuite/gnat.dg/string_merge1.adb 2018-08-26 16:31:12.65027193

[PATCH v2, rs6000] 2/2 Add x86 SSE3 intrinsics to GCC PPC64LE target

2018-10-05 Thread Paul Clarke
This is part 2/2 for contributing PPC64LE support for X86 SSE3 instrisics. This patch includes testsuite/gcc.target tests for the intrinsics defined in pmmintrin.h. Tested on POWER8 ppc64le and ppc64 (-m64 and -m32, the latter only reporting 10 new unsupported tests.) [gcc/testsuite] 2018-10-01

libgo patch committed: Use inline assembler for xgetbv

2018-10-05 Thread Ian Lance Taylor
This patch by Than McIntosh uses inline assembler instead of the _xgetbv intrinsic, so that libgo can be built by compilers that don't support the intrinsic. Bootstrapped and ran Go testsuite on x86_64-pc-linux-gnu. Committed to mainline. Ian Index: gcc/go/gofrontend/MERGE ==

[PATCH, pdp11] remove -mfloat32, -mfloat64

2018-10-05 Thread Paul Koning
This patch removes switches that allow the size of "float" to be either the usual 4, or 8 -- which is also the size of "double". That second choice creates problems for Fortran and violates the Fortran standard. I don't see a reason for having the option; it certainly is not a familiar thing t

Re: [PATCH 2/2] Support string locations for C++ in -Wformat (PR c++/56856)

2018-10-05 Thread Jeff Law
On 10/4/18 9:00 AM, David Malcolm wrote: > -Wformat in the C++ FE doesn't work as well as it could: > (a) it doesn't report precise locations within the string literal, and > (b) it doesn't underline arguments for those arguments !CAN_HAVE_LOCATION_P, > despite having location wrapper nodes. > > F

Re: [PATCH 1/2] testsuite: multiline.exp: implement optional target/xfail selector

2018-10-05 Thread Jeff Law
On 10/4/18 9:00 AM, David Malcolm wrote: > Successfully regrtested on x86_64-pc-linux-gnu. > > OK for trunk? > > gcc/testsuite/ChangeLog: > * lib/multiline.exp (proc dg-end-multiline-output): Check argument > count. If there's a 3rd argument, use dg-process-target on it, > bail

[PATCH, i386]: Merge ftest insn patterns with FP compare insn patterns

2018-10-05 Thread Uros Bizjak
Now that we have universal "C" constraint, we can use it in FP compare insn patterns to merge ftest insn patterns. 2018-10-05 Uros Bizjak * config/i386/i386.md (*cmpxf_i387): Change operand 2 predicate to reg_or_0_operand. Add "C" constraint. (*cmpxf_cc_i387): Ditto. (*cmp_i38

Re: [PATCH, rs6000] 2/2 Add x86 SSE3 intrinsics to GCC PPC64LE target

2018-10-05 Thread Segher Boessenkool
On Fri, Oct 05, 2018 at 10:54:18AM -0500, Paul Clarke wrote: > On 10/05/2018 04:20 AM, Segher Boessenkool wrote: > >> @@ -0,0 +1,49 @@ > >> +/* { dg-do compile } */ > >> +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ > >> +/* { dg-options "-O3 -mdirect-move" } */ > > > > -mdirect-m

Re: [PATCH, GCC/ARM] Fix PR87374: ICE with -mslow-flash-data and -mword-relocations

2018-10-05 Thread Thomas Preudhomme
Hi Ramana and Kyrill, I've reworked the patch to add some documentation of the option conflict and reworked the -mword-relocation logic slightly to set the variable explicitely in PIC mode rather than test for PIC and word relocation everywhere. ChangeLog entries are now as follows: *** gcc/Chan

[PATCH, i386]: Do not depend "C" constraint on TARGET_SSE

2018-10-05 Thread Uros Bizjak
This constraint is used in move patterns which do not depend on TARGET_SSE. Also, rename "vector_move_operand" to "nonimm_or_0_operand". 2018-10-05 Uros Bizjak * config/i386/constraints.md ("C"): Do not depend on TARGET_SSE. * config/i386/predicates.md (nonimm_or_0_operand): Rename

Re: [PATCH] RISC-V: Fix unordered float compare for Signaling NaN.

2018-10-05 Thread Jim Wilson
On Wed, Oct 3, 2018 at 11:37 AM Jim Wilson wrote: > Thanks. I see that the rs6000.md port has a pattern that checks > HONOR_SNANS which looks like the right way to solve this problem. I > will try modifying Andrew's patch to use that and check against the > glibc testsuite. With a modified vers

Re: [PATCH 2/2 v3][IRA,LRA] Fix PR86939, IRA incorrectly creates an interference between a pseudo register and a hard register

2018-10-05 Thread Peter Bergner
On 10/4/18 3:01 PM, Vladimir Makarov wrote: > IMHO, the name copy_insn_p is too common and confusing (we already have > functions copy_insn and copy_insn_1 in GCC). The name does not reflect its > result meaning. I would call it something like non_conflict_copy_source_reg > although it is long.

Re: Don't ICE on vectors of enums (PR 87286)

2018-10-05 Thread Richard Biener
On October 5, 2018 2:48:24 PM GMT+02:00, Richard Sandiford wrote: >We've traditionally allowed vectors of enums (not sure if that's >deliberate) but vector_types_compatible_elements_p checked for >INTEGER_TYPE rather than INTEGRAL_TYPE_P. > >Tested on aarch64-linux-gnu. OK to install? OK. Ric

Re: introduce --enable-mingw-full32 to default to --large-address-aware

2018-10-05 Thread Joseph Myers
A new configure option needs documenting in install.texi. -- Joseph S. Myers jos...@codesourcery.com

Re: [PATCH, rs6000] 2/2 Add x86 SSE3 intrinsics to GCC PPC64LE target

2018-10-05 Thread Paul Clarke
On 10/05/2018 04:20 AM, Segher Boessenkool wrote: > On Tue, Oct 02, 2018 at 09:12:07AM -0500, Paul Clarke wrote: >> This is part 2/2 for contributing PPC64LE support for X86 SSE3 >> instrisics. This patch includes testsuite/gcc.target tests for the >> intrinsics defined in pmmintrin.h. >> >> Teste

libgo patch committed: Remove checkgoarm function

2018-10-05 Thread Ian Lance Taylor
The checkgoarm function in libgo's runtime package is never called, and the whole point of that function is to verify a goarm variable that libgo never sets it. This patch removes the function. Committed to mainline. Ian Index: gcc/go/gofrontend/MERGE

Re: [C++ Patch] PR 71128 ("[concepts] ICE on ill-formed explicit instantiation of a function concept")

2018-10-05 Thread Jason Merrill
OK. On Fri, Oct 5, 2018 at 10:07 AM Paolo Carlini wrote: > > Hi, > > another simple issue: here we ICE at the beginning of instantiate_decl > when we try to explicitly instantiate a concept. Tested x86_64-linux. > > Thanks, Paolo. > > / >

libbacktrace patch committed: backtrace_create_state should be called once

2018-10-05 Thread Ian Lance Taylor
This patch to libbacktrace expands the comment for backtrace_create_state to make clear that it should be called only once. There is no backtrace_free_state function. While it would be nice to have such a function, it's hard to write completely accurately as libbacktrace doesn't currently track a

[C++ Patch] PR 71128 ("[concepts] ICE on ill-formed explicit instantiation of a function concept")

2018-10-05 Thread Paolo Carlini
Hi, another simple issue: here we ICE at the beginning of instantiate_decl when we try to explicitly instantiate a concept. Tested x86_64-linux. Thanks, Paolo. / /cp 2018-10-05 Paolo Carlini PR c++/71128 * pt.c (do_decl_instantiation): Per 12.6.8/5, a

Re: [patch] various OpenACC reduction enhancements - ME and nvptx changes

2018-10-05 Thread Tom de Vries
On 6/29/18 8:19 PM, Cesar Philippidis wrote: > The attached patch includes the nvptx and GCC ME reductions enhancements. > > Is this patch OK for trunk? It bootstrapped / regression tested cleanly > for x86_64 with nvptx offloading. > These need fixing: ... === ERROR type #5: trailing whitespace

Re: [PATCH, OpenACC] Add support for gang local storage allocation in shared memory

2018-10-05 Thread Tom de Vries
On 8/16/18 5:46 PM, Julian Brown wrote: > On Wed, 15 Aug 2018 21:56:54 +0200 > Bernhard Reutner-Fischer wrote: > >> On 15 August 2018 18:46:37 CEST, Julian Brown >> wrote: >>> On Mon, 13 Aug 2018 12:06:21 -0700 >>> Cesar Philippidis wrote: >> >> atttribute has more t than strictly necessary.

Re: [PATCH 6/6, OpenACC, libgomp] Async re-work, nvptx changes

2018-10-05 Thread Tom de Vries
On 9/25/18 3:11 PM, Chung-Lin Tang wrote: > Hi Tom, > this patch removes large portions of plugin/plugin-nvptx.c, since a lot > of it is > now in oacc-async.c now. Yay! > The new code is essentially a > NVPTX/CUDA-specific implementation > of the new-style goacc_asyncqueues. > > Also, some neede

Re: [PATCH 2/4] Remove unused functions and fields.

2018-10-05 Thread Martin Liška
On 10/5/18 12:43 AM, Bernhard Reutner-Fischer wrote: > Hi! > > So i just added archive handling to ease looking at more than just the > plain frontends, applied as r264856. Running the tools for cc1 does not show anything. Please update the comment in the script with example invocation. > > You

Don't ICE on vectors of enums (PR 87286)

2018-10-05 Thread Richard Sandiford
We've traditionally allowed vectors of enums (not sure if that's deliberate) but vector_types_compatible_elements_p checked for INTEGER_TYPE rather than INTEGRAL_TYPE_P. Tested on aarch64-linux-gnu. OK to install? Richard 2018-10-05 Richard Sandiford gcc/c-family/ PR c/87286

Re: [patch] nvptx libgcc atomic routines

2018-10-05 Thread Tom de Vries
On 9/26/18 8:33 PM, Cesar Philippidis wrote: > This patch adds nvptx support for the atomic FETCH_AND_OP functions. I > recall that this used to be important for OpenACC reductions back in the > GCC 5.0 days before Nathan split reductions into four phases. Nowadays, > atomic reductions use a spin l

[PATCH][GCC][DOC] Relocate list under Deprecated in options.texi to Var

2018-10-05 Thread Sam Tebbs
Hi all, I recently found what seems to be an error in the options documentation (gcc/doc/options.texi) where a list describing how _var_ is set (referring to the Var attribute) is written beneath the _Deprecated_ attribute instead. This patch moves it to the correct location. gcc/doc 2018-05-10

Re: [PATCH] Optimize sin(atan(x)), take 2

2018-10-05 Thread Giuliano Augusto Faulin Belinassi
Thank you for the review. I will address all these issues :-). > Imagine a pause here while I lookup isolation of radicals It's been > a long time... OK. Sure. I see what you're doing here... Sorry, but I really did not understand your comment. Should I write a shorter comment for that f

Re: [PATCH][4/n] Remove BLOCK_ABSTRACT

2018-10-05 Thread Richard Biener
On Fri, 28 Sep 2018, Richard Biener wrote: > > It turns out that nobody sets this anymore (dwarf2out did with the > original code of outputting abstract instances, temporarily so IIRC). > > Bootstrap and regtest running on x86_64-unknown-linux-gnu. > > Any objection to purge it completely like

Re: [PATCH] i386: Use TImode for BLKmode values in 2 integer registers

2018-10-05 Thread H.J. Lu
On Sat, Sep 29, 2018 at 11:02 AM Uros Bizjak wrote: > > On Sat, Sep 29, 2018 at 6:36 PM H.J. Lu wrote: > > > > When passing and returning BLKmode values in 2 integer registers, use > > 1 TImode register instead of 2 DImode registers. Otherwise, V1TImode > > may be used to move and store such BLKm

Re: [PATCH][i386] Fix scalar costing in ix86_add_stmt_cost

2018-10-05 Thread Jan Hubicka
> > The following fixes bogus differences in scalar iteration cost > computed by the vectorizer when comparing 128 and 256 bit vectorizations. > This was caused by the hook looking at the vector types mode even > for kind == scalar_stmt and thus returning vector operation costs > for things like a

Re: [Patch, Aarch64] Fix testsuite regressions related to PR tree-optimization/71625

2018-10-05 Thread Richard Earnshaw (lists)
On 26/09/18 17:21, Steve Ellcey wrote: > A patch for PR tree-optimized/71625 caused regressions in the > gcc.target/aarch64/vclz.c and gcc.target/aarch64/vneg_s.c tests > because a couple of routines that were not getting inlined before > started getting inlined.  The inlining is not a bug, the  >

[PATCH] Fix PR63155 (again)

2018-10-05 Thread Richard Biener
This fixes yet another bottleneck in the SSA propagator where the way we process the worklists (in particular the BB one) causes excessive re-processing of PHI nodes. The following patch priorizes forward progress over iteration as that ensures the maximum set of possible backedges is executable

[PATCH] rs6000: Various fixes for the new fpscr builtins (PR87509)

2018-10-05 Thread Segher Boessenkool
With these fixes all testcases test clean for me, both on powerpc64-linux {-m32,-m64} and on powerpc64le-linux, with all relevant -mcpu= settings. Committing to trunk. The generated code (esp. for -m32) isn't optimal yet, but if we do not allow SImode in FPRs this isn't easy to solve. So first t

Re: [PATCH][RFC][i386] Change sminmax reduction patterns

2018-10-05 Thread Uros Bizjak
On Thu, Oct 4, 2018 at 2:05 PM Richard Biener wrote: > > > This tries to apply the same trick to sminmax reduction patterns > as for the reduc_plus_scal ones, namely reduce %zmm -> %ymm -> %xmm > first. On a microbenchmark this improves performance on Zen > by ~30% for AVX2 and on Skylake-SP by ~

Re: [patch] tighten toplevel guard on ibm-ldouble.c

2018-10-05 Thread Segher Boessenkool
Hi Olivier, On Wed, Oct 03, 2018 at 09:35:35PM +0200, Olivier Hainque wrote: > With a forthcoming micro cleanup patch to the 32bits powerpc-vxworks > port (arranging to define __powerpc__ in addition to a few others), > the port fails to build with: > > In file included from > ../../../../src

Re: [PATCH, rs6000] 2/2 Add x86 SSE3 intrinsics to GCC PPC64LE target

2018-10-05 Thread Segher Boessenkool
Hi! On Tue, Oct 02, 2018 at 09:12:07AM -0500, Paul Clarke wrote: > This is part 2/2 for contributing PPC64LE support for X86 SSE3 > instrisics. This patch includes testsuite/gcc.target tests for the > intrinsics defined in pmmintrin.h. > > Tested on POWER8 ppc64le and ppc64 (-m64 and -m32, the l

Re: [PATCH, rs6000] 1/2 Add x86 SSE3 intrinsics to GCC PPC64LE target

2018-10-05 Thread Segher Boessenkool
Hi Paul, On Tue, Oct 02, 2018 at 09:11:57AM -0500, Paul Clarke wrote: > This is a follow-on to earlier commits for adding compatibility > implementations of x86 intrinsics for PPC64LE. This is the first of > two patches. This patch adds 11 of the 13 x86 intrinsics from > ("SSE3"). (Patch 2/2 a

Re: [patch] Fix PR tree-optimization/86659

2018-10-05 Thread Eric Botcazou
> So I wonder why it is necessary to track 'reverse' in gimple_match_op > at all given we bail out without optimizing as far as I can see? Because of the valueization? If it is done, gimple_simplify returns true so the result will be synthetized from res_op by means of maybe_build_generic_op. Th

Re: #999 spurious error on derived record passed as Out parameter

2018-10-05 Thread Eric Botcazou
Sorry, wrong list... -- Eric Botcazou

#999 spurious error on derived record passed as Out parameter

2018-10-05 Thread Eric Botcazou
The error message is: p.adb:7:03: unconstrained subtype not allowed (need initialization) p.adb:7:03: provide initial value or explicit discriminant values p.adb:7:03: or give default discriminant values for type "Rec" and is issued by every compiler I tried. This doesn't happen if the parameter

Re: [PATCH] i386: Don't pass -msse2avx to assembler for -mavx

2018-10-05 Thread Uros Bizjak
On Fri, Oct 5, 2018 at 1:01 AM H.J. Lu wrote: > > > With > > gcc -O2 -fPIC -flto -g -c -o a.o a.c > gcc -O2 -fPIC -flto -g -mavx -c -o b.o b.c > gcc -shared -O2 -fPIC -flto -g -o lib1.so a.o b.o > > LTO correctly generates AVX for b.o and SSE for a.o. But the GCC driver > passes -msse2avx to as