Re: [PATCH][AArch64] Enable AES fusion with -mcpu=generic

On Thu, Mar 16, 2017 at 11:01 AM, Andrew Pinski wrote: > On Thu, Mar 16, 2017 at 10:22 AM, Wilco Dijkstra > wrote: >> Many supported cores implement fusion of AES instructions. When fusion >> happens it can give a significant performance gain. If not, scheduling >> fusion candidates next to ea

Re: [RFC][PATCH][AArch64] Improve generic branch cost

On Tue, Mar 14, 2017 at 2:37 AM, James Greenhalgh wrote: > I'd like to hear comments from the Exynos-M1, Falkor and > xgene-1 subtarget contributors, particularly as these targets use > generic_branch_costs for their subtarget-sepcific tuning. It may be that > your patch needs to preserve the 2,2

Re: [PR63238] output alignment debug information

>> This is OK so far, but the DW_AT_alignment attribute also needs to be >> added to the checksum computation in die_checksum and >> die_checksum_ordered. > > Thanks. I see what to do in die_checksum_ordered, but die_checksum? It > seems to handle attributes by value class, and AFAICT the classes

[PATCH 1/2] Port Doxygen support script from Perl to Python; add unittests

It's possible to run GCC's sources through Doxygen by setting INPUT_FILTER = contrib/filter_gcc_for_doxygen within contrib/gcc.doxy and invoking doxygen on the latter file. The script filters out various preprocessor constructs from GCC sources before Doxygen tries to parse them

[PATCH 2/2] filter_params.py: GTY fix and other cleanups

This patch updates the removal of GTY tags in the Doxygen support script so that it can cope with multiline tags, such as that for class symtab_node. It also makes some tweaks to regexes to make them more idiomatic for Python (and stripping some whitespace). Tested via unit test suite, and by run

Patch RFC: 32-bit x86: Fix regparm for -fsplit-stack with nested function

While working on a modification to libgo I ran into a bug with -fsplit-stack support for 32-bit x86. When a function has a stack frame more than 256 bytes, it needs a scratch register to add add the stack frame size to the stack pointer register. This happens at the very beginning of the function

Re: [PATCH] Install gcov-dump.

On 15.03.2017 14:49, Richard Biener wrote: > On March 15, 2017 11:19:24 AM GMT+01:00, "Martin Liška" > wrote: >> On 03/14/2017 06:31 PM, Matthias Klose wrote: >>> On 14.03.2017 15:15, Richard Biener wrote: On Tue, Mar 14, 2017 at 1:30 PM, Martin Liška >> wrote: > Tested on my local mach

C++ PATCH to update __cplusplus for C++17

This is the value discussed at the Kona meeting. commit 6a8c9d106fd69e2aa0dd54fe856b7083d7988c7e Author: Jason Merrill Date: Thu Mar 16 13:06:48 2017 -0400 * init.c (cpp_init_builtins): Update __cplusplus for C++17. diff --git a/libcpp/init.c b/libcpp/init.c index 0679b7f..1477673

Re: C++ PATCH for c++/79797, ICE with array NSDMI

On Wed, Mar 8, 2017 at 8:00 PM, Jason Merrill wrote: > In this testcase, ctx->object was the array subobject and 'this' > refers to the containing object, so we failed. Fixed by generalizing > PLACEHOLDER_EXPR handling more (in a way that replace_placeholders_r > already handles). A slight tweak

Re: [PATCH] Define std::byte for C++17 (P0298R3)

On Thu, Mar 9, 2017 at 10:47 AM, Jonathan Wakely wrote: > This is a new type for C++17, with no impact on anything in non-C++17 > dialects. This is intentionally only defined in and not > . And this patch adds the aliasing semantics: Tested x86_64-pc-linux-gnu, applying to trunk. commit cc516c1

Re: [PATCH rs6000] Fix PR79951, ICE for unrecognizable insn with -mno-cmpb

On Wed, Mar 15, 2017 at 06:09:57PM -0500, Pat Haugen wrote: > The define_expand for copysign3 will call > gen_copysign3_fcpsgn if either TARGET_CMPB || VECTOR_UNIT_VSX_P > (mode) are true, but gen_copysign3_fcpsgn is missing the > check of VECTOR_UNIT_VSX_P (mode) which results in an > unrecognizab

Re: [PATCH], PR target/71294, Fix compiler segfault for reload & power8

Hi Mike, On Wed, Mar 15, 2017 at 06:31:12PM -0400, Michael Meissner wrote: > This patch is a simpler approach to fixing PR 71294, then I proposed last > year. Much simpler! Thank you. > I have built compilers on a little endian Power8 system (64-bit only), big > endian Power8 system (64-bit on

Re: [PATCH] Fix tree-prof/pr66295.c

On 03/15/2017 09:59 PM, Segher Boessenkool wrote: This testcase can only ever be built on x86 (it needs the "avx*" attributes). This patch skips the test elsewhere. Is this okay for trunk? Ok. Bernd

[PATCH 4/5 ][P1] [PR tree-optimization/71437] Use a dominator order walk rather than random for VRP threading

This is patch #4 in the kit for solving 71437. This turns the random walk of edges for threading from VRP into a dominator walk. It became clear very quickly in that work that DOM and VRP were going to have duplicated code with this change. That duplicated code was refactored and pushed do

[PATCH 3/5][P1][tree-optimization/71437] Remove ASSERT_EXPR handling from core of threader

For reference the ppc64 bootstrap & regression testing of patches #1 and #2 turned up no issues. This patch removes ASSERT_EXPR handling from the core of the jump threader. 10+ years after its introduction it's painfully obvious "handle_dominating_asserts" was a bad idea. The good news i

Re: [PATCH C++] document order of C++ ctors and attribute constructor is unspecified

On Thu, Mar 16, 2017 at 11:22 AM, Martin Sebor wrote: > On 03/15/2017 10:49 PM, Jason Merrill wrote: >> >> On Wed, Mar 15, 2017 at 6:59 PM, Martin Sebor wrote: >>> >>> In bug 52477 - Wrong initialization order? attribute constructor >>> vs static data access, the reporter expects C++ objects wit

Re: [PATCH][AArch64] Enable AES fusion with -mcpu=generic

On Thu, Mar 16, 2017 at 10:22 AM, Wilco Dijkstra wrote: > Many supported cores implement fusion of AES instructions. When fusion > happens it can give a significant performance gain. If not, scheduling > fusion candidates next to each other has almost no effect on performance. > Due to the high

Re: [PATCH] Various fixes for facets

On 16/03/17 15:23 +, Jonathan Wakely wrote: On 14/03/17 18:46 +, Jonathan Wakely wrote: On 13/03/17 19:35 +, Jonathan Wakely wrote: This is a series of patches to fix various bugs in the Unicode character conversion facets. Ther first patch fixes a silly < versus <= bug that meant

[PATCH][AArch64] Enable AES fusion with -mcpu=generic

Many supported cores implement fusion of AES instructions. When fusion happens it can give a significant performance gain. If not, scheduling fusion candidates next to each other has almost no effect on performance. Due to the high benefit/low cost it makes sense to enable AES fusion with -mcpu=g

Re: [PR 77333] Fix fntypes of calls calling clones

Hi, On Mon, Mar 13, 2017 at 01:46:47PM +0100, Richard Biener wrote: > On Fri, 10 Mar 2017, Martin Jambor wrote: > > > Hi, > > > > PR 77333 is a i686-windows target bug, which however has its root in > > our general mechanism of adjusting gimple statements when redirecting > > call graph edge. B

Re: [PATCH 2/5][P1][tree-optimization/71437] Record more equivalences in some cases

On Thu, 16 Mar 2017, Jeff Law wrote: On 03/16/2017 06:54 AM, Trevor Saunders wrote: + if (TREE_CODE (op0) == SSA_NAME && integer_zerop (op1)) + { + enum tree_code code = eq->cond.ops.binary.op; + if ((code == EQ_EXPR && eq->value == boolean_true_node) +

Re: [PATCH] Various fixes for facets

On 14/03/17 18:46 +, Jonathan Wakely wrote: On 13/03/17 19:35 +, Jonathan Wakely wrote: This is a series of patches to fix various bugs in the Unicode character conversion facets. Ther first patch fixes a silly < versus <= bug that meant that 0x got written as a surrogate pair inste

Re: [PATCH 2/5][P1][tree-optimization/71437] Record more equivalences in some cases

On Thu, Mar 16, 2017 at 09:03:43AM -0600, Jeff Law wrote: > On 03/16/2017 06:54 AM, Trevor Saunders wrote: > > > + if (TREE_CODE (op0) == SSA_NAME && integer_zerop (op1)) > > > + { > > > + enum tree_code code = eq->cond.ops.binary.op; > > > + if ((code == EQ_EXPR && eq->value == b

Re: [PATCH C++] document order of C++ ctors and attribute constructor is unspecified

On 03/15/2017 10:49 PM, Jason Merrill wrote: On Wed, Mar 15, 2017 at 6:59 PM, Martin Sebor wrote: In bug 52477 - Wrong initialization order? attribute constructor vs static data access, the reporter expects C++ objects with static storage duration to have their ctors called in the same order a

Re: [PATCH 2/5][P1][tree-optimization/71437] Record more equivalences in some cases

On 03/16/2017 06:54 AM, Trevor Saunders wrote: + if (TREE_CODE (op0) == SSA_NAME && integer_zerop (op1)) + { + enum tree_code code = eq->cond.ops.binary.op; + if ((code == EQ_EXPR && eq->value == boolean_true_node) + || (code == NE_EXPR &&

[PATCH] PR libstdc++/67440 make pretty printers work with GDB 7.6 again

The gdb.Type.name attribute was only added in GDB 7.7, so several printer tests fail on older GDB versions. Since all we need is to strip cv-qualifiers we can use gdb.Type.unqualified() for that. PR libstdc++/67440 * python/libstdcxx/v6/printers.py (find_type): Avoid gdb.Type.name

Re: [gomp4] backport misc OMP 4.5 changes from trunk

Hi Cesar! On Wed, 15 Mar 2017 07:21:26 -0700, Cesar Philippidis wrote: > This patch backports Jakub's Fortran OMP 4.5 changes to gomp-4_0-branch. > The original patch may be found here > . I've applied > it to gomp-4_0-branch. Thanks! A

Re: [PATCH] Remove dead stores and initializations

On 2017.03.16 at 14:40 +0100, Bernd Schmidt wrote: > On 03/16/2017 01:31 PM, Markus Trippelsdorf wrote: > > clang --analyze pointed out a number of dead stores and initializations. > > > > Tested on ppc64le. Ok for trunk? > > I'd say - not now. > > Ideally someone would delve into the commit his

Re: [PATCH, GCC/LTO, ping2] Fix PR69866: LTO with def for weak alias in regular object file

Ping? Is this ok for stage4? Best regards, Thomas On 09/03/17 09:43, Thomas Preudhomme wrote: Ping? Best regards, Thomas On 02/03/17 14:51, Thomas Preudhomme wrote: Hi, This patch fixes an assert failure when linking one LTOed object file having a weak alias with a regular object file co

Re: RFC: PR libstdc++/80064 make heap algorithms work with function types

On 16/03/17 15:31 +0200, Ville Voutilainen wrote: All in all it seems to some extent reasonable to me to allow such code. It seems rather easy to fail to provide a function pointer as the comparator type, but also rather easy for the implementation to not mind that. I do find it suspicious that a

Re: [PATCH] Remove dead stores and initializations

On 03/16/2017 01:31 PM, Markus Trippelsdorf wrote: clang --analyze pointed out a number of dead stores and initializations. Tested on ppc64le. Ok for trunk? I'd say - not now. Ideally someone would delve into the commit history to figure out what happened with each of these, and whether any

Re: RFC: PR libstdc++/80064 make heap algorithms work with function types

On 16 March 2017 at 15:02, Jonathan Wakely wrote: > Richi reported a GCC 7 regression for a testcase from Cython that > boils down to: > > void > test01(int* first, int* last) > { > extern bool cmp(int, int); > // PR libstdc++/80064 > // This is undefined, because [alg.sorting] requires the tem

RFC: PR libstdc++/80064 make heap algorithms work with function types

Richi reported a GCC 7 regression for a testcase from Cython that boils down to: void test01(int* first, int* last) { extern bool cmp(int, int); // PR libstdc++/80064 // This is undefined, because [alg.sorting] requires the template argument // Compare to be a function object type, and bool(i

Re: [PATCH 2/5][P1][tree-optimization/71437] Record more equivalences in some cases

On Wed, Mar 15, 2017 at 09:18:27PM -0600, Jeff Law wrote: > On 03/15/2017 09:17 PM, Jeff Law wrote: > > > > Patch #3 will remove handle_dominating_asserts from the core of the jump > > threading code and push it into VRP's callbacks where it should always > > have been. > > > > As a side effect i

[PATCH] Remove dead stores and initializations

clang --analyze pointed out a number of dead stores and initializations. Tested on ppc64le. Ok for trunk? Thanks. gcc/c-family/ChangeLog: * c-ada-spec.c (to_ada_name): Remove dead store. gcc/c/ChangeLog: * c-array-notation.c (build_array_notation_expr): Remove dead stores.

RE: [PATCH][GCC][AArch64] Fix incorrect INS in SIMD mov pattern

> This isn't technically a regression, but the bug would be subtle enough, and > hard enough to debug that I think we should fix it for GCC 7. > > OK for trunk, where else does this need backported to? > I think it might be worthwhile to backport to GCC 6 as well. Tamar > Thanks, > James > >

[PATCH][AArch64] Allow CMP+SHIFT when comparing with zero

Hi all The backend pattern for combining a CMP+SHIFT was missing out on a case when comparing with zero. This was happening because aarch64_select_cc_mode (SELECT_CC_MODE) was not returning the correct mode (in this case CC_SWP) which was needed to identify the combine. This patch adds this mis

[PATCH] [ARM] Cleanup macro TARGET_EITHER

Hi all This is a cleanup patch to remove the macro TARGET_EITHER. This macro seems to have become irrelevant in recent times since its previous definition had been commented out and replaced with 1. Bootstrapped and tested on arm-none-linux-gnueabihf. Sudi 2017-03-10 Sudakshina Das

Re: [PATCH][AArch64] Use 'x' constraint for vector HFmode multiplication by indexed element instructions

Hi Christophe, On 16/03/17 09:54, Christophe Lyon wrote: On 16 March 2017 at 10:29, Kyrill Tkachov wrote: Hi all, The advsimd-intrinsics.exp tests for the fmul and fmulx instructions that perform a multiplication by indexed element have started generating invalid assembly in my testing. For e

Re: [PATCH][AArch64] Use 'x' constraint for vector HFmode multiplication by indexed element instructions

On 16 March 2017 at 10:29, Kyrill Tkachov wrote: > Hi all, > > The advsimd-intrinsics.exp tests for the fmul and fmulx instructions that > perform a multiplication by indexed element > have started generating invalid assembly in my testing. For example: > Error: register number out of range 0 to 1

Re: [PATCH][AArch64] Use 'x' constraint for vector HFmode multiplication by indexed element instructions

On Thu, Mar 16, 2017 at 09:29:52AM +, Kyrill Tkachov wrote: > Hi all, > > The advsimd-intrinsics.exp tests for the fmul and fmulx instructions that > perform a multiplication by indexed element have started generating invalid > assembly in my testing. For example: > Error: register number out

[PATCH][AArch64] Use 'x' constraint for vector HFmode multiplication by indexed element instructions

Hi all, The advsimd-intrinsics.exp tests for the fmul and fmulx instructions that perform a multiplication by indexed element have started generating invalid assembly in my testing. For example: Error: register number out of range 0 to 15 at operand 3 -- `fmulx v24.8h,v23.8h,v22.h[0]' The prob