Re: [RFC] fix bootstrap on aarch64-*-freebsd and probably others

On 19.01.17 00:33, Jeff Law wrote: On 01/18/2017 11:43 AM, Andreas Tobler wrote: Hi all, I have the following issue here on aarch64-*-freebsd: (sorry if the format is hardly readable) .. /export/devel/net/src/gcc/head/gcc/gcc/config/aarch64/aarch64.c: In function 'void aarch64_elf_asm_des

Re: [PATCH] Introduce --with-gcc-major-version-only configure option

Just one suggestion: What about configure option like --with-version-convert where one could specify actual conversion? I have used conversion sed -e 's:\.::2g' for DJGPP to leave only the first dot in version for complying with MS-DOS file name restrictions. The implementation of that was not

[RFC][PATCH][PR 67336][PING] Verify pointers during stack unwind

Hi all, Libgcc unwinder currently does not do any verification of pointers which it chases on stack. In practice this not so rarely causes segfaults when unwinding on corrupted stacks (e.g. when when trying to print diagnostic on fatal error) [1]. Ironically this usually happens in error reporting

Re: [PATCH, rs6000] Fix PR78516, broken spe.md constraints exposed by LRA.

On 1/18/17 8:04 PM, Segher Boessenkool wrote: On Wed, Jan 18, 2017 at 02:38:30PM -0600, Peter Bergner wrote: Is this ok for trunk? This looks good, please apply. Thanks, Thanks, committed as revision 244609. Peter

Re: [PATCH, rs6000] Fix PR78516, broken spe.md constraints exposed by LRA.

On Wed, Jan 18, 2017 at 02:38:30PM -0600, Peter Bergner wrote: > This is a partial patch for PR78516. This patch fixes some broken constraints > in spe.md that were exposed by the rs6000 port's switch to using LRA. > In order to change some of the constraints to outputs from inout, I had > to chan

Re: [PATCH, GCC/x86 mingw32] Add configure option to force wildcard behavior on Windows

On 01/18/2017 09:48 AM, Thomas Preudhomme wrote: > By default, wildcard support on Windows for programs compiled with mingw > depends on how the mingw runtime was configured. This means if one wants > to build GCC for Windows with a consistent behavior with Wildcard > (enabled or disabled) the ming

[PATCH], PowerPC ISA 3.0 defaults + IEEE 128-bit floating point test

This patch changes the default options enabled for the PowerPC -mcpu=power9 option to include the undocumented -mpower9-minmax option. This option enables MIN/MAX instructions that do not require -ffast-math or -fhonor-nans. I also changed the minimum option requirements for IEEE 128-bit floating

Re: [PATCH, rs6000] Update some Power9 latencies

On Wed, Jan 18, 2017 at 12:34:00PM -0600, Pat Haugen wrote: > The following patch updates a few latencies in the Power9 machine > description. Bootstrap/regtest on powerpc64le with no new regressions. Ok for > trunk? Okay, thanks! Segher > 2017-01-18 Pat Haugen > > * config/rs6000/

Re: [RFC] fix bootstrap on aarch64-*-freebsd and probably others

On 01/18/2017 11:43 AM, Andreas Tobler wrote: Hi all, I have the following issue here on aarch64-*-freebsd: (sorry if the format is hardly readable) .. /export/devel/net/src/gcc/head/gcc/gcc/config/aarch64/aarch64.c: In function 'void aarch64_elf_asm_destructor(rtx, int)': /export/devel/ne

Re: [PATCH, MIPS] Target flag and build option to disable indexed memory OPs.

On 01/17/2017 05:41 AM, Moore, Catherine wrote: > > >> -Original Message- >> From: Matthew Fortune [mailto:matthew.fort...@imgtec.com] >> Sent: Tuesday, January 17, 2017 4:35 AM >> ... >> Thanks for the comments. >> >> Having thought further I agree we can safely ignore DSP indexed load >

[PATCH, rs6000, committed] Fix "type" attribute for vbpermq instruction

Hi, Pat Haugen pointed out that the vbpermq instruction should preferably have its "type" attribute set to vecperm, rather than vecsimple. This patch makes that change. Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no regressions, committed as obvious. Thanks, Bill 2017-01-18

[PATCH, rs6000, committed] Fix PR79040 (built-in typo)

Hi, A previous patch mistakenly added a #define of vec_cntlz which should have been a #define of vec_cnttz. This patch fixes that. Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no regressions, committed as obvious. Thanks, Bill 2017-01-18 Bill Schmidt PR target/790

Re: [PATCH] Fix IPA CP where it forgot to add a reference in cgraph

> > 2016-12-19 Martin Liska > > * cgraphclones.c (cgraph_node::create_virtual_clone): > Create either IPA_REF_LOAD of IPA_REF_READ depending on > whether new_tree is a VAR_DECL or an ADDR_EXPR. > * ipa-cp.c (create_specialized_node): Add reference just for > ADDR_

Re: [committed] libitm: Disable TSX on processors on which it may be broken.

On Wed, Jan 18, 2017 at 10:48 PM, Uros Bizjak wrote: > Hello! > >> This fix follows the same approach that glibc uses to disable TSX on >> processors on which it is broken. TSX can also be disabled through a >> microcode update on these processors, but glibc consensus is that it >> cannot be dete

Re: [PATCH] Allow building GCC with PTX offloading even without CUDA being installed (gcc and nvptx-tools patches)

On Wed, Jan 18, 2017 at 10:52:32PM +0300, Alexander Monakov wrote: > Sorry for not noticing this earlier, but ... > > > +#ifdef __LP64__ > > +typedef unsigned long long CUdeviceptr; > > +#else > > +typedef unsigned CUdeviceptr; > > +#endif > > I think this #ifdef doesn't do the right thing on Min

Re: [committed] libitm: Disable TSX on processors on which it may be broken.

On Wed, Jan 18, 2017 at 10:48:28PM +0100, Uros Bizjak wrote: > Hello! > > > This fix follows the same approach that glibc uses to disable TSX on > > processors on which it is broken. TSX can also be disabled through a > > microcode update on these processors, but glibc consensus is that it > > ca

[PATCH] C++: fix fix-it hints for misspellings within explicit namespaces (v2)

On Sat, 2017-01-14 at 09:50 -0500, Jason Merrill wrote: > On Fri, Jan 13, 2017 at 5:05 PM, David Malcolm > wrote: > > On Wed, 2017-01-04 at 14:58 -0500, Jason Merrill wrote: > > > On Tue, Jan 3, 2017 at 8:28 PM, David Malcolm < > > > dmalc...@redhat.com> > > > wrote: > > > > PR c++/77829 and PR c+

Re: [committed] libitm: Disable TSX on processors on which it may be broken.

On Wed, Jan 18, 2017 at 10:48 PM, Uros Bizjak wrote: > Hello! > >> This fix follows the same approach that glibc uses to disable TSX on >> processors on which it is broken. TSX can also be disabled through a >> microcode update on these processors, but glibc consensus is that it >> cannot be dete

Re: [PATCH] [ARC] Clean up arc header file.

On 18/01/2017 18:43, Andrew Burgess wrote: * Mike Stump [2017-01-17 10:49:30 -0800]: On Jan 17, 2017, at 3:30 AM, Andrew Burgess wrote: This patch revamps the arc's header file by means of using separate headers for different tool targets. Each target header file holds the specific compile

Re: [committed] libitm: Disable TSX on processors on which it may be broken.

Hello! > This fix follows the same approach that glibc uses to disable TSX on > processors on which it is broken. TSX can also be disabled through a > microcode update on these processors, but glibc consensus is that it > cannot be detected reliably whether the microcode update has been > applied

Fortran, committed: Forall-with-temporary problems(pr 50069 and pr 55086).

Fixed in revision 244601.

Re: [PATCH] Add AVX512 k-mask intrinsics

On Wed, Jan 18, 2017 at 1:45 PM, Andrew Senkevich wrote: > 2017-01-17 16:51 GMT+03:00 Jakub Jelinek : >> On Tue, Jan 17, 2017 at 04:03:08PM +0300, Andrew Senkevich wrote: >>> > I've played a bit w/ SDE. And looks like operands are not early clobber: >>> > TID0: INS 0x004003ee A

[committed] Implement LANG_HOOKS_TYPE_FOR_SIZE for jit

The jit testcase test-nested-loops.c was crashing. Root cause is that deep inside loop optimization we're now exposing this call within fold-const.c which wasn't being hit before: 4082 /* Compute the mask to access the bitfield. */ 4083 unsigned_type = lang_hooks.types.type_for_size (*

Re: [expand] Fix for PR rtl-optimization/79121 incorrect expansion of extend plus left shift

On 01/18/2017 11:08 AM, Richard Earnshaw (lists) wrote: PR 79121 is a silent wrong code regression where, when generating a shift from an extended value moving from one to two machine registers, the type of the right shift is for the most significant word should be determined by the signedness of

C++ PATCH for c++/68666 (member variable template)

The problem was that finish_class_member_access_expr got missed when we added variable templates. 68666 is a report of how this affects concepts; the patch adds both concepts and non-concepts testcases. Tested x86_64-pc-linux-gnu, applying to trunk. commit 40ab19fcedf621438a819dbdf08d9ee66e3143db

[committed] jit.dg: fix issue with compilation of test-threads.c

DejaGnu's provides decls of various inline functions, of which the jit testsuite uses "pass", "fail" and "note". The jit testcase test-threads.c jumps through some hoops to make these functions threadsafe, using macros to rename the implementation in dejagnu.h, giving them a "dejagnu_" prefix, th

[PATCH, rs6000] Fix PR78516, broken spe.md constraints exposed by LRA.

This is a partial patch for PR78516. This patch fixes some broken constraints in spe.md that were exposed by the rs6000 port's switch to using LRA. In order to change some of the constraints to outputs from inout, I had to change some of the instructions we emit to equivalent forms. Joseph has sa

[committed] libitm: Disable TSX on processors on which it may be broken.

This fix follows the same approach that glibc uses to disable TSX on processors on which it is broken. TSX can also be disabled through a microcode update on these processors, but glibc consensus is that it cannot be detected reliably whether the microcode update has been applied. Thus, we just l

Re: [PATCH] Allow building GCC with PTX offloading even without CUDA being installed (gcc and nvptx-tools patches)

Hello Jakub, Sorry for not noticing this earlier, but ... > +#ifdef __LP64__ > +typedef unsigned long long CUdeviceptr; > +#else > +typedef unsigned CUdeviceptr; > +#endif I think this #ifdef doesn't do the right thing on MinGW. Would it be fine to simplify it? In my code I have typedef uint

[PATCH, i386]: (Partially) fix PR78952, Combine does not convert 8-bit sign-extract to a zero-extract

As suggested by Segher, we have to use code iterator to iterate RTX pattern through zero- and sign-extract for 8 bit inserts. In a similar way, we can use any_shiftrt in a RTX pattern involving 8-bit inserts. While it would be nice to have a middle-end perform relevant simplifications, these two p

[PATCH] fix 78488, ICE with inherited ctor

This patch fixes an ICE with inherited default ctor and a local decl. In such a case we don't have any conv args (just the object expression, handled differently). Thus 'num_convs-1' is -1 and we seg fault at: cand->convs[cand->num_convs-1]->ellipsis_p do just check it's non-zero first. commi

Re: transaction_safe exceptions prevent libstdc++ building for some targets

Joe Seymour writes: >> the msp430 -mlarge multilib failing to build with... >>> configure: error: Unknown underlying type for size_t >>> make[1]: *** [configure-target-libstdc++-v3] Error 1 > > This is still reproducible. FYI the underlying type is uint20_t I think I've complained that libstdc++

Re: transaction_safe exceptions prevent libstdc++ building for some targets

On 17/08/2016 12:19, Joe Seymour wrote: > fail to build with... > >> ../../../../../libstdc++-v3/src/c++11/cow-stdexcept.cc:274:3: error: static >> assertion failed: Pointers must be 32 bits or 64 bits wide >> static_assert(sizeof(uint64_t) == sizeof(void*) > > The assert fails because msp430 h

Re: [PATCH], Add support for PowerPC ISA 3.0 vector byte reverse instructions

On Wed, Jan 18, 2017 at 11:21:40AM -0600, Segher Boessenkool wrote: > On Tue, Jan 17, 2017 at 08:50:08PM -0500, Michael Meissner wrote: > > I have checked this on a little endian power8 system (64-bit only), a big > > endian power8 system (64-bit only), and a big endian power7 system (both > > 32-

Re: [PATCH, Fortran, sync_alloc, v1] [Coarray] Do not add sync all call when allocating allocatable/pointer component

Hi Jerry, and also for this many thanks. Committed as r244590. Regards, Andre PS: Hopefully this mail is not declared SPAM by the mail-host like the last one. On Wed, 18 Jan 2017 10:13:10 -0800 Jerry DeLisle wrote: > On 01/18/2017 08:54 AM, Andre Vehreschild wrote: > > Hi all, > > >

[RFC] fix bootstrap on aarch64-*-freebsd and probably others

Hi all, I have the following issue here on aarch64-*-freebsd: (sorry if the format is hardly readable) .. /export/devel/net/src/gcc/head/gcc/gcc/config/aarch64/aarch64.c: In function 'void aarch64_elf_asm_destructor(rtx, int)': /export/devel/net/src/gcc/head/gcc/gcc/config/aarch64/aarch64.

[PATCH] PR69301 don't assume atomic can default construct T

This fixes an invalid assumption that std::atomic can default construct a T. It also fixes some variables called "tmp" with non-uglified names. PR libstdc++/69301 * include/std/atomic (atomic::load, atomic::exchange): Use aligned buffer instead of default-initialized varia

Re: [PATCH, Fortran, pr70696, v2] [Coarray] ICE on EVENT POST of host-associated EVENT_TYPE coarray

Hi Jerry, thanks for the fast review. Committed as r244587. Regards, Andre On Wed, 18 Jan 2017 09:38:40 -0800 Jerry DeLisle wrote: > On 01/18/2017 04:26 AM, Andre Vehreschild wrote: > > Hi all, > > > > the patch I proposed for this pr unfortunately did not catch all errors. > > Dominiq

[PATCH, rs6000] Update some Power9 latencies

The following patch updates a few latencies in the Power9 machine description. Bootstrap/regtest on powerpc64le with no new regressions. Ok for trunk? -Pat 2017-01-18 Pat Haugen * config/rs6000/power9.md (power9-alu): Remove 'cmp' type and add define_bypass for CR latency.

[PR c++/78469] default ctor makes dtor required

Jason, I've figured out what's happening here. Just not sure of the most prudent way to fix it. struct no_destr { no_destr() = default; protected: ~no_destr() = default; }; void *Foo () { return new no_destr (); } no_destr is a type for which the default ctor is not DECL_ARTIFICIAL,

Re: [PATCH, Fortran, sync_alloc, v1] [Coarray] Do not add sync all call when allocating allocatable/pointer component

On 01/18/2017 08:54 AM, Andre Vehreschild wrote: Hi all, during discussing some other functionality in the caf-library, it occurred to me that gfortran is adding a caf_sync_all()-call when allocating only allocatable or pointer components of derived typed coarrays. The attached patch fixes the b

Re: [PATCH, Fortran, documentation, v1] [COARRAY][API-DOC] Fix documentation of coarray API functions

On 01/18/2017 06:46 AM, Andre Vehreschild wrote: Hi all, this patch adds undocumented parameters to caf-API functions and fixes the documentation style in many parts of the caf-API functions. It intentionally does not fix the last paragraph in the caf-API function's section (co_reduce), because

[expand] Fix for PR rtl-optimization/79121 incorrect expansion of extend plus left shift

PR 79121 is a silent wrong code regression where, when generating a shift from an extended value moving from one to two machine registers, the type of the right shift is for the most significant word should be determined by the signedness of the inner type, not the signedness of the result type. g

Re: [PATCH] avoid calling memset et al. with excessively large sizes (PR 79095)

On 01/18/2017 01:10 AM, Jakub Jelinek wrote: On Tue, Jan 17, 2017 at 10:59:43PM -0700, Jeff Law wrote: I agree that breaking those applications would be bad. It could be dealt with by adding an option to let them disable the insertion of the trap. With the warning, programmers would get a head

Re: [PATCH][PR lto/79061] Fix LTO plus ASAN fails with "AddressSanitizer: initialization-order-fiasco".

On January 18, 2017 5:17:12 PM GMT+01:00, Maxim Ostapenko wrote: >On 18/01/17 16:00, Richard Biener wrote: >> On Wed, 18 Jan 2017, Maxim Ostapenko wrote: >> >>> Hi, >>> >>> as was figured out in PR LTO + ASan raises false initialization >order fiasco >>> alarm due to in LTO case main_input_filena

Re: [PATCH, Fortran, pr70696, v2] [Coarray] ICE on EVENT POST of host-associated EVENT_TYPE coarray

On 01/18/2017 04:26 AM, Andre Vehreschild wrote: Hi all, the patch I proposed for this pr unfortunately did not catch all errors. Dominique figured, that the original testcase was not resolved (thanks for that). This patch resolves the linker problem by putting the static token into the parent

Re: [PATCH 0/5] OpenMP/PTX: improve correctness in SIMD regions

On Wed, Jan 18, 2017 at 08:02:14PM +0300, Alexander Monakov wrote: > On Wed, 18 Jan 2017, Jakub Jelinek wrote: > > > It is, but I think my approach is compatible with inlining too (and has a > > > more > > > localized impact on the compiler). > > > > But your 2/5 patch disables inlining into the

Re: [PATCH], Add support for PowerPC ISA 3.0 vector byte reverse instructions

On Tue, Jan 17, 2017 at 08:50:08PM -0500, Michael Meissner wrote: > I have checked this on a little endian power8 system (64-bit only), a big > endian power8 system (64-bit only), and a big endian power7 system (both > 32-bit > and 64-bit), and there were no regressions. Can I check this into the

[PATCH] PR68925 don't use thread_local static for stateless object

PR libstdc++/68925 * include/experimental/random (randint): Use temporary instead of thread_local static. Tested powerpc64le-linux, committed to trunk. commit 71544b3d1abd1c9a2d47ef664ce696b750232e0f Author: Jonathan Wakely Date: Wed Jan 18 17:16:10 2017 + PR6

Re: [PATCH 9e] Update "startwith" logic for pass-skipping to handle __RTL functions

On Wed, 2017-01-18 at 09:36 -0700, Jeff Law wrote: > On 01/17/2017 02:28 AM, Richard Biener wrote: > > > > > > This feels somewhat different, but still a hack. > > > > > > I don't have strong suggestions on how to approach this, but what > > > we've got > > > here feels like a hack and one prone

[AArch64] Accelerate -fstack-protector through pointer authentication extension

NOTE, this approach however requires DWARF change as the original LR is signed, the binary needs new libgcc to make sure c++ eh works correctly. Given this acceleration already needs the user specify -mstack-protector-dialect=pauth which means the target platform largely should have install new l

[Ping~]Re: [5/5][libgcc] Runtime support for AArch64 return address signing (needs new target macros)

On 12/01/17 18:10, Jiong Wang wrote: On 06/01/17 11:47, Jiong Wang wrote: This is the update on libgcc unwinder support according to new DWARF proposal. As Joseph commented, duplication of unwind-dw2.c is not encouraged in libgcc, But from this patch, you can see there are a few places we need

Re: [PATCH][GCC][PATCHv3] Improve fpclassify w.r.t IEEE like numbers in GIMPLE.

On Wed, 18 Jan 2017, Joseph Myers wrote: > Generally, I don't see tests added that these new functions are correct > for float, double and long double, which would detect such issues if run > for a target with IBM long double. Specifically, I think gcc.dg/tg-tests.h should have tests added for

Re: [PATCH 0/5] OpenMP/PTX: improve correctness in SIMD regions

On Wed, 18 Jan 2017, Jakub Jelinek wrote: > > It is, but I think my approach is compatible with inlining too (and has a > > more > > localized impact on the compiler). > > But your 2/5 patch disables inlining into the SIMT regions. Or do you mean > the approach with some new IFN for the pointers

[PATCH, Fortran, sync_alloc, v1] [Coarray] Do not add sync all call when allocating allocatable/pointer component

Hi all, during discussing some other functionality in the caf-library, it occurred to me that gfortran is adding a caf_sync_all()-call when allocating only allocatable or pointer components of derived typed coarrays. The attached patch fixes the behavior. Bootstrapped and regtests ok on x86_64-li

C++ PATCH for c++/78894 (ICE with C++17 class deduction and default argument)

We were aborting in tsubst_copy due to finding an AGGR_INIT_EXPR because tsubst_decl thought we needed to instantiate the default arguments of the deduction guide because PRIMARY_TEMPLATE_P was false. Fixed by making a deduction guide its own primary template. Tested x86_64-pc-linux-gnu, applying

Re: [PATCH][GCC][PATCHv3] Improve fpclassify w.r.t IEEE like numbers in GIMPLE.

Also, I don't think the call to perform_ibm_extended_fixups in is_subnormal is correct. Subnormal for IBM long double is *not* the same as subnormal double high part. Likewise it's incorrect in is_normal as well. Generally, I don't see tests added that these new functions are correct for flo

Re: [PATCH][GCC][PATCHv3] Improve fpclassify w.r.t IEEE like numbers in GIMPLE.

Since the patch adds new built-in functions __builtin_issubnormal and __builtin_iszero, it also needs to update c-typeck.c:convert_arguments to make those functions remove excess precision. This is mentioned in the PRs 77925 and 77926 for addition of those functions (which as I noted in

Re: [PATCH] [ARC] Clean up arc header file.

* Mike Stump [2017-01-17 10:49:30 -0800]: > On Jan 17, 2017, at 3:30 AM, Andrew Burgess > wrote: > > > >> This patch revamps the arc's header file by means of using separate > >> headers for different tool targets. Each target header file holds the > >> specific compiler backend macros definit

Re: [PATCH 9e] Update "startwith" logic for pass-skipping to handle __RTL functions

On 01/17/2017 02:28 AM, Richard Biener wrote: This feels somewhat different, but still a hack. I don't have strong suggestions on how to approach this, but what we've got here feels like a hack and one prone to bitrot. All the above needs a bit of cleanup in the way we use (or not use) PROP_x

Re: patch to fix PR79058

On 01/17/2017 04:57 PM, Christophe Lyon wrote: Hi Vladimir, On 17 January 2017 at 17:14, Vladimir Makarov wrote: The following patch fixes https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79058 The patch was successfully bootstrapped and tested on x86-64. Committed as rev. 244535. The new

Re: [PATCH 0/5] OpenMP/PTX: improve correctness in SIMD regions

On Wed, Jan 18, 2017 at 07:15:34PM +0300, Alexander Monakov wrote: > On Wed, 18 Jan 2017, Jakub Jelinek wrote: > > We are talking here about addressable vars, right (so if we turn it into > > non-addressable, in the SIMT region we just use the normal PTX pseudos), > > right? We could emit inner ={

Re: [PATCH][PR lto/79061] Fix LTO plus ASAN fails with "AddressSanitizer: initialization-order-fiasco".

On 18/01/17 16:00, Richard Biener wrote: On Wed, 18 Jan 2017, Maxim Ostapenko wrote: Hi, as was figured out in PR LTO + ASan raises false initialization order fiasco alarm due to in LTO case main_input_filename doesn't match module name passed to __asan_before_dynamic_init. Following Jakub's s

Re: [PATCH 0/5] OpenMP/PTX: improve correctness in SIMD regions

On Wed, 18 Jan 2017, Jakub Jelinek wrote: > We are talking here about addressable vars, right (so if we turn it into > non-addressable, in the SIMT region we just use the normal PTX pseudos), > right? We could emit inner ={v} {CLOBBER}; before SIMT_EXIT() to make it > clear it shouldn't be moved a

Re: [PATCH][GCC][PATCHv3] Improve fpclassify w.r.t IEEE like numbers in GIMPLE.

On 12/19/2016 10:18 AM, Tamar Christina wrote: Hi All, I've respun the patch with the feedback from Jeff and Joseph. I think an integer mode should always exist - even in the case of TFmode on 32-bit systems (32-bit sparc / s390, for example, use TFmode long double for GNU/Linux, and it's supp

[PATCH 1/1] sparc32: Add a workaround for the LEON3FT store-store errata

Hi Eric, This patch adds a workaround to the Sparc backend for the LEON3FT store-store errata. It is enabled using the -mfix-b2bst flag. The workaround inserts NOP instructions to prevent the following two instruction sequences from being generated: std -> stb/sth/st/std stb/sth/st -> any single

Re: [PATCH 0/5] OpenMP/PTX: improve correctness in SIMD regions

On Wed, Jan 18, 2017 at 06:34:05PM +0300, Alexander Monakov wrote: > My main concern is that nothing indicates to optimization passes that after > SIMT_EXIT(), underlying storage is unavailable. What would prevent the > compiler > from transforming, say > > SIMT_ENTER(); > // originally omp

Re: [PATCH C++] Fix PR77489 -- mangling of discriminator >= 10

On Wed, Jan 18, 2017 at 10:32 AM, Markus Trippelsdorf wrote: > On 2017.01.18 at 16:25 +0100, Jakub Jelinek wrote: >> On Wed, Jan 18, 2017 at 04:16:44PM +0100, Markus Trippelsdorf wrote: >> > No. It appears to work even without the additional condition: >> > >> > % g++ -fabi-version=10 -Wabi=11 -W

Re: [PATCH, ARM] correctly encode the CC reg data flow

On 01/13/17 19:28, Bernd Edlinger wrote: > On 01/13/17 17:10, Bernd Edlinger wrote: >> On 01/13/17 14:50, Richard Earnshaw (lists) wrote: >>> On 18/12/16 12:58, Bernd Edlinger wrote: Hi, this is related to PR77308, the follow-up patch will depend on this one. When tryi

Re: [PATCH] Speed-up use-after-scope (re-writing to SSA) (version 2)

Hello. During bootstrap, I came to following test-case: struct A { int regno; }; struct { A base; } typedef *df_ref; int *a; void fn1 (int N) { for (int i = 0; i < N; i++) { df_ref b; a[(b)->base.regno]++; } } As we expand all usages of an LHS of a ASAN_POISON to all us

Re: [PATCH 0/5] OpenMP/PTX: improve correctness in SIMD regions

On Wed, 18 Jan 2017, Jakub Jelinek wrote: > On Wed, Jan 18, 2017 at 05:52:49PM +0300, Alexander Monakov wrote: > > On Wed, 18 Jan 2017, Jakub Jelinek wrote: > > > Can't it be e.g. recorded inside a flag on the VAR_DECLs or magic > > > attributes > > > on them during omplower time and then only fi

Re: [PATCH] Be careful about combined chain with length == 0 (PR, tree-optimization/70754).

On Wed, Jan 18, 2017 at 2:54 PM, Richard Biener wrote: > On Wed, Jan 18, 2017 at 11:10 AM, Martin Liška wrote: >> Hello. >> >> >> Patch can bootstrap on ppc64le-redhat-linux and survives regression tests. >> >> Ready to be installed? > > I'm not sure. If we have such zero distance refs in the IL

Re: [PATCH C++] Fix PR77489 -- mangling of discriminator >= 10

On 2017.01.18 at 16:25 +0100, Jakub Jelinek wrote: > On Wed, Jan 18, 2017 at 04:16:44PM +0100, Markus Trippelsdorf wrote: > > No. It appears to work even without the additional condition: > > > > % g++ -fabi-version=10 -Wabi=11 -Wall -c gcc/testsuite/g++.dg/abi/pr77489.C > > gcc/testsuite/g++.dg/

Re: Ping Re: [PATCH] Avoid in gcc.target/powerpc/ -m32 or -m64 in dg-options (PR target/77416)

On Wed, Jan 18, 2017 at 01:51:12PM +0100, Jakub Jelinek wrote: > > The pr77416.c test fails in some configurations, where the -m32 option > > is not supported. The following patch fixes that by guarding the test > > with ilp32 effective target and removing the -m32 and adjusts a couple of > > test

Re: [PATCH C++] Fix PR77489 -- mangling of discriminator >= 10

On Wed, Jan 18, 2017 at 04:16:44PM +0100, Markus Trippelsdorf wrote: > No. It appears to work even without the additional condition: > > % g++ -fabi-version=10 -Wabi=11 -Wall -c gcc/testsuite/g++.dg/abi/pr77489.C > gcc/testsuite/g++.dg/abi/pr77489.C:56:16: warning: the mangled name of > ‘localVa

Re: [PATCH C++] Fix PR77489 -- mangling of discriminator >= 10

On 2017.01.18 at 10:03 -0500, Jason Merrill wrote: > On Wed, Jan 18, 2017 at 9:23 AM, Markus Trippelsdorf > wrote: > > On 2017.01.18 at 09:11 -0500, Jason Merrill wrote: > >> On Wed, Jan 18, 2017 at 3:55 AM, Markus Trippelsdorf > >> wrote: > >> > On 2017.01.17 at 13:26 -0500, Jason Merrill wrote:

Re: [PR tree-optimization/71691] Fix unswitching in presence of maybe-undef SSA_NAMEs (take 2)

On Fri, Jan 13, 2017 at 7:48 PM, Aldy Hernandez wrote: > [Sorry for the delay, I was sick.] > > > On 01/09/2017 04:30 AM, Richard Biener wrote: >> >> On Sat, Jan 7, 2017 at 1:54 PM, Aldy Hernandez wrote: >>> >>> On 01/04/2017 07:11 AM, Richard Biener wrote: On Tue, Jan 3, 2017 at 6

Re: [PATCH 1/5] omp-low: introduce omplow_simd_context

On Wed, 18 Jan 2017, Jakub Jelinek wrote: > > +/* This structure is part of the interface between > > lower_rec_simd_input_clauses > > + and lower_rec_input_clauses. */ > > + > > +struct omplow_simd_context { > > + tree idx; > > + tree lane; > > + int max_vf; > > + bool is_simt; > > Any re

Re: [PATCH 0/5] OpenMP/PTX: improve correctness in SIMD regions

On Wed, Jan 18, 2017 at 05:52:49PM +0300, Alexander Monakov wrote: > On Wed, 18 Jan 2017, Jakub Jelinek wrote: > > Can't it be e.g. recorded inside a flag on the VAR_DECLs or magic attributes > > on them during omplower time and then only finalized into the magic .local > > alloca in the pass_omp_d

Re: [PATCH 1/5] omp-low: introduce omplow_simd_context

On Wed, Jan 18, 2017 at 06:02:06PM +0300, Alexander Monakov wrote: > > > +struct omplow_simd_context { > > > + tree idx; > > > + tree lane; > > > + int max_vf; > > > + bool is_simt; > > > > Any reason ivar and lvar weren't added there too? > > Yes, they are not part of 'persistently live cont

Re: [PATCH C++] Fix PR77489 -- mangling of discriminator >= 10

On Wed, Jan 18, 2017 at 9:23 AM, Markus Trippelsdorf wrote: > On 2017.01.18 at 09:11 -0500, Jason Merrill wrote: >> On Wed, Jan 18, 2017 at 3:55 AM, Markus Trippelsdorf >> wrote: >> > On 2017.01.17 at 13:26 -0500, Jason Merrill wrote: >> >> On Thu, Jan 12, 2017 at 2:36 AM, Markus Trippelsdorf >>

Re: [PATCH 3/5] improve usage of PROP_gimple_lomp_dev

On Tue, Jan 17, 2017 at 11:07:43PM +0300, Alexander Monakov wrote: > This patch implements propagation of PROP_gimple_lomp_dev during inlining to > allow using it to decide whether pass_omp_device_lower needs to run. > > We need to clear this property in expand_omp_simd when the _simt_ clause is >

Re: [PATCH] Be careful about combined chain with length == 0 (PR, tree-optimization/70754).

On Wed, Jan 18, 2017 at 11:10:32AM +0100, Martin Liška wrote: > Hello. > > After basic understanding of loop predictive commoning, the problematic > combined chain is: > > Loads-only chain 0x38b6730 (combined) > max distance 0 > references: > MEM[(real(kind=8) *)vectp_a.29_81] (id 1) >

Re: [PATCH] Be careful about combined chain with length == 0 (PR, tree-optimization/70754).

On Wed, Jan 18, 2017 at 11:10 AM, Martin Liška wrote: > Hello. > > After basic understanding of loop predictive commoning, the problematic > combined chain is: > > Loads-only chain 0x38b6730 (combined) > max distance 0 > references: > MEM[(real(kind=8) *)vectp_a.29_81] (id 1) > offs

Re: [PATCH 0/5] OpenMP/PTX: improve correctness in SIMD regions

On Wed, 18 Jan 2017, Jakub Jelinek wrote: > Can't it be e.g. recorded inside a flag on the VAR_DECLs or magic attributes > on them during omplower time and then only finalized into the magic .local > alloca in the pass_omp_device_lower pass? No (see my adjacent response): it can't be a variable fl

Re: [PATCH 0/5] OpenMP/PTX: improve correctness in SIMD regions

On Wed, Jan 18, 2017 at 03:32:56PM +0100, Jakub Jelinek wrote: > > It probably is. > > > > But I guess I was asking whether you could initially emit > > > > void *omp_simt = IFN_GOMP_SIMT_ENTER (0); > > > > for (int i = n1; i < n2; i++) > > foo (&tmp); > > > > IFN_GOMP_SIMT_EXIT (omp_

Re: [PATCH 1/5] omp-low: introduce omplow_simd_context

On Tue, Jan 17, 2017 at 11:07:41PM +0300, Alexander Monakov wrote: > In preparation to handle new SIMT privatization in > lower_rec_simd_input_clauses > this patch factors out variables common to this and lower_rec_input_clauses to > a new structure. No functional change intended. > > * om

[PATCH, Fortran, documentation, v1] [COARRAY][API-DOC] Fix documentation of coarray API functions

Hi all, this patch adds undocumented parameters to caf-API functions and fixes the documentation style in many parts of the caf-API functions. It intentionally does not fix the last paragraph in the caf-API function's section (co_reduce), because I do not understand what is intended by the last se

lambda capture scope question

Jason, What is the scope of a lambda capture? AFAICT it depends on whether the capture is simple or initialized. the attached program prints: [x] is i [x=x] is i [x=x] {short x;} is s I'm not sure that's right. The clearest one is an initialized capture. [5.1.6]/12 says this is equivalent t

Re: [PATCH 0/5] OpenMP/PTX: improve correctness in SIMD regions

On Wed, 18 Jan 2017, Richard Biener wrote: > But I guess I was asking whether you could initially emit > > void *omp_simt = IFN_GOMP_SIMT_ENTER (0); > > for (int i = n1; i < n2; i++) > foo (&tmp); > > IFN_GOMP_SIMT_EXIT (omp_simt); > > and only after inlining do liveness / use analysi

Re: [PATCH 0/5] OpenMP/PTX: improve correctness in SIMD regions

On Wed, Jan 18, 2017 at 03:22:15PM +0100, Richard Biener wrote: > > So I guess a way to keep allocation layout implicit until after inlining is > > this: instead of exposing the helper struct in the IR immediately, somehow > > keep > > it on the side, associated only with the SIMT region, and not

Re: [PATCH C++] Fix PR77489 -- mangling of discriminator >= 10

On 2017.01.18 at 09:11 -0500, Jason Merrill wrote: > On Wed, Jan 18, 2017 at 3:55 AM, Markus Trippelsdorf > wrote: > > On 2017.01.17 at 13:26 -0500, Jason Merrill wrote: > >> On Thu, Jan 12, 2017 at 2:36 AM, Markus Trippelsdorf > >> wrote: > > + if (abi_version_at_least (11) && discriminator

Re: [PATCH 0/5] OpenMP/PTX: improve correctness in SIMD regions

On Wed, Jan 18, 2017 at 3:11 PM, Alexander Monakov wrote: > On Wed, 18 Jan 2017, Richard Biener wrote: >> > After OpenMP lowering, inlining might break this by inlining functions with >> > address-taken locals into SIMD regions. For now, such inlining is >> > disallowed >> > (this penalizes only

Re: [PATCH C++] Fix PR77489 -- mangling of discriminator >= 10

On Wed, Jan 18, 2017 at 3:55 AM, Markus Trippelsdorf wrote: > On 2017.01.17 at 13:26 -0500, Jason Merrill wrote: >> On Thu, Jan 12, 2017 at 2:36 AM, Markus Trippelsdorf >> wrote: > + if (abi_version_at_least (11) && discriminator - 1 >= 10) > + { > + write_char ('_'); > +

Re: [PATCH 0/5] OpenMP/PTX: improve correctness in SIMD regions

On Wed, 18 Jan 2017, Richard Biener wrote: > > After OpenMP lowering, inlining might break this by inlining functions with > > address-taken locals into SIMD regions. For now, such inlining is > > disallowed > > (this penalizes only SIMT code), but eventually that can be handled by > > collecting

Re: [PATCH] Fix gcc.target/s390/target-attribute/tattr-2.c testcase

On 01/18/2017 01:05 PM, Jakub Jelinek wrote: ... > Two more things: > 1) > 823 error ("Builtin %qF is not supported without -mhtm " > 824"(default with -march=zEC12 and higher).", fndecl); >is a bug, diagnostics (I think Fortran FE is a big exception here) should

Re: [PATCH][PR lto/79061] Fix LTO plus ASAN fails with "AddressSanitizer: initialization-order-fiasco".

On Wed, 18 Jan 2017, Maxim Ostapenko wrote: > Hi, > > as was figured out in PR LTO + ASan raises false initialization order fiasco > alarm due to in LTO case main_input_filename doesn't match module name passed > to __asan_before_dynamic_init. > Following Jakub's suggestion I used TRANSLATION_UNI

Re: [C++ PATCH] PR 79091, ICE with unnamed enum mangle

On 01/17/2017 03:17 PM, Jason Merrill wrote: Hmm, what if write_exception_spec checks for a dependent noexcept-specifier first, and noexcept_spec_p second? That seems like it would avoid needing any change to nothrow_spec_p. that's a better solution. However it was easier for it to check for

Ping Re: [PATCH] Avoid in gcc.target/powerpc/ -m32 or -m64 in dg-options (PR target/77416)

Hi! On Wed, Jan 11, 2017 at 08:41:02PM +0100, Jakub Jelinek wrote: > The pr77416.c test fails in some configurations, where the -m32 option > is not supported. The following patch fixes that by guarding the test > with ilp32 effective target and removing the -m32 and adjusts a couple of > tests t

Re: [PATCH 9c] callgraph: handle __RTL functions

> > They're added to the cgraph by this call: > > /* Add to cgraph. */ > cgraph_node::finalize_function (fndecl, false); > > within function_reader::create_function (in r244110, though that code > isn't called yet; it's called by the stuff in patch 9). > > If I hack out that call, so that

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