> 2016-11-15 Richard Sandiford
> Alan Hayward
> David Sherwood
>
> * expr.c (emit_group_load_1): Tighten check for whether an
> access involves only one operand of a CONCAT. Use extract_bit_field
> for constants if the bit range does span the whole ope
On Wed, Nov 16, 2016 at 07:31:59AM +0100, Waldemar Brodkorb wrote:
> > On Wed, Nov 09, 2016 at 04:08:39PM +0100, Bernd Schmidt wrote:
> > > On 11/05/2016 06:14 PM, Waldemar Brodkorb wrote:
> > > >Hi,
> > > >
> > > >the following patch fixes PR68468.
> > > >Patch is used for a while in Buildroot wit
Hi,
Jakub Jelinek wrote,
> On Wed, Nov 09, 2016 at 04:08:39PM +0100, Bernd Schmidt wrote:
> > On 11/05/2016 06:14 PM, Waldemar Brodkorb wrote:
> > >Hi,
> > >
> > >the following patch fixes PR68468.
> > >Patch is used for a while in Buildroot without issues.
> > >
> > >2016-11-05 Waldemar Brodkorb
On Tue, 15 Nov 2016, Richard Sandiford wrote:
> Richard Sandiford writes:
> > This isn't intended to change the behaviour, just rewrite the
> > existing logic in a different (and hopefully clearer) way.
> > The new form -- particularly the part based on the "block"
> > concept -- is easier to con
On Sat, Nov 05, 2016 at 10:03:37PM -0400, David Edelsohn wrote:
> The patch adds testcase init-statement6.C, which includes the declaration
>
> extern void publish (int), raise (int);
>
> POSIX defines
>
> int raise (int);
>
> in which gets included by the C++ headers for the testcase on AIX.
On 15.11.2016 23:03, Eric Gallager wrote:
> On 11/15/16, Matthias Klose wrote:
>> On 15.11.2016 21:41, Matthias Klose wrote:
>>> On 15.11.2016 16:52, Jeff Law wrote:
On 11/15/2016 03:55 AM, Matthias Klose wrote:
> This patch removes some references to gcj in the top level and config
>
This is a fix for my PR70890 patch, which incorrectly removed all
REG_EQUIV notes rather than just one regarding a reg that dies.
Bootstrapped and regression tested powerpc64le-linux,
x86_64-linux, and mips-linux. OK to apply?
PR rtl-optimization/78325
PR rtl-optimization/70890
On 11/15/16, Matthias Klose wrote:
> On 15.11.2016 21:41, Matthias Klose wrote:
>> On 15.11.2016 16:52, Jeff Law wrote:
>>> On 11/15/2016 03:55 AM, Matthias Klose wrote:
This patch removes some references to gcj in the top level and config
directories and in the gcc documentation. The c
Bernd Edlinger writes:
> On 11/15/16 13:21, Richard Sandiford wrote:
>> Bernd Edlinger writes:
>>> Hi!
>>>
>>> The genattrtab build-tool uses way too much memory in general.
>>> I think there is no other build step that uses more memory.
>>>
>>> On the currently trunk it takes around 700MB to bui
Hi,
this is follow-up with tests for new __target__ attributes and
__builtin_cpu_supports update.
gcc/
* config/i386/i386.c (processor_features): Add
F_AVX5124VNNIW, F_AVX5124FMAPS.
(isa_names_table): Handle new features.
libgcc/
* config/i386/cpuinfo.c (processor_
On 11/15/2016 09:27 AM, Richard Sandiford wrote:
local_cprop_find_used_regs punted on all multiword registers,
with the comment:
/* Setting a subreg of a register larger than word_mode leaves
the non-written words unchanged. */
But this only applies if the outer mode is smaller
Eric Botcazou writes:
>> alias.c encodes memory sizes as follows:
>>
>> size > 0: the exact size is known
>> size == 0: the size isn't known
>> size < 0: the exact size of the reference itself is known,
>> but the address has been aligned via AND. In this case
>> "-size" includes the size of
On 11/15/16 13:21, Richard Sandiford wrote:
> Bernd Edlinger writes:
>> Hi!
>>
>> The genattrtab build-tool uses way too much memory in general.
>> I think there is no other build step that uses more memory.
>>
>> On the currently trunk it takes around 700MB to build the
>> ARM latency tab files.
Hi Andre,
> attached patch fixes the issue raised. The issue here was, that a copy of the
> base class was generated and its address passed to the _vptr->copy()-method,
> which then accessed memory, that was not present in the copy being an object
> of
> the base class. The patch fixes this by ma
This patch addresses various bugs in the spellcheck code in which
the goal string somehow makes it into the candidate list.
The goal string will always have an edit distance of 0 to itself, and
thus is the "closest" string to the goal, but offering it as a
suggestion will always be nonsensical e.g.
On 15/11/16 21:06, Michael Meissner wrote:
Now, that I have a little time, I can look into this, to at least make
predicate and peepholes match. There is some other stuff (support for the new
load/store that were added to the compiler after that we should also tackle).
I've been investigating
On Mon, 2016-11-14 at 16:14 +0100, Richard Biener wrote:
> On Fri, Nov 11, 2016 at 10:15 PM, David Malcolm
> wrote:
> > Changed in this version:
> >
> > * Rather than running just one pass, run *all* passes, but start at
> > the given pass; support for "dg-do run" tests that execute the
> > r
On Mon, Nov 14, 2016 at 04:57:58PM +, Andrew Stubbs wrote:
> The testcase powerpc/fusion3.c causes an ICE when compiled with
> -msoft-float.
>
> The key line in the testcase looks fairly harmless:
>
>void fusion_float_write (float *p, float f){ p[LARGE] = f; }
LARGE is large enough that
On 11/15/2016 02:06 PM, Daniel Santos wrote:
+;; Save multiple registers out-of-line after realignment
+(define_insn "save_multiple_realign"
+ [(match_parallel 0 "save_multiple"
+[(use (match_operand:P 1 "symbol_operand"))
+ (set (reg:P SP_REG) (plus:P (reg:P AX_REG)
+ (match_ope
On 15.11.2016 21:41, Matthias Klose wrote:
> On 15.11.2016 16:52, Jeff Law wrote:
>> On 11/15/2016 03:55 AM, Matthias Klose wrote:
>>> This patch removes some references to gcj in the top level and config
>>> directories and in the gcc documentation. The change to the config
>>> directory
>>> req
On 11/15/2016 09:49 AM, Richard Sandiford wrote:
vec_cmps assign the result of a vector comparison to a mask.
The optab was called with the destination having mode mask_mode
but with the source (the comparison) having mode VOIDmode,
which led to invalid rtl if the source operand was used directly
On 15.11.2016 16:52, Jeff Law wrote:
> On 11/15/2016 03:55 AM, Matthias Klose wrote:
>> This patch removes some references to gcj in the top level and config
>> directories and in the gcc documentation. The change to the config directory
>> requires regenerating aclocal.m4 and configure in each su
Hi all,
the attached patch fixes a wrong-code problem with the intrinsic
function EXTENDS_TYPE_OF. The simplification function which tries to
reduce calls to EXTENDS_TYPE_OF to a compile-time constant (if
possible) was a bit over-zealous and simplified cases that were
actually not decidable at com
On Tue, Nov 15, 2016 at 12:16:19PM -0700, Kelvin Nilsen wrote:
> The reason I am using SI mode is so that I don't have to disqualify the
> use of these functions on a 32-bit big-endian configuration.
>
> Do you want me to switch to DI mode for all the operands?
SI is fine, and can give slightly b
The PR points out that our FNV hash functions don't correctly
implement the FNV-1a function. Since the code is only kept for
backwards compatibility we probably don't want to change the results,
so this just adds comments to point out the issue.
PR libstdc++/59406
* include/bits/f
Hi,
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77848 identifies a situation
where if-conversion causes degradation when the if-converted loop is not
subsequently vectorized. The if-conversion pass does not have a cost
model to avoid such degradations. However, it does have a capability to
vers
Adds functions emit_msabi_outlined_save and emit_msabi_outlined_restore,
which are called from ix86_expand_prologue and ix86_expand_epilogue,
respectively.
---
gcc/config/i386/i386.c | 307 ++---
1 file changed, 288 insertions(+), 19 deletions(-)
diff -
This C++ class adds the basic support for foutline-msabi-xlogues by
manging the layout (where registers are stored based upon and other
facets of the optimization) and providing the proper symbol rtx for the
required stub.
xlouge_layout should not be used until a call to
ix86_compute_frame_layout
ix86_compute_frame_layout will now populate fields added to structs
machine_function and ix86_frame and modify the frame layout specific to
facilitate the use of save & restore stubs.
---
gcc/config/i386/i386.c | 117 -
1 file changed, 116 insertions
Adds the predicates save_multiple and restore_multiple to predicates.md,
which are used by following patterns in sse.md:
* save_multiple - insn that calls a save stub
* save_multiple_realign - insn that calls a save stub and also manages
a realign and hard frame pointer
* restore_multiple - call
This refactor is separated from a future patch that actually alters
ix86_compute_frame_layout.
---
gcc/config/i386/i386.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 56cc67d..5ed8fb6 100644
--- a/gcc/config
Adds static HARD_REG_SET stub_managed_regs to track registers that will
be managed by the pro/epilogue stubs for the function.
Adds a third parameter bool ignore_outlined to ix86_save_reg to specify
rather or not the count should include registers marked in
stub_managed_regs.
---
gcc/config/i386/
Adds libgcc/config/i386/i386-asm.h to manage common cpp and gas macros.
stubs use the following naming convention:
(sav|res)ms64[f][x]
save|resSave or restore
ms64Avoid possible name collisions with future stubs
(specific to 64-bit msabi --> sysv scenario)
This will need to be unsigned for a subsequent patch. Also adds the
constant NUM_X86_64_MS_CLOBBERED_REGS for brievity.
---
gcc/config/i386/i386.c | 8 +++-
gcc/config/i386/i386.h | 4 +++-
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/
Adds fountline-msabi-xlogues to common.opt and various fields to structs
machine_function and ix86_frame
---
gcc/common.opt | 7 +++
gcc/config/i386/i386.c | 35 ++-
gcc/config/i386/i386.h | 18 ++
3 files changed, 55 insertions(+), 5 de
Due to differences between the 64-bit Microsoft and System V ABIs, any
msabi function that calls a sysv function must consider RSI, RDI and
XMM6-15 as clobbered. The result is that such functions are bloated with
SSE saves/restores costing as much as 106 bytes each (up to 200-ish
bytes per func
On Tue, Nov 15, 2016 at 6:37 PM, Jerry DeLisle wrote:
> All comments incorporated. Standing by for approval.
Looks good, nice job! Ok for trunk.
I was thinking that for strided arrays, it probably is faster to copy
them to dense arrays before doing the matrix multiplication. That
would also enab
On Tue, Nov 15, 2016 at 11:31 AM, Jonathan Wakely wrote:
> On 15/11/16 12:08 +, Jonathan Wakely wrote:
>>
>> On 12/11/16 12:11 -0800, Tim Shen wrote:
>>>
>>> At Issaquah we decided to remove the supports above.
>>
>>
>> OK with a suitable ChangeLog, thanks.
>
>
> I've adjusted your ChangeLog e
> alias.c encodes memory sizes as follows:
>
> size > 0: the exact size is known
> size == 0: the size isn't known
> size < 0: the exact size of the reference itself is known,
> but the address has been aligned via AND. In this case
> "-size" includes the size of the reference and the worst-c
Hello!
Just noticed that we don't test many function specific options on
64-bit targets.
2016-11-15 Uros Bizjak
* gcc.target/i386/funcspec-56.inc: New file.
* gcc.target/i386.funcspec-5.c: Include funcspec-56.inc. Remove
common 32-bit and 64-bit function specific options.
* g
This is needed to avoid problems with the new structured bindings
feature that landed in trunk yesterday.
As part of this patch I'm removing the docs for the DR 2742 and 2748
changes that I added earlier today. The manual doesn't need to track
changes against new features that only appear in trun
On 15/11/16 14:33 +, Jonathan Wakely wrote:
This is another issue resolution for C++17 features that was approved
at the recent meeting. I think this resolution is wrong too, but in
this case the fix is obvious so I've gone ahead and done it.
* doc/xml/manual/intro.xml: Document LWG
On 15/11/16 12:08 +, Jonathan Wakely wrote:
On 12/11/16 12:11 -0800, Tim Shen wrote:
At Issaquah we decided to remove the supports above.
OK with a suitable ChangeLog, thanks.
I've adjusted your ChangeLog entry to fit under 80 columns with TAB
set to 8 spaces. I've also adjusted the pret
On 15/11/16 16:48, Jiong Wang wrote:
>
>
> On 15/11/16 16:18, Jakub Jelinek wrote:
>> On Tue, Nov 15, 2016 at 04:00:40PM +, Jiong Wang wrote:
>Takes one signed LEB128 offset and retrieves 8-byte contents
> from the address
>calculated by CFA plus this offset, the contents
>
>> Thanks for catching this. I think I got endian confusion inside my head
>> while I was writing the above. I will rewrite these comments, below also.
>
> Note the ISA calls the bits in 32-bit registers 32..63, so that 63 is
> the rightmost bit in all registers.
>
True, but the ISA only u
On 11/15/2016 11:56 AM, Jeff Law wrote:
On 11/15/2016 11:12 AM, Richard Sandiford wrote:
Jeff Law writes:
On 11/15/2016 05:42 AM, Richard Sandiford wrote:
LOAD_EXTEND_OP only applies to scalar integer modes that are narrower
than a word. However, callers weren't consistent about which of the
On 11/15/2016 11:12 AM, Richard Sandiford wrote:
Jeff Law writes:
On 11/15/2016 05:42 AM, Richard Sandiford wrote:
LOAD_EXTEND_OP only applies to scalar integer modes that are narrower
than a word. However, callers weren't consistent about which of these
checks they made beforehand, and also
On 07/11/2016 16:59, Adhemerval Zanella wrote:
> On 14/10/2016 15:59, Wilco Dijkstra wrote:
> There is no limit afaik on gold split stack allocation handling,
> and I think one could be added for each backend (in the method
> override require to implement it).
>
> In fact it is not really requir
This implements separate shrink-wrapping for the save/restore of the
floating point registers. It regression checks fine, but that does
not test on many big floating point routines (and neither does the
bootstrap itself). So I'm not proposing this for trunk just yet.
I'll write a changelog if th
> 2016-11-15 Richard Sandiford
> Alan Hayward
> David Sherwood
>
> * rtl.h (load_extend_op): Declare.
> * rtlanal.c (load_extend_op): New function.
I'd make it an inline function.
--
Eric Botcazou
Jeff Law writes:
> On 11/15/2016 09:21 AM, Richard Sandiford wrote:
>> If the size passed in to rtx_addr_can_trap_p was zero, the frame
>> handling would get the size from the mode instead. However, this
>> too can be zero if the mode is BLKmode, i.e. if we have a BLKmode
>> memory reference with
On Tue, Nov 15, 2016 at 11:05:07AM -0700, Kelvin Nilsen wrote:
> >>* config/rs6000/altivec.md (UNSPEC_CMPRB): New unspec value.
> >>(UNSPEC_CMPRB2): New unspec value.
> >
> > I wonder if you really need both? The number of arguments will tell
> > which is which, anyway?
>
> I appreciate
On 11/15/2016 09:52 AM, Richard Sandiford wrote:
Several definitions of INCOMING_RETURN_ADDR_RTX used
gen_rtx_REG (VOIDmode, ...), which with later patches
would trip an assert. This patch converts them to use
Pmode instead.
Tested on aarch64-linux-gnu and x86_64-linux-gnu. OK to install?
Tha
Jeff Law writes:
> On 11/15/2016 05:42 AM, Richard Sandiford wrote:
>> LOAD_EXTEND_OP only applies to scalar integer modes that are narrower
>> than a word. However, callers weren't consistent about which of these
>> checks they made beforehand, and also weren't consistent about whether
>> "small
Hi,
this is the last patch to the hsa branch before using it to create the
merge-to-trunk patches. Basically, it replaces all references to
"GPGPU gridification" in omp-low.c to "HSA gridification" as requested
by Jakub at the Cauldron.
Committed to the HSA branch, it is part of the posted patch
Hi,
this is one of the last two commits to the hsa branch I made while
preparing the merge to trunk, it moves headers generated from HSA
documentation to the plugin directory.
Committed to the HSA branch, it is part of the posted patches merging
it to trunk.
Thanks,
Martin
2016-11-12 Martin
Thank you very much for the prompt and thorough review. There are a few
points below where I'd like to seek further clarification.
On 11/15/2016 04:19 AM, Segher Boessenkool wrote:
> Hi!
>
> On Mon, Nov 14, 2016 at 04:43:35PM -0700, Kelvin Nilsen wrote:
>> * config/rs6000/altivec.md (UNSPE
Eric Botcazou writes:
>> 2016-11-15 Richard Sandiford
>> Alan Hayward
>> David Sherwood
>>
>> * rtlanal.c (num_sign_bit_copies1): Calculate bitwidth after
>> handling VOIDmode.
>
> OK, thanks, but please change the comment too, I think "For a smaller mode"
On 15.11.2016 16:52, Jeff Law wrote:
> On 11/15/2016 03:55 AM, Matthias Klose wrote:
>> This patch removes some references to gcj in the top level and config
>> directories and in the gcc documentation. The change to the config directory
>> requires regenerating aclocal.m4 and configure in each su
OK.
On Tue, Nov 15, 2016 at 9:13 AM, Jakub Jelinek wrote:
> Hi!
>
> This patch adds 3 new tests. Tested on x86_64-linux, ok for trunk?
>
> 2016-11-15 Jakub Jelinek
>
> * g++.dg/cpp1z/decomp13.C: New test.
> * g++.dg/cpp1z/decomp14.C: New test.
> * g++.dg/cpp1z/decomp15
On Tue, 15 Nov 2016, Alexander Monakov wrote:
> Yep, I do see new test execution failures with both Intel MIC and PTX
> offloading
> on device-1.f90, device-3.f90 and target2.f90. Here's an actually-tested
> patch
> for the first two (on target2.f90 there's a different problem).
And here's a pa
On Tue, Nov 15, 2016 at 08:48:04AM -0800, Andrew Pinski wrote:
> On Fri, Oct 7, 2016 at 1:01 AM, Kyrill Tkachov
> wrote:
> > Hi Andrew,
> >
> >
> > On 24/09/16 06:46, Andrew Pinski wrote:
> >>
> >> Hi,
> >>As reported in PR 61367, the aarch64 back-end is too verbose when it
> >> is dealing wit
OK.
On Tue, Nov 15, 2016 at 9:12 AM, Jakub Jelinek wrote:
> Hi!
>
> On the following testcase we ICE, because the underlying artificial decls
> have NULL DECL_NAME (intentional), thus mangling is not able to figure out
> what to do. This patch attempts to follow the
> http://sourcerytools.com/pi
On Tue, Nov 15, 2016 at 07:52:56PM +0300, Alexander Monakov wrote:
> On Mon, 14 Nov 2016, Alexander Monakov wrote:
> > On Mon, 14 Nov 2016, Martin Jambor wrote:
> >
> > > Hi,
> > >
> > > yesterday I forgot to send out the following patch. The test
> > > libgomp/testsuite/libgomp.fortran/examples
On Mon, Nov 14, 2016 at 1:19 AM, Mark Wielaard wrote:
> In various situations the cplus_demangle () function could read past the
> end of input causing crashes. Add checks in various places to not advance
> the demangle string location and fail early when end of string is reached.
> Add various ex
> disabling/enabling makes this api a lot heavier
> than before, but trapping cannot be decided at
> compile-time, although the result may be cached,
> i think this should not be a frequent operation.
>
> otoh rereading my patch i think i fail to restore
> the original exception state correctly.
On Mon, 14 Nov 2016, Alexander Monakov wrote:
> On Mon, 14 Nov 2016, Martin Jambor wrote:
>
> > Hi,
> >
> > yesterday I forgot to send out the following patch. The test
> > libgomp/testsuite/libgomp.fortran/examples-4/device-3.f90 was failing
> > for me when I was testing the HSA branch merge bu
Several definitions of INCOMING_RETURN_ADDR_RTX used
gen_rtx_REG (VOIDmode, ...), which with later patches
would trip an assert. This patch converts them to use
Pmode instead.
Tested on aarch64-linux-gnu and x86_64-linux-gnu. OK to install?
Thanks,
Richard
[ This patch is part of the SVE seri
On 15/11/16 12:29, Segher Boessenkool wrote:
The peepholes do not support it, or maybe the define_insns do not either.
The machine of course will not care.
Oh, OK, so probably the bug is not in the peephole at all, but in the
define_insn, or lack thereof.
More investigation required.
Thanks
On 15/11/16 16:18, Jakub Jelinek wrote:
On Tue, Nov 15, 2016 at 04:00:40PM +, Jiong Wang wrote:
Takes one signed LEB128 offset and retrieves 8-byte contents from the address
calculated by CFA plus this offset, the contents then authenticated as per A
key for instruction pointer usin
vec_cmps assign the result of a vector comparison to a mask.
The optab was called with the destination having mode mask_mode
but with the source (the comparison) having mode VOIDmode,
which led to invalid rtl if the source operand was used directly.
Tested on aarch64-linux-gnu and x86_64-linux-gnu
On 15/11/16 16:18, Jakub Jelinek wrote:
On Tue, Nov 15, 2016 at 04:00:40PM +, Jiong Wang wrote:
Takes one signed LEB128 offset and retrieves 8-byte contents from the address
calculated by CFA plus this offset, the contents then authenticated as per A
key for instruction pointer us
On Fri, Oct 7, 2016 at 1:01 AM, Kyrill Tkachov
wrote:
> Hi Andrew,
>
>
> On 24/09/16 06:46, Andrew Pinski wrote:
>>
>> Hi,
>>As reported in PR 61367, the aarch64 back-end is too verbose when it
>> is dealing with the cost model. I tend to agree, no other back-end is
>> this verbose. So I dec
Richard Sandiford writes:
> This isn't intended to change the behaviour, just rewrite the
> existing logic in a different (and hopefully clearer) way.
> The new form -- particularly the part based on the "block"
> concept -- is easier to convert to polynomial sizes.
>
> Tested on aarch64-linux-gnu
> Hi.
>
> As seen on ppc64le during compilation of Firefox with LTO, combining inchash
> value
> with a pointer, enum value and an integer, one can eventually get zero value.
> Thus I decided to introduce a new flag that would distinguish between not set
> hash value
> and a valid and (possibly)
On 11/15/2016 09:43 AM, Martin Liška wrote:
Hi.
As seen on ppc64le during compilation of Firefox with LTO, combining inchash
value
with a pointer, enum value and an integer, one can eventually get zero value.
Thus I decided to introduce a new flag that would distinguish between not set
hash va
Hi.
As seen on ppc64le during compilation of Firefox with LTO, combining inchash
value
with a pointer, enum value and an integer, one can eventually get zero value.
Thus I decided to introduce a new flag that would distinguish between not set
hash value
and a valid and (possibly) zero value.
I'
On 11/15/2016 09:21 AM, Richard Sandiford wrote:
If the size passed in to rtx_addr_can_trap_p was zero, the frame
handling would get the size from the mode instead. However, this
too can be zero if the mode is BLKmode, i.e. if we have a BLKmode
memory reference with no MEM_SIZE (which should be
This isn't intended to change the behaviour, just rewrite the
existing logic in a different (and hopefully clearer) way.
The new form -- particularly the part based on the "block"
concept -- is easier to convert to polynomial sizes.
Tested on aarch64-linux-gnu and x86_64-linux-gnu. OK to install?
On 15/11/16 16:22, FX wrote:
>> There seems to be a separate api for checking trapping support:
>> ieee_support_halting, but it only checked if the exception status
>> flags are available, so check trapping support too by enabling
>> and disabling traps.
>
> Thanks for the patch.
>
> I am worried
On 11/15/2016 07:59 AM, Jerry DeLisle wrote:
On 11/14/2016 11:22 PM, Thomas Koenig wrote:
Hi Jerry,
With these changes, OK for trunk?
Just going over this with a fine comb...
One thing just struck me: The loop variables should be index_type, so
const index_type m = xcount, n = ycou
On 11/01/2016 03:39 PM, Wilco Dijkstra wrote:
Jeff Law wrote:
I think you'll need to look at bz61320 before this could go in.
I had a look, but there is nothing there that is related - eventually
a latent alignment bug was fixed in IVOpt.
Excellent. Thanks for digging into what really hap
local_cprop_find_used_regs punted on all multiword registers,
with the comment:
/* Setting a subreg of a register larger than word_mode leaves
the non-written words unchanged. */
But this only applies if the outer mode is smaller than the
inner mode. If they're the same size then
Provide versions of subreg_lowpart_offset and subreg_highpart_offset
that work on mode sizes rather than modes. Also provide a routine
that converts an lsb position to a subreg offset.
The intent (in combination with later patches) is to move the
handling of the BYTES_BIG_ENDIAN != WORDS_BIG_ENDI
OK, (hopefully) one more patch for decltype and C++17 decomposition
declarations. I hadn't been thinking that "referenced type" meant to
look through references in the tuple case, since other parts of
[dcl.decomp] define "the referenced type" directly, but that does seem
to be how it's used elsewh
2016-11-15 17:56 GMT+03:00 Jeff Law :
> On 11/15/2016 05:55 AM, Andrew Senkevich wrote:
>>
>> 2016-11-11 14:16 GMT+03:00 Uros Bizjak :
>>>
>>> --- a/gcc/genmodes.c
>>> +++ b/gcc/genmodes.c
>>> --- a/gcc/init-regs.c
>>> +++ b/gcc/init-regs.c
>>> --- a/gcc/machmode.h
>>> +++ b/gcc/machmode.h
>>>
>>>
Hi all,
attached patch fixes the issue raised. The issue here was, that a copy of the
base class was generated and its address passed to the _vptr->copy()-method,
which then accessed memory, that was not present in the copy being an object of
the base class. The patch fixes this by making sure the
The CONCAT handling in emit_group_load chooses between doing
an extraction from a single component or forcing the whole
thing to memory and extracting from there. The condition for
the former (more efficient) option was:
if ((bytepos == 0 && bytelen == slen0)
|| (bytepos !
Maciej Rozycki writes:
> gcc/
> * config/mips/mips-protos.h (mips_set_text_contents_type): New
> prototype.
> * config/mips/mips.h (ASM_OUTPUT_BEFORE_CASE_LABEL): New macro.
> (ASM_OUTPUT_CASE_END): Likewise.
> * config/mips/mips.c (mips_set_text_contents_type):
Hi,
> There seems to be a separate api for checking trapping support:
> ieee_support_halting, but it only checked if the exception status
> flags are available, so check trapping support too by enabling
> and disabling traps.
Thanks for the patch.
I am worried about the unnecessary operations th
On 11/15/2016 09:17 AM, Richard Sandiford wrote:
Using MEM_SIZE is more general, since it copes with cases where
targets are forced to use BLKmode references for whatever reason.
Thanks,
Richard
[ This patch is part of the SVE series posted here:
https://gcc.gnu.org/ml/gcc/2016-11/msg00030.h
If the size passed in to rtx_addr_can_trap_p was zero, the frame
handling would get the size from the mode instead. However, this
too can be zero if the mode is BLKmode, i.e. if we have a BLKmode
memory reference with no MEM_SIZE (which should be rare these days).
This meant that the conditions fo
On 11/14/2016 02:39 AM, Jeff Law wrote:
I was looking at the possibility of dropping threading from VRP1/VRP2 or
DOM1/DOM2 in favor of the backwards threader -- the obvious idea being
to recover some compile-time for gcc-7.
Of the old-style threader passes (VRP1, VRP2, DOM1, DOM2), VRP2 is by
On Tue, Nov 15, 2016 at 04:00:40PM +, Jiong Wang wrote:
> >> Takes one signed LEB128 offset and retrieves 8-byte contents from the
> >> address
> >> calculated by CFA plus this offset, the contents then authenticated as
> >> per A
> >> key for instruction pointer using current CFA as sa
Using MEM_SIZE is more general, since it copes with cases where
targets are forced to use BLKmode references for whatever reason.
Thanks,
Richard
[ This patch is part of the SVE series posted here:
https://gcc.gnu.org/ml/gcc/2016-11/msg00030.html ]
gcc/
2016-11-15 Richard Sandiford
The previous code processed the users of a stack slot in order of
decreasing size and allocated the slot based on the first user.
This seems a bit dangerous, since the ordering is based on the
mode of the biggest reference while the allocation is based also
on the size of the register itself (which
On 11/15/2016 09:07 AM, Richard Sandiford wrote:
After simplifying the operands of a PLUS, canon_rtx checked only
for cases in which one of the simplified operands was a constant,
falling back to gen_rtx_PLUS otherwise. This left the PLUS in a
non-canonical order if one of the simplified operand
When fpu trapping is enabled in libgfortran, the return value of
feenableexcept is not checked. Glibc reports there if the operation
was unsuccessful which happens if the target has no trapping support.
There seems to be a separate api for checking trapping support:
ieee_support_halting, but it o
After simplifying the operands of a PLUS, canon_rtx checked only
for cases in which one of the simplified operands was a constant,
falling back to gen_rtx_PLUS otherwise. This left the PLUS in a
non-canonical order if one of the simplified operands was
(plus (reg R1) (const_int X)); we'd end up wi
alias.c encodes memory sizes as follows:
size > 0: the exact size is known
size == 0: the size isn't known
size < 0: the exact size of the reference itself is known,
but the address has been aligned via AND. In this case
"-size" includes the size of the reference and the worst-case
number o
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