[gcc r15-3477] docs: double mention of armv9-a.

https://gcc.gnu.org/g:240be78237c6d70e0b30ed187c559e359ce81557 commit r15-3477-g240be78237c6d70e0b30ed187c559e359ce81557 Author: Tamar Christina Date: Thu Sep 5 10:35:18 2024 +0100 docs: double mention of armv9-a. The list of available architecture for Arm is incorrectly listing a

[gcc r15-3478] testsuite: remove -fwrapv from signbit-5.c

https://gcc.gnu.org/g:67eaf67360e434dd5969e1c66f043e3c751f9f52 commit r15-3478-g67eaf67360e434dd5969e1c66f043e3c751f9f52 Author: Tamar Christina Date: Thu Sep 5 10:36:02 2024 +0100 testsuite: remove -fwrapv from signbit-5.c The meaning of the testcase was changed by passing it -fw

[gcc r15-3479] middle-end: have vect_recog_cond_store_pattern use pattern statement for cond if available

https://gcc.gnu.org/g:a50f54c0d06139d791b875e09471f2fc03af5b04 commit r15-3479-ga50f54c0d06139d791b875e09471f2fc03af5b04 Author: Tamar Christina Date: Thu Sep 5 10:36:55 2024 +0100 middle-end: have vect_recog_cond_store_pattern use pattern statement for cond if available When vec

[gcc r15-3518] middle-end: check that the lhs of a COND_EXPR is an SSA_NAME in cond_store recognition [PR116628]

https://gcc.gnu.org/g:2c4438d39156493b5b382eb48b1f884ca5ab7ed4 commit r15-3518-g2c4438d39156493b5b382eb48b1f884ca5ab7ed4 Author: Tamar Christina Date: Fri Sep 6 14:05:43 2024 +0100 middle-end: check that the lhs of a COND_EXPR is an SSA_NAME in cond_store recognition [PR116628] B

[gcc r15-1808] ivopts: fix wide_int_constant_multiple_p when VAL and DIV are 0. [PR114932]

https://gcc.gnu.org/g:25127123100f04c2d5d70c6933a5f5aedcd69c40 commit r15-1808-g25127123100f04c2d5d70c6933a5f5aedcd69c40 Author: Tamar Christina Date: Wed Jul 3 09:30:28 2024 +0100 ivopts: fix wide_int_constant_multiple_p when VAL and DIV are 0. [PR114932] wide_int_constant_multi

[gcc r15-1809] ivopts: replace constant_multiple_of with aff_combination_constant_multiple_p [PR114932]

https://gcc.gnu.org/g:735edbf1e2479fa2323a2b4a9714fae1a0925f74 commit r15-1809-g735edbf1e2479fa2323a2b4a9714fae1a0925f74 Author: Tamar Christina Date: Wed Jul 3 09:31:09 2024 +0100 ivopts: replace constant_multiple_of with aff_combination_constant_multiple_p [PR114932] The curren

[gcc r15-1841] c++ frontend: check for missing condition for novector [PR115623]

https://gcc.gnu.org/g:84acbfbecbdbc3fb2a395bd97e338b2b26fad374 commit r15-1841-g84acbfbecbdbc3fb2a395bd97e338b2b26fad374 Author: Tamar Christina Date: Thu Jul 4 11:01:55 2024 +0100 c++ frontend: check for missing condition for novector [PR115623] It looks like I forgot to check in

[gcc r14-10378] c++ frontend: check for missing condition for novector [PR115623]

https://gcc.gnu.org/g:1742b699c31e3ac4dadbedb6036ee2498b569259 commit r14-10378-g1742b699c31e3ac4dadbedb6036ee2498b569259 Author: Tamar Christina Date: Thu Jul 4 11:01:55 2024 +0100 c++ frontend: check for missing condition for novector [PR115623] It looks like I forgot to check i

[gcc r15-1842] testsuite: Update test for PR115537 to use SVE .

https://gcc.gnu.org/g:adcfb4fb8fb20a911c795312ff5f5284dba05275 commit r15-1842-gadcfb4fb8fb20a911c795312ff5f5284dba05275 Author: Tamar Christina Date: Thu Jul 4 11:19:20 2024 +0100 testsuite: Update test for PR115537 to use SVE . The PR was about SVE codegen, the testcase accident

[gcc r15-1855] AArch64: remove aarch64_simd_vec_unpack_lo_

https://gcc.gnu.org/g:6ff698106644af39da9e0eda51974fdcd111280d commit r15-1855-g6ff698106644af39da9e0eda51974fdcd111280d Author: Tamar Christina Date: Fri Jul 5 12:09:21 2024 +0100 AArch64: remove aarch64_simd_vec_unpack_lo_ The fix for PR18127 reworked the uxtl to zip optimizatio

[gcc r15-1856] AArch64: lower 2 reg TBL permutes with one zero register to 1 reg TBL.

https://gcc.gnu.org/g:97fcfeac3dcc433b792711fd840b92fa3e860733 commit r15-1856-g97fcfeac3dcc433b792711fd840b92fa3e860733 Author: Tamar Christina Date: Fri Jul 5 12:10:39 2024 +0100 AArch64: lower 2 reg TBL permutes with one zero register to 1 reg TBL. When a two reg TBL is perform

[gcc r15-2099] middle-end: fix 0 offset creation and folding [PR115936]

https://gcc.gnu.org/g:0135a90de5a99b51001b6152d8b548151ebfa1c3 commit r15-2099-g0135a90de5a99b51001b6152d8b548151ebfa1c3 Author: Tamar Christina Date: Wed Jul 17 16:22:14 2024 +0100 middle-end: fix 0 offset creation and folding [PR115936] As shown in PR115936 SCEV and IVOPTS creat

[gcc r15-2191] middle-end: Implement conditonal store vectorizer pattern [PR115531]

https://gcc.gnu.org/g:af792f0226e479b165a49de5e8f9e1d16a4b26c0 commit r15-2191-gaf792f0226e479b165a49de5e8f9e1d16a4b26c0 Author: Tamar Christina Date: Mon Jul 22 10:26:14 2024 +0100 middle-end: Implement conditonal store vectorizer pattern [PR115531] This adds a conditional store

[gcc r15-2192] AArch64: implement TARGET_VECTORIZE_CONDITIONAL_OPERATION_IS_EXPENSIVE [PR115531].

https://gcc.gnu.org/g:0c5c0c959c2e592b84739f19ca771fa69eb8dfee commit r15-2192-g0c5c0c959c2e592b84739f19ca771fa69eb8dfee Author: Tamar Christina Date: Mon Jul 22 10:28:19 2024 +0100 AArch64: implement TARGET_VECTORIZE_CONDITIONAL_OPERATION_IS_EXPENSIVE [PR115531]. This implement

[gcc r14-9493] match.pd: Only merge truncation with conversion for -fno-signed-zeros

https://gcc.gnu.org/g:7dd3b2b09cbeb6712ec680a0445cb0ad41070423 commit r14-9493-g7dd3b2b09cbeb6712ec680a0445cb0ad41070423 Author: Joe Ramsay Date: Fri Mar 15 09:20:45 2024 + match.pd: Only merge truncation with conversion for -fno-signed-zeros This optimisation does not honour

[gcc r14-9969] middle-end: adjust loop upper bounds when peeling for gaps and early break [PR114403].

https://gcc.gnu.org/g:85002f8085c25bb3e74ab013581a74e7c7ae006b commit r14-9969-g85002f8085c25bb3e74ab013581a74e7c7ae006b Author: Tamar Christina Date: Mon Apr 15 12:06:21 2024 +0100 middle-end: adjust loop upper bounds when peeling for gaps and early break [PR114403]. This fixes

[gcc r13-8604] AArch64: Do not allow SIMD clones with simdlen 1 [PR113552]

https://gcc.gnu.org/g:1e08e39c743692afdd5d3546b2223474beac1dbc commit r13-8604-g1e08e39c743692afdd5d3546b2223474beac1dbc Author: Tamar Christina Date: Mon Apr 15 12:11:48 2024 +0100 AArch64: Do not allow SIMD clones with simdlen 1 [PR113552] This is a backport of g:306713c953d5097

[gcc r12-10329] AArch64: Do not allow SIMD clones with simdlen 1 [PR113552]

https://gcc.gnu.org/g:642cfd049780f03335da9fe0a51415f130232334 commit r12-10329-g642cfd049780f03335da9fe0a51415f130232334 Author: Tamar Christina Date: Mon Apr 15 12:16:53 2024 +0100 AArch64: Do not allow SIMD clones with simdlen 1 [PR113552] This is a backport of g:306713c953d509

[gcc r11-11323] [AArch64]: Do not allow SIMD clones with simdlen 1 [PR113552]

https://gcc.gnu.org/g:0c2fcf3ddfe93d1f403962c4bacbb5d55ab7d19d commit r11-11323-g0c2fcf3ddfe93d1f403962c4bacbb5d55ab7d19d Author: Tamar Christina Date: Mon Apr 15 12:32:24 2024 +0100 [AArch64]: Do not allow SIMD clones with simdlen 1 [PR113552] This is a backport of g:306713c953d5

[gcc r14-9997] testsuite: Fix data check loop on vect-early-break_124-pr114403.c

https://gcc.gnu.org/g:f438acf7ce2e6cb862cf62f2543c36639e2af233 commit r14-9997-gf438acf7ce2e6cb862cf62f2543c36639e2af233 Author: Tamar Christina Date: Tue Apr 16 20:56:26 2024 +0100 testsuite: Fix data check loop on vect-early-break_124-pr114403.c The testcase had the wrong indice

[gcc r14-10014] AArch64: remove reliance on register allocator for simd/gpreg costing. [PR114741]

https://gcc.gnu.org/g:a2f4be3dae04fa8606d1cc8451f0b9d450f7e6e6 commit r14-10014-ga2f4be3dae04fa8606d1cc8451f0b9d450f7e6e6 Author: Tamar Christina Date: Thu Apr 18 11:47:42 2024 +0100 AArch64: remove reliance on register allocator for simd/gpreg costing. [PR114741] In PR114741 we

[gcc r14-10040] middle-end: refactory vect_recog_absolute_difference to simplify flow [PR114769]

https://gcc.gnu.org/g:1216460e7023cd8ec49933866107417c70e933c9 commit r14-10040-g1216460e7023cd8ec49933866107417c70e933c9 Author: Tamar Christina Date: Fri Apr 19 15:22:13 2024 +0100 middle-end: refactory vect_recog_absolute_difference to simplify flow [PR114769] Hi All,

[gcc r15-2336] middle-end: check for vector mode before calling get_mask_mode [PR116074]

https://gcc.gnu.org/g:29e4e4bdb674118b898d50ce7751c183aa0a44ee commit r15-2336-g29e4e4bdb674118b898d50ce7751c183aa0a44ee Author: Tamar Christina Date: Fri Jul 26 13:02:53 2024 +0100 middle-end: check for vector mode before calling get_mask_mode [PR116074] For historical reasons AA

[gcc r15-2638] AArch64: Update Neoverse V2 cost model to release costs

https://gcc.gnu.org/g:7e7c1e38829d45667748db68f15584bdd16fcad6 commit r15-2638-g7e7c1e38829d45667748db68f15584bdd16fcad6 Author: Tamar Christina Date: Thu Aug 1 16:53:22 2024 +0100 AArch64: Update Neoverse V2 cost model to release costs This updates the cost for Neoverse V2 to ref

[gcc r15-2640] AArch64: Add Neoverse V3AE core definition and cost model

https://gcc.gnu.org/g:7ca2a803c4a0d8e894f0b36625a2c838c54fb4cd commit r15-2640-g7ca2a803c4a0d8e894f0b36625a2c838c54fb4cd Author: Tamar Christina Date: Thu Aug 1 16:53:59 2024 +0100 AArch64: Add Neoverse V3AE core definition and cost model This adds a cost model and core definition

[gcc r15-2641] AArch64: Add Neoverse N3 and Cortex-A725 core definition and cost model

https://gcc.gnu.org/g:488395f9513233944e488fae59372da4de4324c3 commit r15-2641-g488395f9513233944e488fae59372da4de4324c3 Author: Tamar Christina Date: Thu Aug 1 16:54:15 2024 +0100 AArch64: Add Neoverse N3 and Cortex-A725 core definition and cost model This adds a cost model and c

[gcc r15-2642] AArch64: Update Generic Armv9-a cost model to release costs

https://gcc.gnu.org/g:3b0bac451110bf1591ce9085b66857448d099a8c commit r15-2642-g3b0bac451110bf1591ce9085b66857448d099a8c Author: Tamar Christina Date: Thu Aug 1 16:54:31 2024 +0100 AArch64: Update Generic Armv9-a cost model to release costs this updates the costs for gener-armv9-a

[gcc r15-2643] AArch64: Update Neoverse N2 cost model to release costs

https://gcc.gnu.org/g:f88cb43aed5c7db5676732c755ec4fee960ecbed commit r15-2643-gf88cb43aed5c7db5676732c755ec4fee960ecbed Author: Tamar Christina Date: Thu Aug 1 16:54:49 2024 +0100 AArch64: Update Neoverse N2 cost model to release costs This updates the cost for Neoverse N2 to ref

[gcc r15-2639] AArch64: Add Neoverse V3 core definition and cost model

https://gcc.gnu.org/g:729000b90300a31ef9ed405635a0be761c5e168b commit r15-2639-g729000b90300a31ef9ed405635a0be761c5e168b Author: Tamar Christina Date: Thu Aug 1 16:53:41 2024 +0100 AArch64: Add Neoverse V3 core definition and cost model This adds a cost model and core definition f

[gcc r15-2644] AArch64: Add Cortex-X925 core definition and cost model

https://gcc.gnu.org/g:1f53319cae81aea438b6c0ba55f49e5669acf1c8 commit r15-2644-g1f53319cae81aea438b6c0ba55f49e5669acf1c8 Author: Tamar Christina Date: Thu Aug 1 16:55:10 2024 +0100 AArch64: Add Cortex-X925 core definition and cost model This adds a cost model and core definition f

[gcc r15-2768] AArch64: take gather/scatter decode overhead into account

https://gcc.gnu.org/g:a50916a6c0a6c73c1537d033509d4f7034341f75 commit r15-2768-ga50916a6c0a6c73c1537d033509d4f7034341f75 Author: Tamar Christina Date: Tue Aug 6 22:41:10 2024 +0100 AArch64: take gather/scatter decode overhead into account Gather and scatters are not usually benefi

[gcc r15-2839] AArch64: Fix signbit mask creation after late combine [PR116229]

https://gcc.gnu.org/g:2c24e0568392e51a77ebdaab629d631969ce8966 commit r15-2839-g2c24e0568392e51a77ebdaab629d631969ce8966 Author: Tamar Christina Date: Thu Aug 8 18:51:30 2024 +0100 AArch64: Fix signbit mask creation after late combine [PR116229] The optimization to generate a Di s

[gcc r15-1038] AArch64: convert several predicate patterns to new compact syntax

https://gcc.gnu.org/g:fd4898891ae0c73d6b7aa433cd1ef4539aaa2457 commit r15-1038-gfd4898891ae0c73d6b7aa433cd1ef4539aaa2457 Author: Tamar Christina Date: Wed Jun 5 19:30:39 2024 +0100 AArch64: convert several predicate patterns to new compact syntax This converts the single alternati

[gcc r15-1039] AArch64: add new tuning param and attribute for enabling conditional early clobber

https://gcc.gnu.org/g:35f17c680ca650f8658994f857358e5a529c0b93 commit r15-1039-g35f17c680ca650f8658994f857358e5a529c0b93 Author: Tamar Christina Date: Wed Jun 5 19:31:11 2024 +0100 AArch64: add new tuning param and attribute for enabling conditional early clobber This adds a new

[gcc r15-1040] AArch64: add new alternative with early clobber to patterns

https://gcc.gnu.org/g:2de3bbde1ebea8689f3596967769f66bf903458e commit r15-1040-g2de3bbde1ebea8689f3596967769f66bf903458e Author: Tamar Christina Date: Wed Jun 5 19:31:39 2024 +0100 AArch64: add new alternative with early clobber to patterns This patch adds new alternatives to the

[gcc r15-1041] AArch64: enable new predicate tuning for Neoverse cores.

https://gcc.gnu.org/g:3eb9f6eab9802d5ae65ead6b1f2ae6fe0833e06e commit r15-1041-g3eb9f6eab9802d5ae65ead6b1f2ae6fe0833e06e Author: Tamar Christina Date: Wed Jun 5 19:32:16 2024 +0100 AArch64: enable new predicate tuning for Neoverse cores. This enables the new tuning flag for Neover

[gcc r15-1071] AArch64: correct constraint on Upl early clobber alternatives

https://gcc.gnu.org/g:afe85f8e22a703280b17c701f3490d89337f674a commit r15-1071-gafe85f8e22a703280b17c701f3490d89337f674a Author: Tamar Christina Date: Thu Jun 6 14:35:48 2024 +0100 AArch64: correct constraint on Upl early clobber alternatives I made an oversight in the previous pa

[gcc r15-4324] middle-end: support SLP early break

https://gcc.gnu.org/g:accb85345edb91368221fd07b74e74df427b7de0 commit r15-4324-gaccb85345edb91368221fd07b74e74df427b7de0 Author: Tamar Christina Date: Mon Oct 14 11:58:59 2024 +0100 middle-end: support SLP early break This patch introduces feature parity for early break int the SL

[gcc r15-4353] AArch64: re-enable memory access costing after SLP change.

https://gcc.gnu.org/g:a1540bb843fd1a3e87f50d3f713386eaae454d1c commit r15-4353-ga1540bb843fd1a3e87f50d3f713386eaae454d1c Author: Tamar Christina Date: Tue Oct 15 11:22:26 2024 +0100 AArch64: re-enable memory access costing after SLP change. While chasing down a costing difference

[gcc r15-4460] AArch64: support encoding integer immediates using floating point moves

https://gcc.gnu.org/g:87dc6b1992e7ee02e7a4a81c568754198c0f61f5 commit r15-4460-g87dc6b1992e7ee02e7a4a81c568754198c0f61f5 Author: Tamar Christina Date: Fri Oct 18 09:43:45 2024 +0100 AArch64: support encoding integer immediates using floating point moves This patch extends our imme

[gcc r15-4461] AArch64: use movi d0, #0 to clear SVE registers instead of mov z0.d, #0

https://gcc.gnu.org/g:453d3d90c374d3bb329f1431b7dfb8d0510a88b9 commit r15-4461-g453d3d90c374d3bb329f1431b7dfb8d0510a88b9 Author: Tamar Christina Date: Fri Oct 18 09:44:15 2024 +0100 AArch64: use movi d0, #0 to clear SVE registers instead of mov z0.d, #0 This patch changes SVE to u

[gcc r15-4463] middle-end: Fix GSI for gcond root [PR117140]

https://gcc.gnu.org/g:51291ad0f1f89a81de917110af96e019dcd5690c commit r15-4463-g51291ad0f1f89a81de917110af96e019dcd5690c Author: Tamar Christina Date: Fri Oct 18 10:37:28 2024 +0100 middle-end: Fix GSI for gcond root [PR117140] When finding the gsi to use for code of the root stat

[gcc r15-4459] AArch64: update testsuite to account for new zero moves

https://gcc.gnu.org/g:fc3507927768c3df425a0b5c0e4051eb8bb1ccf0 commit r15-4459-gfc3507927768c3df425a0b5c0e4051eb8bb1ccf0 Author: Tamar Christina Date: Fri Oct 18 09:42:46 2024 +0100 AArch64: update testsuite to account for new zero moves The patch series will adjust how zeros are

[gcc r15-4462] middle-end: Fix VEC_PERM_EXPR lowering since relaxation of vector sizes

https://gcc.gnu.org/g:55f898008ec8235897cf56c89f5599c3ec1bc963 commit r15-4462-g55f898008ec8235897cf56c89f5599c3ec1bc963 Author: Tamar Christina Date: Fri Oct 18 10:36:19 2024 +0100 middle-end: Fix VEC_PERM_EXPR lowering since relaxation of vector sizes In GCC 14 VEC_PERM_EXPR was

[gcc r15-4326] AArch64: rename the SVE2 psel intrinsics to psel_lane [PR116371]

https://gcc.gnu.org/g:306834b7f74ab61160f205e04f5bf35b71f9ec52 commit r15-4326-g306834b7f74ab61160f205e04f5bf35b71f9ec52 Author: Tamar Christina Date: Mon Oct 14 13:58:09 2024 +0100 AArch64: rename the SVE2 psel intrinsics to psel_lane [PR116371] The psel intrinsics. similar to th

[gcc r15-4327] simplify-rtx: Fix incorrect folding of shift and AND [PR117012]

https://gcc.gnu.org/g:be966baa353dfcc20b76b5a5586ab2494bb0a735 commit r15-4327-gbe966baa353dfcc20b76b5a5586ab2494bb0a735 Author: Tamar Christina Date: Mon Oct 14 14:00:25 2024 +0100 simplify-rtx: Fix incorrect folding of shift and AND [PR117012] The optimization added in r15-1047-

[gcc r15-4328] middle-end: copy STMT_VINFO_STRIDED_P when DR is replaced [PR116956]

https://gcc.gnu.org/g:ec3d3ea60a55f25a743a037adda7d10d03ca73b2 commit r15-4328-gec3d3ea60a55f25a743a037adda7d10d03ca73b2 Author: Tamar Christina Date: Mon Oct 14 14:01:24 2024 +0100 middle-end: copy STMT_VINFO_STRIDED_P when DR is replaced [PR116956] When move_dr copies a DR from

[gcc r14-10909] AArch64: backport Neoverse and Cortex CPU definitions

https://gcc.gnu.org/g:05d54bcdc5395a9d3df36c8b640579a0558c89f0 commit r14-10909-g05d54bcdc5395a9d3df36c8b640579a0558c89f0 Author: Tamar Christina Date: Fri Nov 8 18:12:32 2024 + AArch64: backport Neoverse and Cortex CPU definitions This is a conservative backport of a few core

[gcc r15-4802] middle-end: Lower all gconds during vector pattern matching [PR117176]

https://gcc.gnu.org/g:d2f9159cfe7ea904e6476cabefea0c6ac9532e29 commit r15-4802-gd2f9159cfe7ea904e6476cabefea0c6ac9532e29 Author: Tamar Christina Date: Thu Oct 31 12:50:23 2024 + middle-end: Lower all gconds during vector pattern matching [PR117176] I have been taking a look at

[gcc r15-3792] middle-end: Insert invariant instructions before the gsi [PR116812]

https://gcc.gnu.org/g:09892448ebd8c396a26b2c09ba71f1e5a8dc42d7 commit r15-3792-g09892448ebd8c396a26b2c09ba71f1e5a8dc42d7 Author: Tamar Christina Date: Mon Sep 23 11:45:43 2024 +0100 middle-end: Insert invariant instructions before the gsi [PR116812] The new invariant statements sh

[gcc r15-3767] aarch64: Take into account when VF is higher than known scalar iters

https://gcc.gnu.org/g:e84e5d034124c6733d3b36d8623c56090d4d17f7 commit r15-3767-ge84e5d034124c6733d3b36d8623c56090d4d17f7 Author: Tamar Christina Date: Sun Sep 22 13:34:10 2024 +0100 aarch64: Take into account when VF is higher than known scalar iters Consider low overhead loops li

[gcc r15-3768] middle-end: lower COND_EXPR into gimple form in vect_recog_bool_pattern

https://gcc.gnu.org/g:4150bcd205ebb60b949224758c05012c0dfab7a7 commit r15-3768-g4150bcd205ebb60b949224758c05012c0dfab7a7 Author: Tamar Christina Date: Sun Sep 22 13:38:49 2024 +0100 middle-end: lower COND_EXPR into gimple form in vect_recog_bool_pattern Currently the vectorizer ch

[gcc r15-3800] aarch64: store signing key and signing method in DWARF _Unwind_FrameState

https://gcc.gnu.org/g:f531673917e4f80ad51eda0d806f0479c501a907 commit r15-3800-gf531673917e4f80ad51eda0d806f0479c501a907 Author: Matthieu Longo Date: Mon Sep 23 15:03:30 2024 +0100 aarch64: store signing key and signing method in DWARF _Unwind_FrameState This patch is only a refac

[gcc r15-3802] libgcc: hide CIE and FDE data for DWARF architecture extensions behind a handler.

https://gcc.gnu.org/g:bdf41d627c13bc5f0dc676991f4513daa9d9ae36 commit r15-3802-gbdf41d627c13bc5f0dc676991f4513daa9d9ae36 Author: Matthieu Longo Date: Mon Sep 23 15:03:37 2024 +0100 libgcc: hide CIE and FDE data for DWARF architecture extensions behind a handler. This patch provid

[gcc r15-3801] aarch64: skip copy of RA state register into target context

https://gcc.gnu.org/g:ba3e597681b640f6f9a676ec4f6cd3ca3878cefc commit r15-3801-gba3e597681b640f6f9a676ec4f6cd3ca3878cefc Author: Matthieu Longo Date: Mon Sep 23 15:03:35 2024 +0100 aarch64: skip copy of RA state register into target context The RA state register is local to a fram

[gcc r15-3804] dwarf2: add hooks for architecture-specific CFIs

https://gcc.gnu.org/g:9e1c71bab50d51a1a8ec1a75080ffde6ca3d854c commit r15-3804-g9e1c71bab50d51a1a8ec1a75080ffde6ca3d854c Author: Matthieu Longo Date: Mon Sep 23 15:34:57 2024 +0100 dwarf2: add hooks for architecture-specific CFIs Architecture-specific CFI directives are currently

[gcc r15-3803] Rename REG_CFA_TOGGLE_RA_MANGLE to REG_CFA_NEGATE_RA_STATE

https://gcc.gnu.org/g:4068096fbf5aef65883a7492f4940cea85b39f40 commit r15-3803-g4068096fbf5aef65883a7492f4940cea85b39f40 Author: Matthieu Longo Date: Mon Sep 23 15:31:18 2024 +0100 Rename REG_CFA_TOGGLE_RA_MANGLE to REG_CFA_NEGATE_RA_STATE The current name REG_CFA_TOGGLE_RA_MANGLE

[gcc r15-3805] aarch64 testsuite: explain expectections for pr94515* tests

https://gcc.gnu.org/g:fb475d3f25943beffac8e9c0c78247bad75287a1 commit r15-3805-gfb475d3f25943beffac8e9c0c78247bad75287a1 Author: Matthieu Longo Date: Mon Sep 23 15:35:02 2024 +0100 aarch64 testsuite: explain expectections for pr94515* tests gcc/testsuite/ChangeLog:

[gcc r15-3806] dwarf2: store the RA state in CFI row

https://gcc.gnu.org/g:2b7971448f122317ed012586f9f73ccc0537deb2 commit r15-3806-g2b7971448f122317ed012586f9f73ccc0537deb2 Author: Matthieu Longo Date: Mon Sep 23 15:35:07 2024 +0100 dwarf2: store the RA state in CFI row On AArch64, the RA state informs the unwinder whether the retu

[gcc r15-3738] testsuite: Update commandline for PR116628.c to use neoverse-v2 [PR116628]

https://gcc.gnu.org/g:0189ab205aa86b8e67ae982294f0fe58aa9c4774 commit r15-3738-g0189ab205aa86b8e67ae982294f0fe58aa9c4774 Author: Tamar Christina Date: Fri Sep 20 17:01:39 2024 +0100 testsuite: Update commandline for PR116628.c to use neoverse-v2 [PR116628] The testcase for this te

[gcc r15-3739] AArch64: Define VECTOR_STORE_FLAG_VALUE.

https://gcc.gnu.org/g:33cb400b2e7266e65030869254366217e51494aa commit r15-3739-g33cb400b2e7266e65030869254366217e51494aa Author: Tamar Christina Date: Fri Sep 20 17:03:54 2024 +0100 AArch64: Define VECTOR_STORE_FLAG_VALUE. This defines VECTOR_STORE_FLAG_VALUE to CONST1_RTX for AAr

[gcc r15-3959] middle-end: check explicitly for external or constants when checking for loop invariant [PR116817]

https://gcc.gnu.org/g:87905f63a6521eef1f38082e2368e18c637ef092 commit r15-3959-g87905f63a6521eef1f38082e2368e18c637ef092 Author: Tamar Christina Date: Mon Sep 30 13:06:24 2024 +0100 middle-end: check explicitly for external or constants when checking for loop invariant [PR116817]

[gcc r14-10893] AArch64: rename the SVE2 psel intrinsics to psel_lane [PR116371]

https://gcc.gnu.org/g:97640e9632697b9f0ab31e4022d24d360d1ea2c9 commit r14-10893-g97640e9632697b9f0ab31e4022d24d360d1ea2c9 Author: Tamar Christina Date: Mon Oct 14 13:58:09 2024 +0100 AArch64: rename the SVE2 psel intrinsics to psel_lane [PR116371] The psel intrinsics. similar to t

[gcc r15-5791] AArch64: Suppress default options when march or mcpu used is not affected by it.

https://gcc.gnu.org/g:5b0e4ed3081e6648460661ff5013e9f03e318505 commit r15-5791-g5b0e4ed3081e6648460661ff5013e9f03e318505 Author: Tamar Christina Date: Fri Nov 29 13:01:11 2024 + AArch64: Suppress default options when march or mcpu used is not affected by it. This patch makes

[gcc r15-5585] middle-end:For multiplication try swapping operands when matching complex multiply [PR116463]

https://gcc.gnu.org/g:a9473f9c6f2d755d2eb79dbd30877e64b4bc6fc8 commit r15-5585-ga9473f9c6f2d755d2eb79dbd30877e64b4bc6fc8 Author: Tamar Christina Date: Thu Nov 21 15:10:24 2024 + middle-end:For multiplication try swapping operands when matching complex multiply [PR116463] This

[gcc r15-5745] middle-end: rework vectorizable_store to iterate over single index [PR117557]

https://gcc.gnu.org/g:1b3bff737b2d5a7dc0d5977b77200c785fc53f01 commit r15-5745-g1b3bff737b2d5a7dc0d5977b77200c785fc53f01 Author: Tamar Christina Date: Thu Nov 28 10:23:14 2024 + middle-end: rework vectorizable_store to iterate over single index [PR117557] The testcase

[gcc r14-11053] middle-end:For multiplication try swapping operands when matching complex multiply [PR116463]

https://gcc.gnu.org/g:f01f01f0ebf8f5207096cb9650354210d890fe0d commit r14-11053-gf01f01f0ebf8f5207096cb9650354210d890fe0d Author: Tamar Christina Date: Thu Nov 21 15:10:24 2024 + middle-end:For multiplication try swapping operands when matching complex multiply [PR116463] Thi

[gcc r15-6654] cfgexpand: Factor out getting the stack decl index

https://gcc.gnu.org/g:4b1a2878ba3241ec5c0a1bf05ff47bfcd09c3711 commit r15-6654-g4b1a2878ba3241ec5c0a1bf05ff47bfcd09c3711 Author: Andrew Pinski Date: Fri Nov 15 20:22:02 2024 -0800 cfgexpand: Factor out getting the stack decl index This is the first patch in improving this code.

[gcc r15-6656] cfgexpand: Handle integral vector types and constructors for scope conflicts [PR105769]

https://gcc.gnu.org/g:4f4722b0722ec343df70e5ec5fd9d5c682ff8149 commit r15-6656-g4f4722b0722ec343df70e5ec5fd9d5c682ff8149 Author: Andrew Pinski Date: Fri Nov 15 20:22:04 2024 -0800 cfgexpand: Handle integral vector types and constructors for scope conflicts [PR105769] This is an e

[gcc r15-6655] cfgexpand: Rewrite add_scope_conflicts_2 to use cache and look back further [PR111422]

https://gcc.gnu.org/g:0014a858a14b825818d6b557c3d5193f85790bde commit r15-6655-g0014a858a14b825818d6b557c3d5193f85790bde Author: Andrew Pinski Date: Fri Nov 15 20:22:03 2024 -0800 cfgexpand: Rewrite add_scope_conflicts_2 to use cache and look back further [PR111422] After fixing

[gcc r15-6657] perform affine fold to unsigned on non address expressions. [PR114932]

https://gcc.gnu.org/g:405c99c17210a58df1a237219e773e689f17 commit r15-6657-g405c99c17210a58df1a237219e773e689f17 Author: Tamar Christina Date: Mon Jan 6 17:52:14 2025 + perform affine fold to unsigned on non address expressions. [PR114932] When the patch for PR114074 w

[gcc r15-6597] AArch64: Implement four and eight chunk VLA concats [PR118272]

https://gcc.gnu.org/g:830bead4859cd00da87e1304ba249cf0d3eb5a5a commit r15-6597-g830bead4859cd00da87e1304ba249cf0d3eb5a5a Author: Tamar Christina Date: Mon Jan 6 09:24:36 2025 + AArch64: Implement four and eight chunk VLA concats [PR118272] The following testcase #pr

[gcc r15-7453] testsuite: Fix two testisms on x86 after PFA [PR118754]

https://gcc.gnu.org/g:aaf5f5027d3f29c6c0d836753dddac16ba94a49a commit r15-7453-gaaf5f5027d3f29c6c0d836753dddac16ba94a49a Author: Tamar Christina Date: Mon Feb 10 09:32:29 2025 + testsuite: Fix two testisms on x86 after PFA [PR118754] These two tests now vectorize the result fi

[gcc r15-7395] middle-end: Remove unused internal function after IVopts cleanup [PR118756]

https://gcc.gnu.org/g:8d19fbb2be487f19ed1c48699e17cafe19520525 commit r15-7395-g8d19fbb2be487f19ed1c48699e17cafe19520525 Author: Tamar Christina Date: Thu Feb 6 17:46:52 2025 + middle-end: Remove unused internal function after IVopts cleanup [PR118756] It seems that after my I

[gcc r13-9373] AArch64: Fix GCC 13 backport of big.Little CPU detection [PR118800]

https://gcc.gnu.org/g:fa5aedd841105329b2f65cb0ff418cb4427f255e commit r13-9373-gfa5aedd841105329b2f65cb0ff418cb4427f255e Author: Tamar Christina Date: Wed Feb 12 10:38:21 2025 + AArch64: Fix GCC 13 backport of big.Little CPU detection [PR118800] On the GCC-13 branch the backpo

[gcc r15-6109] middle-end: Add initial support for poly_int64 BIT_FIELD_REF in expand pass [PR96342]

https://gcc.gnu.org/g:b6242bd122757ec6c75c73a4921f24a9a382b090 commit r15-6109-gb6242bd122757ec6c75c73a4921f24a9a382b090 Author: Victor Do Nascimento Date: Wed Dec 11 12:00:58 2024 + middle-end: Add initial support for poly_int64 BIT_FIELD_REF in expand pass [PR96342] While `

[gcc r15-6108] middle-end: add vec_init support for variable length subvector concatenation. [PR96342]

https://gcc.gnu.org/g:d069eb91d5696a8642bd5fc44a6d47fd7f74d18b commit r15-6108-gd069eb91d5696a8642bd5fc44a6d47fd7f74d18b Author: Victor Do Nascimento Date: Wed Dec 11 12:00:09 2024 + middle-end: add vec_init support for variable length subvector concatenation. [PR96342] For a

[gcc r15-6104] middle-end: refactor type to be explicit in operand_equal_p [PR114932]

https://gcc.gnu.org/g:3c32575e5b6370270d38a80a7fa8eaa144e083d0 commit r15-6104-g3c32575e5b6370270d38a80a7fa8eaa144e083d0 Author: Tamar Christina Date: Wed Dec 11 11:45:36 2024 + middle-end: refactor type to be explicit in operand_equal_p [PR114932] This is a refactoring with

[gcc r15-6105] middle-end: use two's complement equality when comparing IVs during candidate selection [PR114932]

https://gcc.gnu.org/g:9403b035befe3537c343f7430e321468c0f2c28b commit r15-6105-g9403b035befe3537c343f7430e321468c0f2c28b Author: Tamar Christina Date: Wed Dec 11 11:47:49 2024 + middle-end: use two's complement equality when comparing IVs during candidate selection [PR114932]

[gcc r15-6107] middle-end: Fix mask length arg in call to vect_get_loop_mask [PR96342]

https://gcc.gnu.org/g:240cbd2f26c0f1c1f83cfc3b69cc0271b56172e2 commit r15-6107-g240cbd2f26c0f1c1f83cfc3b69cc0271b56172e2 Author: Victor Do Nascimento Date: Wed Dec 11 11:58:55 2024 + middle-end: Fix mask length arg in call to vect_get_loop_mask [PR96342] When issuing multiple

[gcc r15-6106] middle-end: Pass stmt_vec_info to TARGET_SIMD_CLONE_USABLE [PR96342]

https://gcc.gnu.org/g:561ef7c8477ba58ea64de259af9c2d0870afd9d4 commit r15-6106-g561ef7c8477ba58ea64de259af9c2d0870afd9d4 Author: Andre Vieira Date: Wed Dec 11 11:50:22 2024 + middle-end: Pass stmt_vec_info to TARGET_SIMD_CLONE_USABLE [PR96342] This patch adds stmt_vec_info to

[gcc r15-6262] arm: fix bootstrap after MVE changes

https://gcc.gnu.org/g:7b5599dbd75fe1ee7d861d4cfc6ea655a126bef3 commit r15-6262-g7b5599dbd75fe1ee7d861d4cfc6ea655a126bef3 Author: Tamar Christina Date: Sun Dec 15 13:21:44 2024 + arm: fix bootstrap after MVE changes The recent commits for MVE on Saturday have broken armhf boots

[gcc r15-6217] AArch64: Set L1 data cache size according to size on CPUs

https://gcc.gnu.org/g:6a5a1b8175e07ff578204476cd5d8a071cbc commit r15-6217-g6a5a1b8175e07ff578204476cd5d8a071cbc Author: Tamar Christina Date: Fri Dec 13 11:20:18 2024 + AArch64: Set L1 data cache size according to size on CPUs This sets the L1 data cache size for some

[gcc r15-6216] AArch64: Add CMP+CSEL and CMP+CSET for cores that support it

https://gcc.gnu.org/g:4a9427f75b9f5dfbd9edd0ec8e0a07f868754b65 commit r15-6216-g4a9427f75b9f5dfbd9edd0ec8e0a07f868754b65 Author: Tamar Christina Date: Fri Dec 13 11:17:55 2024 + AArch64: Add CMP+CSEL and CMP+CSET for cores that support it GCC 15 added two new fusions CMP+CSEL

[gcc r15-6391] AArch64: Disable `omp declare variant' tests for aarch64 [PR96342]

https://gcc.gnu.org/g:6ecb365d4c3f36eaf684c38fc5d9008a1409c725 commit r15-6391-g6ecb365d4c3f36eaf684c38fc5d9008a1409c725 Author: Tamar Christina Date: Fri Dec 20 14:25:50 2024 + AArch64: Disable `omp declare variant' tests for aarch64 [PR96342] These tests are x86 specific and

[gcc r15-6392] AArch64: Add SVE support for simd clones [PR96342]

https://gcc.gnu.org/g:d7d3dfe7a2a26e370805ddf835bfd00c51d32f1b commit r15-6392-gd7d3dfe7a2a26e370805ddf835bfd00c51d32f1b Author: Tamar Christina Date: Fri Dec 20 14:27:25 2024 + AArch64: Add SVE support for simd clones [PR96342] This patch finalizes adding support for the gene

[gcc r15-6393] AArch64: Implement vector concat of partial SVE vectors [PR96342]

https://gcc.gnu.org/g:89b2c7dc96c4944c306131b665a4738a8a99413e commit r15-6393-g89b2c7dc96c4944c306131b665a4738a8a99413e Author: Tamar Christina Date: Fri Dec 20 14:34:32 2024 + AArch64: Implement vector concat of partial SVE vectors [PR96342] This patch adds support for vecto

[gcc r15-5565] middle-end: Pass along SLP node when costing vector loads/stores

https://gcc.gnu.org/g:dbc38dd9e96a9995298da2478041bdbbf247c479 commit r15-5565-gdbc38dd9e96a9995298da2478041bdbbf247c479 Author: Tamar Christina Date: Thu Nov 21 12:49:35 2024 + middle-end: Pass along SLP node when costing vector loads/stores With the support to SLP only we no

[gcc r15-6752] AArch64: Fix costing of emulated gathers/scatters [PR118188]

https://gcc.gnu.org/g:08b6e875c6b1b52c6e98f4a2e37124bf8c6a6ccb commit r15-6752-g08b6e875c6b1b52c6e98f4a2e37124bf8c6a6ccb Author: Tamar Christina Date: Thu Jan 9 21:31:05 2025 + AArch64: Fix costing of emulated gathers/scatters [PR118188] When a target does not support gathers

[gcc r14-11199] AArch64: correct Cortex-X4 MIDR

https://gcc.gnu.org/g:26f78a4249b051c7755a44ba1ab1743f4133b0c2 commit r14-11199-g26f78a4249b051c7755a44ba1ab1743f4133b0c2 Author: Tamar Christina Date: Fri Jan 10 21:33:57 2025 + AArch64: correct Cortex-X4 MIDR The Parts Num field for the MIDR for Cortex-X4 is wrong. It's cur

[gcc r15-7094] aarch64: Drop ILP32 from default elf multilibs after deprecation

https://gcc.gnu.org/g:9fd190c70976638eb8ae239f09d9f73da26d3021 commit r15-7094-g9fd190c70976638eb8ae239f09d9f73da26d3021 Author: Tamar Christina Date: Tue Jan 21 10:27:13 2025 + aarch64: Drop ILP32 from default elf multilibs after deprecation Following the deprecation of ILP32

[gcc r15-7018] AArch64: Use standard names for saturating arithmetic

https://gcc.gnu.org/g:aa361611490947eb228e5b625a3f0f23ff647dbd commit r15-7018-gaa361611490947eb228e5b625a3f0f23ff647dbd Author: Akram Ahmad Date: Fri Jan 17 17:43:49 2025 + AArch64: Use standard names for saturating arithmetic This renames the existing {s,u}q{add,sub} instruc

[gcc r15-7015] Revert "AArch64: Use standard names for SVE saturating arithmetic"

https://gcc.gnu.org/g:8787f63de6e51bc43f86bb08c8a5f4a370246a90 commit r15-7015-g8787f63de6e51bc43f86bb08c8a5f4a370246a90 Author: Tamar Christina Date: Sat Jan 18 11:12:35 2025 + Revert "AArch64: Use standard names for SVE saturating arithmetic" This reverts commit 26b2d9f27ca2

[gcc r15-7016] Revert "AArch64: Use standard names for saturating arithmetic"

https://gcc.gnu.org/g:1775a7280a230776927897147f1b07964cf5cfc7 commit r15-7016-g1775a7280a230776927897147f1b07964cf5cfc7 Author: Tamar Christina Date: Sat Jan 18 11:12:38 2025 + Revert "AArch64: Use standard names for saturating arithmetic" This reverts commit 5f5833a4107ddfbc

[gcc r15-7017] AArch64: Use standard names for SVE saturating arithmetic

https://gcc.gnu.org/g:8f8ca83f2f6f165c4060ee1fc18ed3c74571ab7a commit r15-7017-g8f8ca83f2f6f165c4060ee1fc18ed3c74571ab7a Author: Akram Ahmad Date: Fri Jan 17 17:44:23 2025 + AArch64: Use standard names for SVE saturating arithmetic Rename the existing SVE unpredicated saturati

[gcc r13-9351] AArch64: have -mcpu=native detect architecture extensions for unknown non-homogenous systems [PR1132

https://gcc.gnu.org/g:eb45b829bb3fb658aa34a340264dee9755d34e69 commit r13-9351-geb45b829bb3fb658aa34a340264dee9755d34e69 Author: Tamar Christina Date: Thu Jan 16 19:25:26 2025 + AArch64: have -mcpu=native detect architecture extensions for unknown non-homogenous systems [PR113257]

[gcc r13-9352] AArch64: don't override march to assembler with mcpu if march is specified [PR110901]

https://gcc.gnu.org/g:57a9595f05efe2839a39e711c6cf3ce21ca1ff33 commit r13-9352-g57a9595f05efe2839a39e711c6cf3ce21ca1ff33 Author: Tamar Christina Date: Thu Jan 16 19:23:50 2025 + AArch64: don't override march to assembler with mcpu if march is specified [PR110901] When both -m

[gcc r14-11255] AArch64: don't override march to assembler with mcpu if march is specified [PR110901]

https://gcc.gnu.org/g:f8daec2ad9a20c31a98efb4602080e1e5d0c19fe commit r14-11255-gf8daec2ad9a20c31a98efb4602080e1e5d0c19fe Author: Tamar Christina Date: Thu Jan 16 19:23:50 2025 + AArch64: don't override march to assembler with mcpu if march is specified [PR110901] When both -

[gcc r14-11254] AArch64: have -mcpu=native detect architecture extensions for unknown non-homogenous systems [PR1132

https://gcc.gnu.org/g:7c6fde4bac6c20e0b04c3feb820abe5ce0e48d9b commit r14-11254-g7c6fde4bac6c20e0b04c3feb820abe5ce0e48d9b Author: Tamar Christina Date: Thu Jan 16 19:25:26 2025 + AArch64: have -mcpu=native detect architecture extensions for unknown non-homogenous systems [PR113257]

[gcc r15-7095] middle-end: use ncopies both when registering and reading masks [PR118273]

https://gcc.gnu.org/g:1dd79f44dfb64b441f3d6c64e7f909d73441bd05 commit r15-7095-g1dd79f44dfb64b441f3d6c64e7f909d73441bd05 Author: Tamar Christina Date: Tue Jan 21 10:29:08 2025 + middle-end: use ncopies both when registering and reading masks [PR118273] When registering masks f

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