[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] Déplacement shift descriptor vers gfc_conv_array_parameter

https://gcc.gnu.org/g:877f897ec3921f1a326ca8ad21a44a962c917239 commit 877f897ec3921f1a326ca8ad21a44a962c917239 Author: Mikael Morin Date: Tue Dec 17 17:27:24 2024 +0100 Déplacement shift descriptor vers gfc_conv_array_parameter Suppression variables inutilisées Diff: --- gcc/for

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Generate -mcpu and -mtune options from riscv-cores.def.

https://gcc.gnu.org/g:29d6dcedb37718f03c88cecdad7a27ae15246be9 commit 29d6dcedb37718f03c88cecdad7a27ae15246be9 Author: Dongyan Chen Date: Wed Jun 25 21:20:25 2025 +0800 RISC-V: Generate -mcpu and -mtune options from riscv-cores.def. Automatically generate -mcpu and -mtune options

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add new operand constraint: cR

https://gcc.gnu.org/g:94b41ed01f858cf424de65f7b5a7263609024e0c commit 94b41ed01f858cf424de65f7b5a7263609024e0c Author: Kito Cheng Date: Mon May 12 14:36:07 2025 +0800 RISC-V: Add new operand constraint: cR This commit introduces a new operand constraint `cR` for the RISC-V arc

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add patterns for vector-scalar negate-(multiply-add/sub) [PR119100]

https://gcc.gnu.org/g:3d456460f57ce3ecab003cb3efe0825c82aa937e commit 3d456460f57ce3ecab003cb3efe0825c82aa937e Author: Paul-Antoine Arras Date: Wed Jun 4 14:51:17 2025 +0200 RISC-V: Add patterns for vector-scalar negate-(multiply-add/sub) [PR119100] This pattern enables the combin

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix gcc.target/riscv/predef-19.c [PR120054]

https://gcc.gnu.org/g:1994653203e4d2e170f432fd82db18557e84ebf5 commit 1994653203e4d2e170f432fd82db18557e84ebf5 Author: Kito Cheng Date: Mon May 5 10:08:22 2025 +0800 RISC-V: Fix gcc.target/riscv/predef-19.c [PR120054] gcc/testsuite/ChangeLog: PR target/120054

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] Refactoring shift descriptor

https://gcc.gnu.org/g:6441e6b2c681e53cda4aeedb1845648683c5449e commit 6441e6b2c681e53cda4aeedb1845648683c5449e Author: Mikael Morin Date: Wed Aug 13 14:02:37 2025 +0200 Refactoring shift descriptor Correction pr85938 Correction régression associate_33 Correction

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] Suppression gfc_conv_descriptor_dtype compil' OK

https://gcc.gnu.org/g:92a5839ef2d3b1a6f275d3f5a87fb25d542f35d0 commit 92a5839ef2d3b1a6f275d3f5a87fb25d542f35d0 Author: Mikael Morin Date: Sat Jun 28 23:09:22 2025 +0200 Suppression gfc_conv_descriptor_dtype compil' OK Suppression non_lvalue dtype_get Ajout location descri

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] Modif implémentation descriptor_extent_get

https://gcc.gnu.org/g:cc2084b11fecbda8f341b906cb72ed329f115e8b commit cc2084b11fecbda8f341b906cb72ed329f115e8b Author: Mikael Morin Date: Sat Sep 6 17:37:52 2025 +0200 Modif implémentation descriptor_extent_get Diff: --- gcc/fortran/trans-descriptor.cc | 4 ++-- 1 file changed, 2 inserti

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Disable uint128_t testcase of SAT_MUL when rv32

https://gcc.gnu.org/g:1ce0e5264d9307fb434dab5ed546d78aa850db38 commit 1ce0e5264d9307fb434dab5ed546d78aa850db38 Author: Pan Li Date: Tue Jul 8 10:46:29 2025 +0800 RISC-V: Disable uint128_t testcase of SAT_MUL when rv32 The rv32 doesn't support __uint128, and then we will have e

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: frm/mode-switch: Reduce FRM restores on DYN transition [PR119164]

https://gcc.gnu.org/g:bdc040400d41097afb0bd45a8c31daf152409be8 commit bdc040400d41097afb0bd45a8c31daf152409be8 Author: Vineet Gupta Date: Sun Jun 8 14:55:01 2025 -0700 RISC-V: frm/mode-switch: Reduce FRM restores on DYN transition [PR119164] FRM mode switching state machine has DY

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/120642] Avoid propagating constant AVL for theadvector

https://gcc.gnu.org/g:309d5527b5bf0fc1d437d1e407dd5c7131db787f commit 309d5527b5bf0fc1d437d1e407dd5c7131db787f Author: Jeff Law Date: Wed Jul 9 05:23:34 2025 -0600 [RISC-V][PR target/120642] Avoid propagating constant AVL for theadvector AVL propagation currently assumes that it c

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vrem.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:a5251de6f9dc54f833adf9c482d988ee43dea129 commit a5251de6f9dc54f833adf9c482d988ee43dea129 Author: Pan Li Date: Sun Jun 8 16:55:34 2025 +0800 RISC-V: Add test for vec_duplicate + vrem.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check test for vec

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] Extraction set_descriptor_with_shape

https://gcc.gnu.org/g:616fc48e8ef5bcc318f472f2219e0e045a1ff055 commit 616fc48e8ef5bcc318f472f2219e0e045a1ff055 Author: Mikael Morin Date: Sun Aug 17 19:28:04 2025 +0200 Extraction set_descriptor_with_shape Diff: --- gcc/fortran/trans-descriptor.cc | 110 ++

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add Profiles RVA/B23S64 support.

https://gcc.gnu.org/g:43656c22fdb2fd12c1a15e15df752e6b3050f37a commit 43656c22fdb2fd12c1a15e15df752e6b3050f37a Author: Jiawei Date: Tue Jun 24 17:34:05 2025 +0800 RISC-V: Add Profiles RVA/B23S64 support. This patch adds support for the RISC-V Profiles RVA23S64 and RVB23S64.

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_dup + vmax.vv combine case 1 with max func 0 and GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:662a9268285c456e675d62424984bbc7c09f48fd commit 662a9268285c456e675d62424984bbc7c09f48fd Author: Pan Li Date: Thu Jun 12 10:23:49 2025 +0800 RISC-V: Add test for vec_dup + vmax.vv combine case 1 with max func 0 and GR2VR cost 0, 1 and 2 Add asm dump check te

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] Extraction gfc_set_gfc_from_cfi

https://gcc.gnu.org/g:be565a7a832f44d519574651565b2292a008 commit be565a7a832f44d519574651565b2292a008 Author: Mikael Morin Date: Tue Jul 22 12:17:50 2025 +0200 Extraction gfc_set_gfc_from_cfi Diff: --- gcc/fortran/trans-descriptor.cc | 99

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Use helper function to get FPR to VR move cost

https://gcc.gnu.org/g:861d77124cb29570b96a8dfa4e5d6ad19ef5f246 commit 861d77124cb29570b96a8dfa4e5d6ad19ef5f246 Author: Paul-Antoine Arras Date: Wed May 28 12:09:22 2025 +0200 RISC-V: Use helper function to get FPR to VR move cost Since last patch introduced get_fr2vr_cost () to ge

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] gimple-simulate: Correction ICE MEM_REF avec offset négatif

https://gcc.gnu.org/g:8e155f7ca562bcf865e06959777a5a81edd7751b commit 8e155f7ca562bcf865e06959777a5a81edd7751b Author: Mikael Morin Date: Fri Aug 29 11:24:15 2025 +0200 gimple-simulate: Correction ICE MEM_REF avec offset négatif Diff: --- gcc/gimple-simulate.cc | 53 +

[gcc r14-12001] libstdc++: Make CTAD ignore pair(const T1&, const T2&) constructor [PR110853]

https://gcc.gnu.org/g:98c53d4494eb38778c95414228625d2ed5a495e3 commit r14-12001-g98c53d4494eb38778c95414228625d2ed5a495e3 Author: Jonathan Wakely Date: Tue Sep 2 22:30:46 2025 +0100 libstdc++: Make CTAD ignore pair(const T1&, const T2&) constructor [PR110853] For the pair(T1, T2)

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] gimple-simulate: Prise en charge VIEW_CONVERT_EXPR

https://gcc.gnu.org/g:d9c71b3ba1f66edb0d67fec1cf49c9cb8298536b commit d9c71b3ba1f66edb0d67fec1cf49c9cb8298536b Author: Mikael Morin Date: Tue Jul 29 11:06:05 2025 +0200 gimple-simulate: Prise en charge VIEW_CONVERT_EXPR Diff: --- gcc/gimple-simulate.cc | 49 ++

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] Modif gfc_init_descriptor_variable

https://gcc.gnu.org/g:a1964fd4cc62df52daf8c4d99a6dadf7903fa170 commit a1964fd4cc62df52daf8c4d99a6dadf7903fa170 Author: Mikael Morin Date: Sat Jul 19 15:55:19 2025 +0200 Modif gfc_init_descriptor_variable Diff: --- gcc/fortran/trans-descriptor.cc | 19 +-- 1 file changed,

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] Déplacement gfc_array_init_count -> gfc_descriptor_init_count

https://gcc.gnu.org/g:6d9ca3056a95456cb8b796818bde13a789525341 commit 6d9ca3056a95456cb8b796818bde13a789525341 Author: Mikael Morin Date: Thu Jul 31 16:51:20 2025 +0200 Déplacement gfc_array_init_count -> gfc_descriptor_init_count Diff: --- gcc/fortran/trans-array.cc | 301 ++---

[gcc r16-3618] RISC-V: Add support for the XAndesvbfhcvt ISA extension.

https://gcc.gnu.org/g:726006cd69144591e2c2fd36720b50054d950d04 commit r16-3618-g726006cd69144591e2c2fd36720b50054d950d04 Author: Kuan-Lin Chen Date: Sat Sep 6 12:29:36 2025 -0600 RISC-V: Add support for the XAndesvbfhcvt ISA extension. This patch add support for XAndesvbfhcvt ISA

[gcc r16-3600] libstdc++: Document missing implementation defined behavior for std::filesystem.

https://gcc.gnu.org/g:d6c370b8e96d43448537276d91c2b33fedb9754a commit r16-3600-gd6c370b8e96d43448537276d91c2b33fedb9754a Author: Tomasz Kamiński Date: Fri Sep 5 13:16:40 2025 +0200 libstdc++: Document missing implementation defined behavior for std::filesystem. libstdc++-v3/Chang

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH v5] RISC-V: Mips P8700 Conditional Move Support.

https://gcc.gnu.org/g:c2f5b9890e471882c8d78cd07861db28c5613ba3 commit c2f5b9890e471882c8d78cd07861db28c5613ba3 Author: Umesh Kalappa Date: Tue Jul 15 10:35:44 2025 -0600 [PATCH v5] RISC-V: Mips P8700 Conditional Move Support. Updated the test for rv32 accordingly and no regress fo

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Rename VX_BINARY test helper to VX_BINARY_CASE_0

https://gcc.gnu.org/g:8b149fb91b6d92e87684f5c6e6a9ba67faec07c9 commit 8b149fb91b6d92e87684f5c6e6a9ba67faec07c9 Author: Pan Li Date: Wed May 7 20:48:40 2025 +0800 RISC-V: Rename VX_BINARY test helper to VX_BINARY_CASE_0 This patch would like to rename the VX_BINARY within CASE_0 su

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] Déplacement shift descriptor vers gfc_conv_array_parameter

https://gcc.gnu.org/g:877f897ec3921f1a326ca8ad21a44a962c917239 commit 877f897ec3921f1a326ca8ad21a44a962c917239 Author: Mikael Morin Date: Tue Dec 17 17:27:24 2024 +0100 Déplacement shift descriptor vers gfc_conv_array_parameter Suppression variables inutilisées Diff: --- gcc/for

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] Introduction gfc_symbol_attr

https://gcc.gnu.org/g:5009dd11e2f8cd0e8b8517ff0c23c3191355facd commit 5009dd11e2f8cd0e8b8517ff0c23c3191355facd Author: Mikael Morin Date: Thu Jul 17 16:38:25 2025 +0200 Introduction gfc_symbol_attr Ajout déclaration gfc_symbol_attr Diff: --- gcc/fortran/gfortran.h | 1 + gcc/fo

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] Factorisation shift_dimension_fields/set_dimension_fields gfc_set_temporaray_descriptor

https://gcc.gnu.org/g:67666efc1f2d122dd258c27349c9c92d0075df5d commit 67666efc1f2d122dd258c27349c9c92d0075df5d Author: Mikael Morin Date: Sat Aug 16 18:41:13 2025 +0200 Factorisation shift_dimension_fields/set_dimension_fields gfc_set_temporaray_descriptor Correction utilisation

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support RISC-V Profiles 23.

https://gcc.gnu.org/g:bf80965a0fbab2d4ef67ed1e140a54de5893fdc7 commit bf80965a0fbab2d4ef67ed1e140a54de5893fdc7 Author: Jiawei Date: Sat May 10 19:26:35 2025 +0800 RISC-V: Support RISC-V Profiles 23. This patch introduces support for RISC-V Profiles RV23A and RV23B [1], enablin

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] Suppression set_dtype_if_unallocated

https://gcc.gnu.org/g:93dbd09fceb543ca2474efcc6d4fcc68b33f8eeb commit 93dbd09fceb543ca2474efcc6d4fcc68b33f8eeb Author: Mikael Morin Date: Sun Aug 10 11:03:57 2025 +0200 Suppression set_dtype_if_unallocated Extraction gfc_descriptor_set_dtype_if_unallocated Sauvegarde

[gcc r15-10289] AVR: target/121794 - Invoke zero_reg less.

https://gcc.gnu.org/g:be6142b9edfe1e496b7e5f2be0eeb438ef7d3050 commit r15-10289-gbe6142b9edfe1e496b7e5f2be0eeb438ef7d3050 Author: Georg-Johann Lay Date: Thu Sep 4 22:03:31 2025 +0200 AVR: target/121794 - Invoke zero_reg less. There are some cases where involing zero_reg is not nee

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] Refactoring nullifcations descripteur

https://gcc.gnu.org/g:c877f3484854b0016d04865d8d170a6d04ab9da9 commit c877f3484854b0016d04865d8d170a6d04ab9da9 Author: Mikael Morin Date: Sun Aug 10 18:30:59 2025 +0200 Refactoring nullifcations descripteur Revert partiel Diff: --- gcc/fortran/trans-descriptor.cc | 104 +

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Leverage vaadd.vv for signed standard name avg_ceil

https://gcc.gnu.org/g:14401c7cbe6e5625d92d1cff7a3e1de5eebc0c29 commit 14401c7cbe6e5625d92d1cff7a3e1de5eebc0c29 Author: Pan Li Date: Thu May 29 21:19:36 2025 +0800 RISC-V: Leverage vaadd.vv for signed standard name avg_ceil The avg_ceil has the rounding mode towards +inf, while the

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] Déplacement fonctions descripteur vers fichier séparé

https://gcc.gnu.org/g:5450a7e6f901fa3e502de1f79d7d2c81d750b4f9 commit 5450a7e6f901fa3e502de1f79d7d2c81d750b4f9 Author: Mikael Morin Date: Wed Jun 18 17:31:23 2025 +0200 Déplacement fonctions descripteur vers fichier séparé Suppression déclarations trans-array.h Inclusion

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] Extraction gfc_set_descriptor

https://gcc.gnu.org/g:f1bc70e891099b9cdbaaba8af0cf95d27b3ddc9f commit f1bc70e891099b9cdbaaba8af0cf95d27b3ddc9f Author: Mikael Morin Date: Sun Jul 20 17:25:26 2025 +0200 Extraction gfc_set_descriptor Correction bootstsrap Diff: --- gcc/fortran/trans-array.cc | 163 +-

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] Suppression gfc_conv_descriptor_elem_len compil' OK

https://gcc.gnu.org/g:ba4116cd86df6cbba0c937041a4e1a703b4ed2dc commit ba4116cd86df6cbba0c937041a4e1a703b4ed2dc Author: Mikael Morin Date: Sun Jun 29 12:40:53 2025 +0200 Suppression gfc_conv_descriptor_elem_len compil' OK Correction ICE class_allocate_21 Suppression non_lv

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] Suppression déclarations inutiles

https://gcc.gnu.org/g:b1a510366648be49c6542111ec65570937ed1268 commit b1a510366648be49c6542111ec65570937ed1268 Author: Mikael Morin Date: Thu Jul 31 17:50:45 2025 +0200 Suppression déclarations inutiles Diff: --- gcc/fortran/trans-descriptor.h | 7 --- 1 file changed, 7 deletions(-)

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] gimple-simulate: Correction ICE évaluation adresse

https://gcc.gnu.org/g:99b340b9b4c521a851be450024c2d015f2b7b4f0 commit 99b340b9b4c521a851be450024c2d015f2b7b4f0 Author: Mikael Morin Date: Fri Aug 29 17:10:53 2025 +0200 gimple-simulate: Correction ICE évaluation adresse Diff: --- gcc/gimple-simulate.cc | 26 -- gc

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Update Profiles string in RV23.

https://gcc.gnu.org/g:0deb969b3d12fb992b402213ff422880a864328b commit 0deb969b3d12fb992b402213ff422880a864328b Author: Jiawei Date: Mon Jun 16 11:21:29 2025 +0800 RISC-V: Update Profiles string in RV23. Add b-ext in RVA/B23 as independent extension flags and add supm in RVA23.

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix line too long format issue for autovect.md [NFC]

https://gcc.gnu.org/g:f8dc9eaa21d4c9e64a9e3d817ef503910668cc71 commit f8dc9eaa21d4c9e64a9e3d817ef503910668cc71 Author: Pan Li Date: Sat May 31 11:01:06 2025 +0800 RISC-V: Fix line too long format issue for autovect.md [NFC] Inspired by the avg_ceil patches, notice there were even

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Minimal support for sdtrig and ssstrict extensions.

https://gcc.gnu.org/g:77d826d89b28dcf164cee3f2449708b3d781bede commit 77d826d89b28dcf164cee3f2449708b3d781bede Author: Dongyan Chen Date: Tue May 6 17:09:54 2025 -0600 [PATCH] RISC-V: Minimal support for sdtrig and ssstrict extensions. This patch support sdtrig and ssstrict extens

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support -mcpu for XiangShan Kunminghu cpu.

https://gcc.gnu.org/g:be55f311e6c0b27717a594f8020c702446430d4e commit be55f311e6c0b27717a594f8020c702446430d4e Author: Jiawei Date: Wed Jun 4 17:56:49 2025 +0800 RISC-V: Support -mcpu for XiangShan Kunminghu cpu. This patch adds support for the XiangShan Kunminghu CPU in GCC, allo

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Don't use structured binding in riscv-common.cc

https://gcc.gnu.org/g:29b74ceea2303031167fb1f649c5258d83b0a86e commit 29b74ceea2303031167fb1f649c5258d83b0a86e Author: Kito Cheng Date: Thu Jun 5 15:23:59 2025 +0800 RISC-V: Don't use structured binding in riscv-common.cc It's new C++ language feature introduced in C++17, which is

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] Extraction gfc_set_descriptor

https://gcc.gnu.org/g:3ed0bd817ff5a48de51a37237002dffb78dd088f commit 3ed0bd817ff5a48de51a37237002dffb78dd088f Author: Mikael Morin Date: Sun Jul 20 17:25:26 2025 +0200 Extraction gfc_set_descriptor Correction bootstsrap Diff: --- gcc/fortran/trans-array.cc | 163 +-

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR middle-end/114512] Recognize more bext idioms for RISC-V

https://gcc.gnu.org/g:542172132870370e2632e140a9db752d1e0d8d25 commit 542172132870370e2632e140a9db752d1e0d8d25 Author: Shreya Munnangi Date: Tue May 6 06:38:00 2025 -0600 [RISC-V][PR middle-end/114512] Recognize more bext idioms for RISC-V This is Shreya's next chunk of work. Whe

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test cases for unsigned scalar SAT_MUL from uint128_t

https://gcc.gnu.org/g:dc190f0dd828776e5a180fe87c1a55a1872e525f commit dc190f0dd828776e5a180fe87c1a55a1872e525f Author: Pan Li Date: Wed Jul 2 10:52:25 2025 +0800 RISC-V: Add test cases for unsigned scalar SAT_MUL from uint128_t Add run and tree-optimized check for unsigned scalar

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions.

https://gcc.gnu.org/g:670347187ac7a973395d4bdb964533d32bebf6ff commit 670347187ac7a973395d4bdb964533d32bebf6ff Author: yulong Date: Tue Apr 29 21:12:03 2025 +0800 RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions. This commit adds testcases for Xsfvcp. Co-Auth

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] Suppression déclarations inutiles

https://gcc.gnu.org/g:6a96de713f0c6fb56c290d5235a1fd0f54e1c80a commit 6a96de713f0c6fb56c290d5235a1fd0f54e1c80a Author: Mikael Morin Date: Thu Jul 31 17:50:45 2025 +0200 Suppression déclarations inutiles Diff: --- gcc/fortran/trans-descriptor.h | 7 --- 1 file changed, 7 deletions(-)

[gcc r15-10287] c++/modules: Mark implicit inline namespaces as purview [PR121724]

https://gcc.gnu.org/g:597bc675e6f5392caee0c423b9a6c5c1b8e93db5 commit r15-10287-g597bc675e6f5392caee0c423b9a6c5c1b8e93db5 Author: Nathaniel Shead Date: Mon Sep 1 21:28:03 2025 +1000 c++/modules: Mark implicit inline namespaces as purview [PR121724] When we push an existing namespa

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Avoid unnecessary andi with -1 argument

https://gcc.gnu.org/g:08824bb65a7853216dc052b8cc5223fc1d285158 commit 08824bb65a7853216dc052b8cc5223fc1d285158 Author: Jeff Law Date: Tue May 6 19:20:14 2025 -0600 [RISC-V] Avoid unnecessary andi with -1 argument I was preparing to do some testing of Shreya's next patch on spec an

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Refine the test case for vector avg_floor and avg_ceil [NFC]

https://gcc.gnu.org/g:bf8d760727f28467a6e784f6a96feeef2b040537 commit bf8d760727f28467a6e784f6a96feeef2b040537 Author: Pan Li Date: Sat Jul 19 10:49:15 2025 +0800 RISC-V: Refine the test case for vector avg_floor and avg_ceil [NFC] The previous test case doesn't leverage the right

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vsaddu.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:7e4c07d969079f214e010d599d0114625e4de556 commit 7e4c07d969079f214e010d599d0114625e4de556 Author: Pan Li Date: Sat Jun 21 10:07:38 2025 +0800 RISC-V: Add test for vec_duplicate + vsaddu.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check test for

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Improve signed division by 2^n

https://gcc.gnu.org/g:2aad5eeb28ae9a3df77d51fa7ecfabb2bd9206d1 commit 2aad5eeb28ae9a3df77d51fa7ecfabb2bd9206d1 Author: Jeff Law Date: Thu Jun 5 16:58:45 2025 -0600 [RISC-V] Improve signed division by 2^n So another class of cases where we can do better than a zicond sequence. Li

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vremu.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:391daf5eb23a8b71c34c4513a9c3ba3cd90e51cb commit 391daf5eb23a8b71c34c4513a9c3ba3cd90e51cb Author: Pan Li Date: Mon Jun 9 16:35:47 2025 +0800 RISC-V: Add test for vec_duplicate + vremu.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check test for ve

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Extract vec_duplicate for expand_const_vector [NFC]

https://gcc.gnu.org/g:afd28fe83706ed263b0105f155c98a4d5672aaba commit afd28fe83706ed263b0105f155c98a4d5672aaba Author: Pan Li Date: Wed Apr 16 11:16:21 2025 +0800 RISC-V: Extract vec_duplicate for expand_const_vector [NFC] Consider the expand_const_vector is quit long (about 500 l

[gcc r14-12000] libstdc++: Fix std::get for std::pair with reference members [PR121745]

https://gcc.gnu.org/g:72c9a10d700e5f4297aed523a79b0d7dc633f14e commit r14-12000-g72c9a10d700e5f4297aed523a79b0d7dc633f14e Author: Jonathan Wakely Date: Mon Sep 1 18:12:27 2025 +0100 libstdc++: Fix std::get for std::pair with reference members [PR121745] Make the std::get overloads

[gcc r16-3607] RISC-V: Check if we can vec_extract [PR121510].

https://gcc.gnu.org/g:a6bf07653cd272add46a2218ec141c95d7f02427 commit r16-3607-ga6bf07653cd272add46a2218ec141c95d7f02427 Author: Robin Dapp Date: Fri Sep 5 09:35:46 2025 +0200 RISC-V: Check if we can vec_extract [PR121510]. For Zvfhmin a vector mode exists but the corresponding ve

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add augmented hypervisor series extensions.

https://gcc.gnu.org/g:5c9c74c067ae4dc9df9fb61a48b691dc893bba7e commit 5c9c74c067ae4dc9df9fb61a48b691dc893bba7e Author: Jiawei Date: Tue May 13 15:23:39 2025 +0800 RISC-V: Add augmented hypervisor series extensions. The augmented hypervisor series extensions 'sha'[1] is a new profi

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [riscv] vec_dup immediate constants in pred_broadcast expand [PR118182]

https://gcc.gnu.org/g:2844769b933fa6779761771d95f5f5ba15f69f3f commit 2844769b933fa6779761771d95f5f5ba15f69f3f Author: Alexandre Oliva Date: Mon Apr 21 22:48:55 2025 -0300 [riscv] vec_dup immediate constants in pred_broadcast expand [PR118182] pr118182-2.c fails on gcc-14 because

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] gimple-simulate: Correction ICE extraction ref avec padding

https://gcc.gnu.org/g:d8608d4bdeefce8e994be9b37cf94181dbb64580 commit d8608d4bdeefce8e994be9b37cf94181dbb64580 Author: Mikael Morin Date: Fri Aug 29 14:38:54 2025 +0200 gimple-simulate: Correction ICE extraction ref avec padding Diff: --- gcc/gimple-simulate.cc | 112

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] fortran: Factor array descriptor references

https://gcc.gnu.org/g:42d8ec73b53ae0bece9585d71dba91276a4a8b43 commit 42d8ec73b53ae0bece9585d71dba91276a4a8b43 Author: Mikael Morin Date: Wed Jul 9 21:18:18 2025 +0200 fortran: Factor array descriptor references Regression tested on x86_64-pc-linux-gnu. OK for master?

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] Initialisation shifted offset en partant de zero

https://gcc.gnu.org/g:57d5e98eba9dfaaa07923e11b35a3032c2b70867 commit 57d5e98eba9dfaaa07923e11b35a3032c2b70867 Author: Mikael Morin Date: Thu Aug 14 11:59:54 2025 +0200 Initialisation shifted offset en partant de zero Suppression utilisation offset descripteur comme variable tempo

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vaaddu.vv combine case 1 with GR2VR cost 0, 1 and 2 for QI, HI

https://gcc.gnu.org/g:085bd579368604116cf37699044a524856ded103 commit 085bd579368604116cf37699044a524856ded103 Author: Pan Li Date: Mon Jul 21 09:16:17 2025 +0800 RISC-V: Add test for vec_duplicate + vaaddu.vv combine case 1 with GR2VR cost 0, 1 and 2 for QI, HI and SI mode Add a

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] fortran: Factor array descriptor references

https://gcc.gnu.org/g:736983d60bd44e5b8a78ea49fd04166a16fa51a8 commit 736983d60bd44e5b8a78ea49fd04166a16fa51a8 Author: Mikael Morin Date: Wed Jul 9 21:18:18 2025 +0200 fortran: Factor array descriptor references Regression tested on x86_64-pc-linux-gnu. OK for master?

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 1

https://gcc.gnu.org/g:cefa94fd32b0eb513966771987c24de5ebf5df2d commit cefa94fd32b0eb513966771987c24de5ebf5df2d Author: Pan Li Date: Sun May 11 16:31:16 2025 +0800 RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 1 Add asm dump check test for vec_duplica

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcase for unsigned scalar SAT_ADD form 8 and form 9

https://gcc.gnu.org/g:8c6025fff4ab0b20ef85e48c2873cb27e6446cc6 commit 8c6025fff4ab0b20ef85e48c2873cb27e6446cc6 Author: panciyan Date: Mon Jul 21 01:41:31 2025 + RISC-V: Add testcase for unsigned scalar SAT_ADD form 8 and form 9 This patch adds testcase for form8 and form9, as

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/119865] Don't free ggc allocated memory

https://gcc.gnu.org/g:197624427619862d76620a15e99c504bb2e2b7bd commit 197624427619862d76620a15e99c504bb2e2b7bd Author: Jeff Law Date: Sat Apr 19 12:35:29 2025 -0600 [RISC-V][PR target/119865] Don't free ggc allocated memory Kaiweng's patch to stop freeing riscv_arch_string was cor

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] Simplification initialisation offset remap descriptor

https://gcc.gnu.org/g:238146e371b8a6c067d8f4edf1b106c8fa069219 commit 238146e371b8a6c067d8f4edf1b106c8fa069219 Author: Mikael Morin Date: Sat Aug 16 15:13:04 2025 +0200 Simplification initialisation offset remap descriptor Modif initialisation stride Revert partiel initia

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vxor.vv to vxor.vx on GR2VR cost

https://gcc.gnu.org/g:3c6fad570b1b8740f01ce61001e81d96f4166af3 commit 3c6fad570b1b8740f01ce61001e81d96f4166af3 Author: Pan Li Date: Sun May 25 17:13:09 2025 +0800 RISC-V: Combine vec_duplicate + vxor.vv to vxor.vx on GR2VR cost This patch would like to combine the vec_duplicate +

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vmul.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:2de45c423a378eb3a475dde85a89bebde32d58f6 commit 2de45c423a378eb3a475dde85a89bebde32d58f6 Author: Pan Li Date: Wed May 28 16:20:32 2025 +0800 RISC-V: Add test for vec_duplicate + vmul.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check test for v

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] Fix invalid right shift count with recent ifcvt changes

https://gcc.gnu.org/g:9c276d4d191cf70db8b319758cfa96eccb72a487 commit 9c276d4d191cf70db8b319758cfa96eccb72a487 Author: Jeff Law Date: Sun Aug 24 19:55:44 2025 -0600 Fix invalid right shift count with recent ifcvt changes I got too clever trying to simplify the right shift computat

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] Extraction gfc_set_temporary_descriptor

https://gcc.gnu.org/g:9e77b2b4973d5086eb3e136ad175cb82cde3c945 commit 9e77b2b4973d5086eb3e136ad175cb82cde3c945 Author: Mikael Morin Date: Wed Jul 23 12:12:01 2025 +0200 Extraction gfc_set_temporary_descriptor Diff: --- gcc/fortran/trans-array.cc | 62 +---

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: testsuite: Fix vx_vf_*run-1-f16.c run tests.

https://gcc.gnu.org/g:05441fab56e7637c596832e4ca3be5a7f1abf76c commit 05441fab56e7637c596832e4ca3be5a7f1abf76c Author: Robin Dapp Date: Mon Jul 21 15:32:09 2025 +0200 RISC-V: testsuite: Fix vx_vf_*run-1-f16.c run tests. This patch fixes the vf_vfmacc-run-1-f16.c test failures on r

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support Smrnmi extension.

https://gcc.gnu.org/g:831aee1f4295cc351c298982febc7eb59bce2461 commit 831aee1f4295cc351c298982febc7eb59bce2461 Author: Jiawei Date: Thu Jun 5 11:24:43 2025 +0800 RISC-V: Support Smrnmi extension. Support the Smrnmi extension, which provides new CSRs for Machine mode Non-Maskab

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add support for resumable non-maskable interrupt (RNMI) handlers

https://gcc.gnu.org/g:2fecd9c2ef0c728ebe189132f3f42f7fda100a7f commit 2fecd9c2ef0c728ebe189132f3f42f7fda100a7f Author: Christoph Müllner Date: Thu Jul 24 23:08:40 2025 +0200 RISC-V: Add support for resumable non-maskable interrupt (RNMI) handlers The Smrnmi extension introduces th

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_dup + vmax.vv combine case 0 with max func 1 and GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:d115490bee92e9f6f4278a71ac4909c8190638ed commit d115490bee92e9f6f4278a71ac4909c8190638ed Author: Pan Li Date: Thu Jun 12 09:12:09 2025 +0800 RISC-V: Add test for vec_dup + vmax.vv combine case 0 with max func 1 and GR2VR cost 0, 2 and 15 Add asm dump check t

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vnmsac.vv signed combine with GR2VR cost 0, 1 and 15

https://gcc.gnu.org/g:a9a2a3ae5eeafdfc2dd94805ad0f63cc70875afa commit a9a2a3ae5eeafdfc2dd94805ad0f63cc70875afa Author: Pan Li Date: Thu Aug 28 10:36:35 2025 +0800 RISC-V: Add test for vec_duplicate + vnmsac.vv signed combine with GR2VR cost 0, 1 and 15 Add asm dump check and run

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vaaddu.vv to vaaddu.vx on GR2VR cost for HI, QI and SI mode

https://gcc.gnu.org/g:70954408240b4c269b0f5ab36393f03982557685 commit 70954408240b4c269b0f5ab36393f03982557685 Author: Pan Li Date: Mon Jul 21 09:06:52 2025 +0800 RISC-V: Combine vec_duplicate + vaaddu.vv to vaaddu.vx on GR2VR cost for HI, QI and SI mode This patch would like to

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] gimple-simulate: prise en charge __builtin_alloca_with_align

https://gcc.gnu.org/g:f15f2b6559acafcf46b874d8884e01dcb17e516d commit f15f2b6559acafcf46b874d8884e01dcb17e516d Author: Mikael Morin Date: Thu Aug 21 21:52:17 2025 +0200 gimple-simulate: prise en charge __builtin_alloca_with_align Diff: --- gcc/gimple-simulate.cc | 59

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Use riscv-ext.def to generate target options and variables

https://gcc.gnu.org/g:6dd0b1380ceaecd9e1a4e6cd347290c40cd5da11 commit 6dd0b1380ceaecd9e1a4e6cd347290c40cd5da11 Author: Kito Cheng Date: Wed May 7 18:28:18 2025 +0800 RISC-V: Use riscv-ext.def to generate target options and variables Leverage the centralized riscv-ext.def definitio

[gcc r16-3624] ipa: Fix build on MacOS

https://gcc.gnu.org/g:8ab5b7f590938a878845156a8da5f25731e9dff6 commit r16-3624-g8ab5b7f590938a878845156a8da5f25731e9dff6 Author: Simon Martin Date: Sat Sep 6 22:12:41 2025 +0200 ipa: Fix build on MacOS The build is broken on MacOS since r16-3581-g1da3c4d90e678a because ipa-inl

[gcc r16-3628] gcc: introduce the dep_fusion pass

https://gcc.gnu.org/g:41b0c7a674e87074fdc8088479cb93f6fe1e070f commit r16-3628-g41b0c7a674e87074fdc8088479cb93f6fe1e070f Author: Artemiy Volkov Date: Sat Sep 6 15:06:36 2025 -0600 gcc: introduce the dep_fusion pass Presently, the scheduler code only considers consecutive instructi

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] Suppression gfc_conv_descriptor_dimension compil' OK

https://gcc.gnu.org/g:d49656e0fc7106efa9379bcfd4369190f401625d commit d49656e0fc7106efa9379bcfd4369190f401625d Author: Mikael Morin Date: Sun Jun 29 14:28:16 2025 +0200 Suppression gfc_conv_descriptor_dimension compil' OK Suppression non_lvalue dimension_get ajout locatio

[gcc r16-3626] forwprop: Factor out the memcpy followed by memset optimization

https://gcc.gnu.org/g:8d381528c7894702d5000aa89c3da63833d4b3f5 commit r16-3626-g8d381528c7894702d5000aa89c3da63833d4b3f5 Author: Andrew Pinski Date: Sat Sep 6 04:04:37 2025 -0700 forwprop: Factor out the memcpy followed by memset optimization As simplify_builtin_call adds more and

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] Mise à jour offset & span dans gfc_array_init_size

https://gcc.gnu.org/g:973804222e18699ad649c1d406e30dded298e6eb commit 973804222e18699ad649c1d406e30dded298e6eb Author: Mikael Morin Date: Fri Feb 14 11:22:35 2025 +0100 Mise à jour offset & span dans gfc_array_init_size Diff: --- gcc/fortran/trans-array.cc | 30 ++

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [to-be-committed][RISC-V] Handle 32bit operands in condition for conditional moves

https://gcc.gnu.org/g:b41bbf1d61d22e4c6781943310d41ee03a06468b commit b41bbf1d61d22e4c6781943310d41ee03a06468b Author: Jeff Law Date: Sat Jun 7 07:48:46 2025 -0600 [to-be-committed][RISC-V] Handle 32bit operands in condition for conditional moves So here's the next chunk of condi

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add pattern for vector-scalar multiply-add/sub [PR119100]

https://gcc.gnu.org/g:6fdf0077e8365976bbf307d7f05a97d74e33c2cf commit 6fdf0077e8365976bbf307d7f05a97d74e33c2cf Author: Paul-Antoine Arras Date: Mon May 12 14:42:24 2025 +0200 RISC-V: Add pattern for vector-scalar multiply-add/sub [PR119100] This pattern enables the combine pass (o

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] Déplacement initialisation dernière borne sup assumed size

https://gcc.gnu.org/g:7069cc75f0e5ecc9ff7213316377849b30877436 commit 7069cc75f0e5ecc9ff7213316377849b30877436 Author: Mikael Morin Date: Sun Aug 10 11:13:41 2025 +0200 Déplacement initialisation dernière borne sup assumed size Diff: --- gcc/fortran/trans-array.cc | 37 ++

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Implement full-featured iterator for riscv_subset_list [NFC]

https://gcc.gnu.org/g:154f99534086d05a75615bba224b34b6ea4f9585 commit 154f99534086d05a75615bba224b34b6ea4f9585 Author: Kito Cheng Date: Mon May 26 14:43:47 2025 +0800 RISC-V: Implement full-featured iterator for riscv_subset_list [NFC] This commit implements a full-featured iterat

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] Extraction set_gfc_from_cfi

https://gcc.gnu.org/g:ea74ff43763371571989f2f9bd53aab23181cedc commit ea74ff43763371571989f2f9bd53aab23181cedc Author: Mikael Morin Date: Tue Jul 22 19:51:53 2025 +0200 Extraction set_gfc_from_cfi Diff: --- gcc/fortran/trans-decl.cc | 210 +++- g

[gcc r16-3630] doc: drop verify-canonical-types=1 ref

https://gcc.gnu.org/g:634d9f99868d9dd3eccd4f4b2d30ae874418cc65 commit r16-3630-g634d9f99868d9dd3eccd4f4b2d30ae874418cc65 Author: Sam James Date: Tue Nov 19 08:05:11 2024 + doc: drop verify-canonical-types=1 ref --param verify-canonical-types was removed back in r0-81986-g73135

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Prepare dynamic LMUL heuristic for SLP.

https://gcc.gnu.org/g:ba963844474b0bdc4efa8b15eee2e5dc554d288f commit ba963844474b0bdc4efa8b15eee2e5dc554d288f Author: Robin Dapp Date: Mon Jul 21 16:00:51 2025 +0200 RISC-V: Prepare dynamic LMUL heuristic for SLP. This patch prepares the dynamic LMUL vector costing to use the com

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] Interdiction non-lvalue as lhs

https://gcc.gnu.org/g:4e739e5b36e56a8c8e6ce39b941dad9c809a4ff9 commit 4e739e5b36e56a8c8e6ce39b941dad9c809a4ff9 Author: Mikael Morin Date: Tue Feb 11 21:34:11 2025 +0100 Interdiction non-lvalue as lhs git commit correction erreur gimplify Diff: --- gcc/gimplify.cc | 6 ++ 1 f

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] gimple-simulate: Réécriture de MEM_REF à l'intérieur de ARRAY_REF

https://gcc.gnu.org/g:5826c0d9f05d77cd7b080730a1eae4b4e285c71f commit 5826c0d9f05d77cd7b080730a1eae4b4e285c71f Author: Mikael Morin Date: Sat Aug 30 21:11:38 2025 +0200 gimple-simulate: Réécriture de MEM_REF à l'intérieur de ARRAY_REF Diff: --- gcc/gimple-simulate.cc | 81 +++

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Read extension data from riscv-ext*.def for arch-canonicalize

https://gcc.gnu.org/g:c89ae56e8fab67f54d37e5f106e75f7721ec73f4 commit c89ae56e8fab67f54d37e5f106e75f7721ec73f4 Author: Kito Cheng Date: Thu Jul 31 16:25:52 2025 +0800 RISC-V: Read extension data from riscv-ext*.def for arch-canonicalize Previously, arch-canonicalize used hardcoded

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] gimple-simulate: Assouplissement type pointeur nul

https://gcc.gnu.org/g:4ad9dcf9f6ef59ab365771cc537dda4db9707566 commit 4ad9dcf9f6ef59ab365771cc537dda4db9707566 Author: Mikael Morin Date: Fri Aug 29 15:14:32 2025 +0200 gimple-simulate: Assouplissement type pointeur nul Diff: --- gcc/gimple-simulate.cc | 43 ++

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] Extraction gfc_set_descriptor_from_scalar

https://gcc.gnu.org/g:53b1048a8b2547b54c2d83e0eabb5d5e25c81c2a commit 53b1048a8b2547b54c2d83e0eabb5d5e25c81c2a Author: Mikael Morin Date: Thu Aug 7 14:11:43 2025 +0200 Extraction gfc_set_descriptor_from_scalar Correction gfc_get_scalar_to_descriptor_type Renommage set_des

[gcc r16-3629] dep_fusion: Fix if target does not have macro fusion [PR121835]

https://gcc.gnu.org/g:7b8c45d48f7fca3c10d43ca3f95e28b64458cf2b commit r16-3629-g7b8c45d48f7fca3c10d43ca3f95e28b64458cf2b Author: Andrew Pinski Date: Sat Sep 6 15:24:00 2025 -0700 dep_fusion: Fix if target does not have macro fusion [PR121835] This new pass will ICE if the target d

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vor.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:c4b6346ccd0bff2557aa2fcad7862ab4abf81c11 commit c4b6346ccd0bff2557aa2fcad7862ab4abf81c11 Author: Pan Li Date: Fri May 23 13:26:41 2025 +0800 RISC-V: Add test for vec_duplicate + vor.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check test for ve

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