[gcc r16-2462] testsuite: Fix gcc.target/powerpc/vsx-builtin-7.c test [PR119382]

https://gcc.gnu.org/g:a1fb757342058111fddcdc5ca2f866c61e87c9b8 commit r16-2462-ga1fb757342058111fddcdc5ca2f866c61e87c9b8 Author: Jeevitha Date: Wed Jul 23 23:39:13 2025 -0500 testsuite: Fix gcc.target/powerpc/vsx-builtin-7.c test [PR119382] The test vsx-builtin-7.c failed on power

[gcc(refs/users/aoliva/heads/testme)] [hardbool] implement OP=, ++ and --, volatile and atomics

https://gcc.gnu.org/g:6f4e367589ca8429985220f58c5d777047c623c0 commit 6f4e367589ca8429985220f58c5d777047c623c0 Author: Alexandre Oliva Date: Thu Jul 17 17:54:00 2025 -0300 [hardbool] implement OP=, ++ and --, volatile and atomics hardbools didn't behave quite like bools when incre

[gcc/aoliva/heads/testme] [hardbool] implement OP=, ++ and --, volatile and atomics

The branch 'aoliva/heads/testme' was updated to point to: 6f4e367589ca... [hardbool] implement OP=, ++ and --, volatile and atomics It previously pointed to: c9c6c9ae8f7b... [hardbool] implement OP=, ++ and --, volatile and atomics Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCES

[gcc(refs/users/aoliva/heads/testme)] [hardbool] implement OP=, ++ and --, volatile and atomics

https://gcc.gnu.org/g:c9c6c9ae8f7bd8758b7d8e47bb4a31ab992f8251 commit c9c6c9ae8f7bd8758b7d8e47bb4a31ab992f8251 Author: Alexandre Oliva Date: Thu Jul 17 17:54:00 2025 -0300 [hardbool] implement OP=, ++ and --, volatile and atomics hardbools didn't behave quite like bools when incre

[gcc/aoliva/heads/testme] [hardbool] implement OP=, ++ and --, volatile and atomics

The branch 'aoliva/heads/testme' was updated to point to: c9c6c9ae8f7b... [hardbool] implement OP=, ++ and --, volatile and atomics It previously pointed to: e0140b308723... [hardbool] implement OP=, ++ and --, volatile and atomics Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCES

[gcc r16-2461] RISC-V: Add test case for vx combine polluting VXRM

https://gcc.gnu.org/g:198653e1cc4ddd33a837bd7130b7c347b27202a6 commit r16-2461-g198653e1cc4ddd33a837bd7130b7c347b27202a6 Author: Pan Li Date: Wed Jul 23 13:02:55 2025 +0800 RISC-V: Add test case for vx combine polluting VXRM Add asm check to make sure vx combine of vaaddu.vx will

[gcc r16-2460] RISC-V: Avoid vaaddu.vx combine pattern pollute VXRM csr

https://gcc.gnu.org/g:5aec85a5f490895f90c1ef75f965ea100e80f50e commit r16-2460-g5aec85a5f490895f90c1ef75f965ea100e80f50e Author: Pan Li Date: Wed Jul 23 12:08:02 2025 +0800 RISC-V: Avoid vaaddu.vx combine pattern pollute VXRM csr The vaaddu.vx combine almost comes from avg_floor,

[gcc r15-10060] c++/modules: Support re-streaming TU_LOCAL_ENTITYs [PR120412]

https://gcc.gnu.org/g:efce571b152ac9f5bdbd6821dd537a93e36c1b73 commit r15-10060-gefce571b152ac9f5bdbd6821dd537a93e36c1b73 Author: Nathaniel Shead Date: Sat May 24 10:56:22 2025 +1000 c++/modules: Support re-streaming TU_LOCAL_ENTITYs [PR120412] When emitting a primary module inter

[gcc r16-2459] c++/modules: Support re-streaming TU_LOCAL_ENTITYs [PR120412]

https://gcc.gnu.org/g:be81c5c01c243013c4bac0718e63e0fdc132d384 commit r16-2459-gbe81c5c01c243013c4bac0718e63e0fdc132d384 Author: Nathaniel Shead Date: Sat May 24 10:56:22 2025 +1000 c++/modules: Support re-streaming TU_LOCAL_ENTITYs [PR120412] When emitting a primary module interf

[gcc(refs/users/aoliva/heads/testme)] [hardbool] implement OP=, ++ and --, volatile and atomics

https://gcc.gnu.org/g:e0140b308723211c08944cc583490da108269736 commit e0140b308723211c08944cc583490da108269736 Author: Alexandre Oliva Date: Thu Jul 17 17:54:00 2025 -0300 [hardbool] implement OP=, ++ and --, volatile and atomics hardbools didn't behave quite like bools when incre

[gcc/aoliva/heads/testme] [hardbool] implement OP=, ++ and --, volatile and atomics

The branch 'aoliva/heads/testme' was updated to point to: e0140b308723... [hardbool] implement OP=, ++ and --, volatile and atomics It previously pointed to: 421b31578d42... [hardbool] implement OP=, ++ and --, volatile and atomics Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCES

[gcc/aoliva/heads/testme] [hardbool] implement OP=, ++ and --, volatile and atomics

The branch 'aoliva/heads/testme' was updated to point to: 421b31578d42... [hardbool] implement OP=, ++ and --, volatile and atomics It previously pointed to: a02db3962b16... [hardbool] implement OP=, ++ and --, volatile and atomics Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCES

[gcc(refs/users/aoliva/heads/testme)] [hardbool] implement OP=, ++ and --, volatile and atomics

https://gcc.gnu.org/g:421b31578d4217481f34bf306e67f9365ed65190 commit 421b31578d4217481f34bf306e67f9365ed65190 Author: Alexandre Oliva Date: Thu Jul 17 17:54:00 2025 -0300 [hardbool] implement OP=, ++ and --, volatile and atomics hardbools didn't behave quite like bools when incre

[gcc r16-2457] aarch64: Relaxed SEL combiner patterns for unpacked SVE FP unary operations

https://gcc.gnu.org/g:8d588dbde026b1b96a921b81e80b2de60fd9f8fd commit r16-2457-g8d588dbde026b1b96a921b81e80b2de60fd9f8fd Author: Spencer Abson Date: Mon Jul 7 18:26:35 2025 + aarch64: Relaxed SEL combiner patterns for unpacked SVE FP unary operations Extend the unary op/UNSPEC

[gcc/aoliva/heads/testme] (377 commits) [hardbool] implement OP=, ++ and --, volatile and atomics

The branch 'aoliva/heads/testme' was updated to point to: a02db3962b16... [hardbool] implement OP=, ++ and --, volatile and atomics It previously pointed to: f2785c2d6795... [vxworks] [x86] disable vxworks6 PIC on vxworks7 Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LO

[gcc(refs/users/aoliva/heads/testme)] [hardbool] implement OP=, ++ and --, volatile and atomics

https://gcc.gnu.org/g:a02db3962b16e9fcaaf9729ff0161bc1bbe9be70 commit a02db3962b16e9fcaaf9729ff0161bc1bbe9be70 Author: Alexandre Oliva Date: Thu Jul 17 17:54:00 2025 -0300 [hardbool] implement OP=, ++ and --, volatile and atomics hardbools didn't behave quite like bools when incre

[gcc/aoliva/heads/testbase] (376 commits) aarch64: Add support for unpacked SVE FP unary operations

The branch 'aoliva/heads/testbase' was updated to point to: 556ed247adc9... aarch64: Add support for unpacked SVE FP unary operations It previously pointed to: e46933d3cc82... [vxworks] add aarch64 to vxworks-dummy.h set Diff: Summary of changes (added commits): -

[gcc r16-2456] aarch64: Add support for unpacked SVE FP unary operations

https://gcc.gnu.org/g:556ed247adc9857ebd89a5bdbcdc8f929f73bd1e commit r16-2456-g556ed247adc9857ebd89a5bdbcdc8f929f73bd1e Author: Spencer Abson Date: Mon Jul 7 16:49:17 2025 + aarch64: Add support for unpacked SVE FP unary operations This patch extends the expander for unpredic

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] Change bellow in comments to below

https://gcc.gnu.org/g:763de945f6b4a65f5cf15aad1452f6b3c187f2ed commit 763de945f6b4a65f5cf15aad1452f6b3c187f2ed Author: Jakub Jelinek Date: Thu Jul 10 10:16:43 2025 +0200 Change bellow in comments to below While I'm not a native English speaker, I believe all the uses of bellow

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vaaddu.vv combine case 1 with GR2VR cost 0, 1 and 2 for QI, HI

https://gcc.gnu.org/g:324e9a955262ad46744bc0c0735a03959d29a3ec commit 324e9a955262ad46744bc0c0735a03959d29a3ec Author: Pan Li Date: Mon Jul 21 09:16:17 2025 +0800 RISC-V: Add test for vec_duplicate + vaaddu.vv combine case 1 with GR2VR cost 0, 1 and 2 for QI, HI and SI mode Add a

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vaaddu.vv to vaaddu.vx on GR2VR cost for HI, QI and SI mode

https://gcc.gnu.org/g:93c2fcdd8e128238bd3cac4e07e8aaee7b9d786d commit 93c2fcdd8e128238bd3cac4e07e8aaee7b9d786d Author: Pan Li Date: Mon Jul 21 09:06:52 2025 +0800 RISC-V: Combine vec_duplicate + vaaddu.vv to vaaddu.vx on GR2VR cost for HI, QI and SI mode This patch would like to

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Refine the test case for vector avg_floor and avg_ceil [NFC]

https://gcc.gnu.org/g:c4c34c8c4f4729546345ce472aebd2090af9a0b1 commit c4c34c8c4f4729546345ce472aebd2090af9a0b1 Author: Pan Li Date: Sat Jul 19 10:49:15 2025 +0800 RISC-V: Refine the test case for vector avg_floor and avg_ceil [NFC] The previous test case doesn't leverage the right

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH v2] RISC-V: Vector-scalar widening multiply-(subtract-)accumulate [PR119100]

https://gcc.gnu.org/g:e0bc128751be5c18c87f75a38e759b3007204d9d commit e0bc128751be5c18c87f75a38e759b3007204d9d Author: Paul-Antoine Arras Date: Mon Jul 14 06:10:44 2025 -0600 [PATCH v2] RISC-V: Vector-scalar widening multiply-(subtract-)accumulate [PR119100] This pattern enables

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vaaddu.vv combine for DImode

https://gcc.gnu.org/g:69057e8a789a89b7868cebad07bbc7568ac3f2ee commit 69057e8a789a89b7868cebad07bbc7568ac3f2ee Author: Pan Li Date: Mon Jul 21 09:28:06 2025 +0800 RISC-V: Add test for vec_duplicate + vaaddu.vv combine for DImode Add asm dump check and run test for vec_duplicate +

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Restrict generic-vector-ooo DFA

https://gcc.gnu.org/g:0bdb4d4f27ff3e479df162286f9911ddbda91b17 commit 0bdb4d4f27ff3e479df162286f9911ddbda91b17 Author: Jeff Law Date: Tue Jul 22 07:26:57 2025 -0600 [RISC-V] Restrict generic-vector-ooo DFA So while debugging Austin's work to support the spacemit x60 in the BPI we

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISCV: Remove the v extension requirement for sat scalar run test

https://gcc.gnu.org/g:20fcd8a9e2428f7567c2101b005efb94d163d14a commit 20fcd8a9e2428f7567c2101b005efb94d163d14a Author: Pan Li Date: Wed Jul 9 10:40:52 2025 +0800 RISCV: Remove the v extension requirement for sat scalar run test The sat scalar run test should not require the v exte

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Fix wrong CFA during stack probe

https://gcc.gnu.org/g:08c27960b0c41355ba367567b485b7a72422a40e commit 08c27960b0c41355ba367567b485b7a72422a40e Author: Andreas Schwab Date: Wed Jul 16 14:48:51 2025 +0200 [RISC-V] Fix wrong CFA during stack probe temp1 is used by the probe loop for the step size, but we need the f

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add ashiftrt operand 2 for vector avg_floor and avg_ceil

https://gcc.gnu.org/g:3a87484ab5e961fc70eec10edb36e69e6997bf25 commit 3a87484ab5e961fc70eec10edb36e69e6997bf25 Author: Pan Li Date: Sat Jul 19 17:17:11 2025 +0800 RISC-V: Add ashiftrt operand 2 for vector avg_floor and avg_ceil According to the semantics of the avg_floor and avg_c

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Allow VLS DImode for sat_op vx DImode pattern

https://gcc.gnu.org/g:5b8472af562323628943d2846cbb3262b9562667 commit 5b8472af562323628943d2846cbb3262b9562667 Author: Pan Li Date: Mon Jul 21 09:20:46 2025 +0800 RISC-V: Allow VLS DImode for sat_op vx DImode pattern When try to introduce the vaaddu.vx combine for DImode, we will

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vssub.vv to vssub.vx on GR2VR cost

https://gcc.gnu.org/g:a4c8e28f013d81cf4e2012b6aa76c5d065e008b8 commit a4c8e28f013d81cf4e2012b6aa76c5d065e008b8 Author: Pan Li Date: Mon Jul 7 11:07:11 2025 +0800 RISC-V: Combine vec_duplicate + vssub.vv to vssub.vx on GR2VR cost This patch would like to combine the vec_duplicate +

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support RVVDImode for avg3_ceil auto vect

https://gcc.gnu.org/g:8b53c83cfc038a486247221b76b4fc7817de84a2 commit 8b53c83cfc038a486247221b76b4fc7817de84a2 Author: Pan Li Date: Wed Jul 16 21:40:14 2025 +0800 RISC-V: Support RVVDImode for avg3_ceil auto vect Like the avg3_floor pattern, the avg3_ceil has the similar issue

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Add missing insn types to xiangshan.md and mips-p8700.md

https://gcc.gnu.org/g:bf08d630ff6b01021a2c93b999e07ae12e4aabd6 commit bf08d630ff6b01021a2c93b999e07ae12e4aabd6 Author: Jeff Law Date: Mon Jul 21 15:58:12 2025 -0600 [RISC-V] Add missing insn types to xiangshan.md and mips-p8700.md This is a trivial patch to add a few missing types

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Enable zvfh for vector-scalar half-float run tests

https://gcc.gnu.org/g:c5a3303c59330b94765d9bd8690e6cf09c823f1b commit c5a3303c59330b94765d9bd8690e6cf09c823f1b Author: Paul-Antoine Arras Date: Wed Jul 9 08:36:24 2025 -0600 [PATCH] RISC-V: Enable zvfh for vector-scalar half-float run tests zvfh is not enabled at the testsuite lev

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix vsetvl merge rule.

https://gcc.gnu.org/g:820f9d56bdbbbded454cf2d1b4b0327e360c3d54 commit 820f9d56bdbbbded454cf2d1b4b0327e360c3d54 Author: Robin Dapp Date: Mon Jul 14 13:53:12 2025 +0200 RISC-V: Fix vsetvl merge rule. In PR120297 we fuse vsetvl e8,mf2,... vsetvl e64,m1,... into

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support RVVDImode for avg3_floor auto vect

https://gcc.gnu.org/g:42743b866d62edf80a6b59009f0dfe7ae34ca240 commit 42743b866d62edf80a6b59009f0dfe7ae34ca240 Author: Pan Li Date: Tue Jul 15 09:45:05 2025 +0800 RISC-V: Support RVVDImode for avg3_floor auto vect The avg3_floor pattern leverage the add and shift rtl with the

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vaaddu.vv combine case 0 with GR2VR cost 0, 2 and 15 for QI, HI

https://gcc.gnu.org/g:26e74989ad56895ee568d87c44abe8a8fd29d73b commit 26e74989ad56895ee568d87c44abe8a8fd29d73b Author: Pan Li Date: Mon Jul 21 09:13:27 2025 +0800 RISC-V: Add test for vec_duplicate + vaaddu.vv combine case 0 with GR2VR cost 0, 2 and 15 for QI, HI and SI mode Add

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH v5] RISC-V: Mips P8700 Conditional Move Support.

https://gcc.gnu.org/g:83974e4d4f3d5b04d486d9b08543795dbc40c534 commit 83974e4d4f3d5b04d486d9b08543795dbc40c534 Author: Umesh Kalappa Date: Tue Jul 15 10:35:44 2025 -0600 [PATCH v5] RISC-V: Mips P8700 Conditional Move Support. Updated the test for rv32 accordingly and no regress fo

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcase for unsigned scalar SAT_ADD form 8 and form 9

https://gcc.gnu.org/g:833cce5832852050fdfd62fa5fd9cb0e6a7529c3 commit 833cce5832852050fdfd62fa5fd9cb0e6a7529c3 Author: panciyan Date: Mon Jul 21 01:41:31 2025 + RISC-V: Add testcase for unsigned scalar SAT_ADD form 8 and form 9 This patch adds testcase for form8 and form9, as

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Vector-scalar widening negate-multiply-(subtract-)accumulate [PR119100]

https://gcc.gnu.org/g:e077fe0f4dea3f2409fe698064510fe74434ee68 commit e077fe0f4dea3f2409fe698064510fe74434ee68 Author: Paul-Antoine Arras Date: Sat Jul 19 08:40:14 2025 -0600 [PATCH] RISC-V: Vector-scalar widening negate-multiply-(subtract-)accumulate [PR119100] This pattern enab

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: prevent NULL_RTX dereference in riscv_macro_fusion_pair_p ()

https://gcc.gnu.org/g:4ea760103aaa2ba885f22705be509b12ef057f65 commit 4ea760103aaa2ba885f22705be509b12ef057f65 Author: Artemiy Volkov Date: Sat Jul 19 08:03:02 2025 -0600 [PATCH] RISC-V: prevent NULL_RTX dereference in riscv_macro_fusion_pair_p () > A number of folks have had thei

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcase for rv32 SAT_MUL from uint64

https://gcc.gnu.org/g:facb0b8390128508f6919fe182c61526725b78ce commit facb0b8390128508f6919fe182c61526725b78ce Author: Pan Li Date: Fri Jul 11 08:58:31 2025 +0800 RISC-V: Add testcase for rv32 SAT_MUL from uint64 Add the run and asm testcase for rv32 SAT_MUL, widen mul from ui

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Make zero-stride load broadcast a tunable.

https://gcc.gnu.org/g:8d827db2a570f9bedb766b5d0ec0654c1cfee88d commit 8d827db2a570f9bedb766b5d0ec0654c1cfee88d Author: Robin Dapp Date: Thu Jul 10 09:41:48 2025 +0200 RISC-V: Make zero-stride load broadcast a tunable. This patch makes the zero-stride load broadcast idiom dependent

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcases for unsigned vector SAT_SUB form 11 and form 12

https://gcc.gnu.org/g:866b6599e8b0c250d360bdad941c48db8017db92 commit 866b6599e8b0c250d360bdad941c48db8017db92 Author: panciyan Date: Thu Jul 10 06:54:26 2025 + RISC-V: Add testcases for unsigned vector SAT_SUB form 11 and form 12 This patch adds testcase for form11 and form12

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vssub.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:3ca3c6d80eda2f12cf135c69e25ea7f24d2bb383 commit 3ca3c6d80eda2f12cf135c69e25ea7f24d2bb383 Author: Pan Li Date: Mon Jul 7 11:17:00 2025 +0800 RISC-V: Add test for vec_duplicate + vssub.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check test for ve

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Adjust testdata for unsigned vector SAT_SUB

https://gcc.gnu.org/g:5d6fd535a95f01b1ca6ba1abc00872b21481c2a4 commit 5d6fd535a95f01b1ca6ba1abc00872b21481c2a4 Author: Ciyan Pan Date: Wed Jul 9 08:31:25 2025 -0600 [PATCH] RISC-V: Adjust testdata for unsigned vector SAT_SUB This patch adjust test data for unsigned vector SAT_SUB

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Detect new fusions for RISC-V

https://gcc.gnu.org/g:635ac775af854700e6ef4d8ad109795f5ee104d1 commit 635ac775af854700e6ef4d8ad109795f5ee104d1 Author: Daniel Barboza Date: Thu Jul 10 07:28:38 2025 -0600 [RISC-V] Detect new fusions for RISC-V This is primarily Daniel's work... He's chasing things in QEMU & LLVM

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/120642] Avoid propagating constant AVL for theadvector

https://gcc.gnu.org/g:b8558ce198fb08e4e30d1b1c2208156f437d24db commit b8558ce198fb08e4e30d1b1c2208156f437d24db Author: Jeff Law Date: Wed Jul 9 05:23:34 2025 -0600 [RISC-V][PR target/120642] Avoid propagating constant AVL for theadvector AVL propagation currently assumes that it c

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Implement unsigned scalar SAT_MUL from uint128_t

https://gcc.gnu.org/g:04628a18a58417a0b0e9018dd5bbaf820de2195c commit 04628a18a58417a0b0e9018dd5bbaf820de2195c Author: Pan Li Date: Wed Jul 2 10:35:10 2025 +0800 RISC-V: Implement unsigned scalar SAT_MUL from uint128_t This patch would like to implement the SAT_MUL scalar unsigned

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Disable uint128_t testcase of SAT_MUL when rv32

https://gcc.gnu.org/g:e1b3e2b098963849d5f0f183567ebc593860a51e commit e1b3e2b098963849d5f0f183567ebc593860a51e Author: Pan Li Date: Tue Jul 8 10:46:29 2025 +0800 RISC-V: Disable uint128_t testcase of SAT_MUL when rv32 The rv32 doesn't support __uint128, and then we will have e

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vsadd.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:2ba4718fe4e3d0eb68fdfd736deb5b0cdb7ffc3d commit 2ba4718fe4e3d0eb68fdfd736deb5b0cdb7ffc3d Author: Pan Li Date: Thu Jul 3 17:17:28 2025 +0800 RISC-V: Add test for vec_duplicate + vsadd.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check test for ve

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vssub.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:0934c8724bd460dd31dcef0c2c435d2d48e7192d commit 0934c8724bd460dd31dcef0c2c435d2d48e7192d Author: Pan Li Date: Mon Jul 7 11:13:15 2025 +0800 RISC-V: Add test for vec_duplicate + vssub.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check and run te

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Do not use vsetivli for THeadVector.

https://gcc.gnu.org/g:d985f7a1698cf4e81b5597ce284a51661b9827da commit d985f7a1698cf4e81b5597ce284a51661b9827da Author: Robin Dapp Date: Tue Jul 8 11:35:12 2025 +0200 RISC-V: Do not use vsetivli for THeadVector. In emit_vlmax_insn_lra we use a vsetivli for an immediate AVL. XTH

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vsadd.vv to vsadd.vx on GR2VR cost

https://gcc.gnu.org/g:95212246f56e31132e593d3ac537515415fcf94c commit 95212246f56e31132e593d3ac537515415fcf94c Author: Pan Li Date: Thu Jul 3 17:07:44 2025 +0800 RISC-V: Combine vec_duplicate + vsadd.vv to vsadd.vx on GR2VR cost This patch would like to combine the vec_duplicate +

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test cases for unsigned scalar SAT_MUL from uint128_t

https://gcc.gnu.org/g:57b108bed5cbacc524dc57d7661a58795b8c30ae commit 57b108bed5cbacc524dc57d7661a58795b8c30ae Author: Pan Li Date: Wed Jul 2 10:52:25 2025 +0800 RISC-V: Add test cases for unsigned scalar SAT_MUL from uint128_t Add run and tree-optimized check for unsigned scalar

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [committed][RISC-V] Fix testsuite fallout from check-function-bodies change

https://gcc.gnu.org/g:eddfc558477fa0cf46693ba8063a87ee05afc373 commit eddfc558477fa0cf46693ba8063a87ee05afc373 Author: Jeff Law Date: Mon Jul 7 20:42:04 2025 -0600 [committed][RISC-V] Fix testsuite fallout from check-function-bodies change Minor fallout from HJ's recent change to

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Ignore non-types in builtin function hash.

https://gcc.gnu.org/g:94db940a20b68d41e27cfa77414581f29745193b commit 94db940a20b68d41e27cfa77414581f29745193b Author: Robin Dapp Date: Tue Jul 8 11:17:41 2025 +0200 RISC-V: Ignore non-types in builtin function hash. If a user passes a string that doesn't represent a variable we s

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vsadd.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:a82205ff03c280a58300c7ea0c7d8286e8a30a95 commit a82205ff03c280a58300c7ea0c7d8286e8a30a95 Author: Pan Li Date: Thu Jul 3 17:16:21 2025 +0800 RISC-V: Add test for vec_duplicate + vsadd.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check and run te

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Add basic instrumentation to fusion detection

https://gcc.gnu.org/g:342e0f685decef56078e201e38891dd4ce01e405 commit 342e0f685decef56078e201e38891dd4ce01e405 Author: Shreya Munnangi Date: Thu Jul 3 21:03:03 2025 -0600 [RISC-V] Add basic instrumentation to fusion detection We were looking to evaluate some changes from Artemiy t

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcases for signed scalar SAT_ADD IMM form 2

https://gcc.gnu.org/g:ed2c97264ef4c6b2a329eaa5c5de9e2f4614d867 commit ed2c97264ef4c6b2a329eaa5c5de9e2f4614d867 Author: panciyan Date: Tue Jun 24 09:58:14 2025 +0800 RISC-V: Add testcases for signed scalar SAT_ADD IMM form 2 This patch adds testcase for form2, as shown below:

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/118886] Refine when two insns are signaled as fusion candidates

https://gcc.gnu.org/g:b8613cba2ebc46bdc6322b582b4fad80b633e7fb commit b8613cba2ebc46bdc6322b582b4fad80b633e7fb Author: Jeff Law Date: Thu Jul 3 06:44:31 2025 -0600 [RISC-V][PR target/118886] Refine when two insns are signaled as fusion candidates A number of folks have had their

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped patterns [PR120356]

https://gcc.gnu.org/g:17f6b67746829ce2c4b9887fc245ad8225ea6a74 commit 17f6b67746829ce2c4b9887fc245ad8225ea6a74 Author: Alexey Merzlyakov Date: Wed Jul 2 11:29:00 2025 -0600 [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped patterns [PR120356] It corrects the shift type

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] Refactor record_function_versions.

https://gcc.gnu.org/g:0190716280b5c2da106ae64e9df77fb6e4b21d51 commit 0190716280b5c2da106ae64e9df77fb6e4b21d51 Author: Alfie Richards Date: Thu Mar 27 14:12:06 2025 + Refactor record_function_versions. Renames record_function_versions to add_function_version, and make it e

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vssubu.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:631cf6bcff6bff83b5051ff38e709aaf281467e4 commit 631cf6bcff6bff83b5051ff38e709aaf281467e4 Author: Pan Li Date: Fri Jun 27 09:09:08 2025 +0800 RISC-V: Add test for vec_duplicate + vssubu.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check test for

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Ignore -Oz for most rvv testcase [NFC]

https://gcc.gnu.org/g:d1ec2e53143fde602a28f5ea56c5621866d27c2c commit d1ec2e53143fde602a28f5ea56c5621866d27c2c Author: Kito Cheng Date: Mon Jun 30 14:18:07 2025 +0800 RISC-V: Ignore -Oz for most rvv testcase [NFC] Most testcase in rvv folder already ignore -Oz, but some of them

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Correct CFA notes for stack-clash protection [PR120714]

https://gcc.gnu.org/g:7a4c77b3daa76391c199f358af51b69821a69a54 commit 7a4c77b3daa76391c199f358af51b69821a69a54 Author: Alexey Merzlyakov Date: Mon Jun 30 13:58:29 2025 -0600 [RISC-V] Correct CFA notes for stack-clash protection [PR120714] Fixes incorrect SP-addresses used in CFA n

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Primary vector pipeline model for sifive 7 series

https://gcc.gnu.org/g:6b0f5feae85b87cde74b40f16296f0a694b44ad5 commit 6b0f5feae85b87cde74b40f16296f0a694b44ad5 Author: Kito Cheng Date: Thu Jun 19 14:31:42 2025 +0800 RISC-V: Primary vector pipeline model for sifive 7 series This commit introduces a primary vector pipeline model f

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vssubu.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:5086e8b3c321404c5ddeba449c8cbd9cabee4f16 commit 5086e8b3c321404c5ddeba449c8cbd9cabee4f16 Author: Pan Li Date: Fri Jun 27 09:06:38 2025 +0800 RISC-V: Add test for vec_duplicate + vssubu.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check and run

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: testsuite: Skip tests providing -march/-mcpu for ILP32E/ILP64E ABIs

https://gcc.gnu.org/g:ee451a07da4d1337cfe1031199fbc9303be99708 commit ee451a07da4d1337cfe1031199fbc9303be99708 Author: Dimitar Dimitrov Date: Fri Jun 20 20:57:15 2025 +0300 RISC-V: testsuite: Skip tests providing -march/-mcpu for ILP32E/ILP64E ABIs Some test cases explicitly set -

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Reconcile the existing test due to cost model change

https://gcc.gnu.org/g:e33555b705755a7cf2bc6c261101bffe21c7c76e commit e33555b705755a7cf2bc6c261101bffe21c7c76e Author: Pan Li Date: Fri Jun 27 11:35:18 2025 +0800 RISC-V: Reconcile the existing test due to cost model change The cost model change will make the default cost of vx to

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Adding B ext, fp16 and missing scalar instruction type for sifive-7 pipeline model [PR120659

https://gcc.gnu.org/g:d9f05954d3b1cb95d37caa75fe0eee8b0689ebd9 commit d9f05954d3b1cb95d37caa75fe0eee8b0689ebd9 Author: Kito Cheng Date: Tue Jun 17 16:20:19 2025 +0800 RISC-V: Adding B ext, fp16 and missing scalar instruction type for sifive-7 pipeline model [PR120659] gcc/ChangeL

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vssubu.vv to vssubu.vx on GR2VR cost

https://gcc.gnu.org/g:2e78bb2b51ec4527a3586df7ec04114cf5f74b35 commit 2e78bb2b51ec4527a3586df7ec04114cf5f74b35 Author: Pan Li Date: Fri Jun 27 09:02:03 2025 +0800 RISC-V: Combine vec_duplicate + vssubu.vv to vssubu.vx on GR2VR cost This patch would like to combine the vec_duplicat

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Vector-scalar negate-multiply-(subtract-)accumulate [PR119100]

https://gcc.gnu.org/g:2b19c585a6f35ef68c0f392b2b688182dd1c779f commit 2b19c585a6f35ef68c0f392b2b688182dd1c779f Author: Paul-Antoine Arras Date: Thu Jun 26 13:20:49 2025 + RISC-V: Vector-scalar negate-multiply-(subtract-)accumulate [PR119100] This pattern enables the combine pa

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: update prepare_ternary_operands to handle vector-scalar case [PR120828]

https://gcc.gnu.org/g:468cffa2642f3165ee59c18d416ddb5e8e172d6d commit 468cffa2642f3165ee59c18d416ddb5e8e172d6d Author: Paul-Antoine Arras Date: Wed Jun 25 16:42:00 2025 + RISC-V: update prepare_ternary_operands to handle vector-scalar case [PR120828] This is a followup to 92e

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vsaddu.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:786c243835c55b5e6fa8d672e07a9af1166475b6 commit 786c243835c55b5e6fa8d672e07a9af1166475b6 Author: Pan Li Date: Sat Jun 21 09:10:07 2025 +0800 RISC-V: Add test for vec_duplicate + vsaddu.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check and run

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix ICE for expand_select_vldi [PR120652]

https://gcc.gnu.org/g:dcdaa59e23951d1584b447c4da226f2f4912c3ef commit dcdaa59e23951d1584b447c4da226f2f4912c3ef Author: Pan Li Date: Thu Jun 19 18:58:17 2025 +0800 RISC-V: Fix ICE for expand_select_vldi [PR120652] The will be one ICE when expand pass, the bt similar as below.

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vmin.vv to vmin.vx on GR2VR cost

https://gcc.gnu.org/g:df78e456dc57cf69d05242c0f8b5a139d0337cff commit df78e456dc57cf69d05242c0f8b5a139d0337cff Author: Pan Li Date: Tue Jun 17 10:00:54 2025 +0800 RISC-V: Combine vec_duplicate + vmin.vv to vmin.vx on GR2VR cost This patch would like to combine the vec_duplicate +

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add pipeline-checker script

https://gcc.gnu.org/g:fba8b6e0cf32bc6b2b4cb0b2aa25ce6f730e2eec commit fba8b6e0cf32bc6b2b4cb0b2aa25ce6f730e2eec Author: Kito Cheng Date: Thu Jun 26 17:21:27 2025 +0800 RISC-V: Add pipeline-checker script Pipeline checker utility for RISC-V architecture that validates processor

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_dup + vmax.vv combine case 1 with max func 1 and GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:8c01d04410445af2bb213966f0bd9aaa91461abc commit 8c01d04410445af2bb213966f0bd9aaa91461abc Author: Pan Li Date: Thu Jun 12 10:42:39 2025 +0800 RISC-V: Add test for vec_dup + vmax.vv combine case 1 with max func 1 and GR2VR cost 0, 1 and 2 Add asm dump check te

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix build issue

https://gcc.gnu.org/g:7bef4a4a0997c01f11f40fc0b1cabf1f2f086194 commit 7bef4a4a0997c01f11f40fc0b1cabf1f2f086194 Author: Kito Cheng Date: Thu Jun 26 14:35:47 2025 +0800 RISC-V: Fix build issue Apparently I forgot to squash this fix into the previous commit before I push...

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/119971] Avoid losing shift count masking

https://gcc.gnu.org/g:310914d32df94ff9134b2b62de623a3ad643b01b commit 310914d32df94ff9134b2b62de623a3ad643b01b Author: Jeff Law Date: Fri Jun 27 07:00:15 2025 -0600 [RISC-V][PR target/119971] Avoid losing shift count masking Fix typo spotted by Bernhard Reutner-Fischer.

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add Profiles RVA/B23S64 support.

https://gcc.gnu.org/g:ed0e22eb68f0b311f6a837d5bee34569fcc7e7f0 commit ed0e22eb68f0b311f6a837d5bee34569fcc7e7f0 Author: Jiawei Date: Tue Jun 24 17:34:05 2025 +0800 RISC-V: Add Profiles RVA/B23S64 support. This patch adds support for the RISC-V Profiles RVA23S64 and RVB23S64.

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [sanitizer_common] Fix build on ppc64+musl (#120036)

https://gcc.gnu.org/g:00fac0b4406e67cf4daf6f8e2d5af7c3ac6b0262 commit 00fac0b4406e67cf4daf6f8e2d5af7c3ac6b0262 Author: Jeff Law Date: Fri Jun 27 15:11:41 2025 -0600 [sanitizer_common] Fix build on ppc64+musl (#120036) Cherry picked from LLVM commit 801b519dfd01e21da0be17aa8f8dc2ce

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add patterns for vector-scalar multiply-(subtract-)accumulate [PR119100]

https://gcc.gnu.org/g:38505babe79206db1cacf083e71450121388013c commit 38505babe79206db1cacf083e71450121388013c Author: Paul-Antoine Arras Date: Tue Jun 24 15:42:50 2025 -0600 RISC-V: Add patterns for vector-scalar multiply-(subtract-)accumulate [PR119100] This pattern enables the

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Refactor the function bitmap_union_of_preds_with_entry

https://gcc.gnu.org/g:85765e5c0d2b7851e2a5466e52ba1f0a46f85cc7 commit 85765e5c0d2b7851e2a5466e52ba1f0a46f85cc7 Author: Jin Ma Date: Sat Jun 28 19:55:00 2025 +0800 RISC-V: Refactor the function bitmap_union_of_preds_with_entry The current implementation of this function is somewhat

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Regen riscv-ext.texi [NFC]

https://gcc.gnu.org/g:318ee821f842314dbc8e838786321448b919304c commit 318ee821f842314dbc8e838786321448b919304c Author: Kito Cheng Date: Tue Jun 10 10:32:37 2025 +0800 RISC-V: Regen riscv-ext.texi [NFC] Regenerates the `riscv-ext.texi` file in the GCC documentation. gcc/Ch

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add comment and reorder the the include files in riscv.md [NFC]

https://gcc.gnu.org/g:21a280fdf786dade2207dc0a46920be782a5ce9b commit 21a280fdf786dade2207dc0a46920be782a5ce9b Author: Kito Cheng Date: Thu Jun 26 14:26:57 2025 +0800 RISC-V: Add comment and reorder the the include files in riscv.md [NFC] This patch adds a comment to the riscv.md

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/119830] Fix RISC-V codegen on 32bit hosts

https://gcc.gnu.org/g:7d12abe78ea1832937a4789ea61e3eb96fd687c9 commit 7d12abe78ea1832937a4789ea61e3eb96fd687c9 Author: Andrew Pinski Date: Sun Jun 22 12:35:19 2025 -0600 [RISC-V][PR target/119830] Fix RISC-V codegen on 32bit hosts So this is Andrew's patch from the PR. We weren't

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vsaddu.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:6521311a515bb66ee384c2d6b9959ce79416cece commit 6521311a515bb66ee384c2d6b9959ce79416cece Author: Pan Li Date: Sat Jun 21 10:07:38 2025 +0800 RISC-V: Add test for vec_duplicate + vsaddu.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check test for

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/118241] Fix data prefetch predicate/constraint for RISC-V

https://gcc.gnu.org/g:cef5e1ca9d07d081e2a218404198bab416562762 commit cef5e1ca9d07d081e2a218404198bab416562762 Author: Jeff Law Date: Sat Jun 21 08:24:58 2025 -0600 [RISC-V][PR target/118241] Fix data prefetch predicate/constraint for RISC-V The RISC-V prefetch support is broken i

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vsaddu.vv to vsaddu.vx on GR2VR cost

https://gcc.gnu.org/g:e3cb2eceec837d858c0bb64a18867d4d63fe49e6 commit e3cb2eceec837d858c0bb64a18867d4d63fe49e6 Author: Pan Li Date: Sat Jun 21 09:00:16 2025 +0800 RISC-V: Combine vec_duplicate + vsaddu.vv to vsaddu.vx on GR2VR cost This patch would like to combine the vec_duplicat

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vremu.vv to vremu.vx on GR2VR cost

https://gcc.gnu.org/g:a905f0166da7bf7da91a4fe1efffa92315b6f879 commit a905f0166da7bf7da91a4fe1efffa92315b6f879 Author: Pan Li Date: Mon Jun 9 16:24:34 2025 +0800 RISC-V: Combine vec_duplicate + vremu.vv to vremu.vx on GR2VR cost This patch would like to combine the vec_duplicate +

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vminu.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:6374a6649b5cae0b39a3d492b3b8592c07a3b717 commit 6374a6649b5cae0b39a3d492b3b8592c07a3b717 Author: Pan Li Date: Thu Jun 19 10:47:33 2025 +0800 RISC-V: Add test for vec_duplicate + vminu.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check and run t

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add generic tune as default.

https://gcc.gnu.org/g:5fb78121819a24b0b157fe4d71e9097e3a68989d commit 5fb78121819a24b0b157fe4d71e9097e3a68989d Author: Dongyan Chen Date: Wed Jun 18 19:47:28 2025 +0800 RISC-V: Add generic tune as default. According to the discussion in https://gcc.gnu.org/pipermail/gcc-patche

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Use riscv_2x_xlen_mode_p [NFC]

https://gcc.gnu.org/g:266be98d14cca6b349599d5e2f4900556611ebe4 commit 266be98d14cca6b349599d5e2f4900556611ebe4 Author: Kito Cheng Date: Tue Jun 17 13:01:01 2025 +0800 RISC-V: Use riscv_2x_xlen_mode_p [NFC] Use riscv_v_ext_mode_p to check the mode size is 2x XLEN, instead of us

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Adding cost model for zilsd

https://gcc.gnu.org/g:786c105a9d457d103c2ef608a0ceab9b92b282a0 commit 786c105a9d457d103c2ef608a0ceab9b92b282a0 Author: Kito Cheng Date: Tue Jun 17 12:56:17 2025 +0800 RISC-V: Adding cost model for zilsd Motivation of this patch is we want to use ld/sd if possible when zilsd is

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Use builtin clz/ctz when count_leading_zeros and count_trailing_zeros is used

https://gcc.gnu.org/g:2abb0cc84713dde6305c84e37fb5e90e7167f484 commit 2abb0cc84713dde6305c84e37fb5e90e7167f484 Author: Sosutha Sethuramapandian Date: Thu Jun 19 20:53:56 2025 -0600 [PATCH] RISC-V: Use builtin clz/ctz when count_leading_zeros and count_trailing_zeros is used longl

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Force several tests to use rocket tuning

https://gcc.gnu.org/g:ba2759d58ac6e08c1aaf9215d4681066bc984259 commit ba2759d58ac6e08c1aaf9215d4681066bc984259 Author: Jeff Law Date: Thu Jun 19 20:58:56 2025 -0600 [RISC-V] Force several tests to use rocket tuning My tester has been flagging these regressions since the default co

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vminu.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:dced81dc986050f44ac8721763d3dd1656674a5e commit dced81dc986050f44ac8721763d3dd1656674a5e Author: Pan Li Date: Thu Jun 19 10:49:07 2025 +0800 RISC-V: Add test for vec_duplicate + vminu.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check test for v

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vmin.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:70cb9dffd6af5fcb9915d97853238d2d19b0fd7a commit 70cb9dffd6af5fcb9915d97853238d2d19b0fd7a Author: Pan Li Date: Tue Jun 17 10:05:33 2025 +0800 RISC-V: Add test for vec_duplicate + vmin.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check and run te

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vmin.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:a82b84b332dea5f3935c3b360991915cb96ca798 commit a82b84b332dea5f3935c3b360991915cb96ca798 Author: Pan Li Date: Tue Jun 17 10:08:44 2025 +0800 RISC-V: Add test for vec_duplicate + vmin.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check test for ve

  1   2   3   4   5   6   >