[Bug target/94042] [10 Regression] Bootstrap fails on ppc-linux-gnu

2020-03-06 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94042 --- Comment #31 from Vladimir Makarov --- (In reply to Segher Boessenkool from comment #30) > r10-6919 isn't good for Power, btw. Why would it *ever* be a good idea? This heuristic avoid creating small gaps in hard reg file which prevent assign

[Bug target/94042] [10 Regression] Bootstrap fails on ppc-linux-gnu

2020-03-06 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94042 --- Comment #33 from Vladimir Makarov --- (In reply to Segher Boessenkool from comment #32) > So it sounds like this helps for targets with tiny register sets? I guess it helps for any target but of course more for ones with smaller register set

[Bug target/94042] [10 Regression] Bootstrap fails on ppc-linux-gnu

2020-03-09 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94042 --- Comment #29 from Vladimir Makarov --- Sorry for all the troubles with my latest patch and thank you for fair criticism. I've decided to revert the patch as soon as git starts working. I'll work to find a better solution after this.

[Bug target/94042] [10 Regression] Bootstrap fails on ppc-linux-gnu

2020-03-09 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94042 --- Comment #39 from Vladimir Makarov --- I've reverted the patch in trouble: https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;a=commitdiff;h=5dc1390b41db5c1765e25fd21dad1a930a015aac

[Bug target/92303] [10 regression] gcc.target/sparc/ultrasp12.c times out

2020-03-12 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92303 --- Comment #11 from Vladimir Makarov --- Jakub, thank you for the analysis. I've been working on this PR too. I hope the patch will be ready on Friday or at the beginning of the next week.

[Bug target/94185] [10 Regression] crashes with "error: unable to generate reloads for {*zero_extendsidi2} internal compiler error: in curr_insn_transform, at lra-constraints.c:4006

2020-03-16 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94185 --- Comment #4 from Vladimir Makarov --- Thank you the reduced test. I've started to work on this.

[Bug target/94185] [10 Regression] crashes with "error: unable to generate reloads for {*zero_extendsidi2} internal compiler error: in curr_insn_transform, at lra-constraints.c:4006

2020-03-16 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94185 --- Comment #5 from Vladimir Makarov --- I found the problem. LRA reused the same insn alternative when mem subreg was changed. The patch will be ready today or tomorrow at worst.

[Bug target/94298] x86 duplicates loads

2020-03-30 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94298 --- Comment #5 from Vladimir Makarov --- I think that the root of the problem is that IRA on register cost calculation sub-pass chooses memory for the pseudo. It happens because the current algorithm (which is just an adoption of old recglass.c)

[Bug rtl-optimization/70164] [8/9/10 Regression] Code/performance regression due to poor register allocation on Cortex-M0

2020-04-21 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70164 --- Comment #25 from Vladimir Makarov --- Sorry, I can not reproduce this. With today trunk I have for pr45701-1.c (-Os -mthumb): history_expand_line_internal: @ args = 0, pretend = 0, frame = 0 @ frame_needed = 0, uses_anonymou

[Bug rtl-optimization/70164] [8/9/10 Regression] Code/performance regression due to poor register allocation on Cortex-M0

2020-04-21 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70164 --- Comment #27 from Vladimir Makarov --- (In reply to Christophe Lyon from comment #26) > For what CPU did you configure GCC? > With today's trunk I still see the same code as in comment #24. > > I can get the same code as you have in comment #

[Bug target/94663] [missed optimization] _mm512_dpbusds_epi32 generates excess vmovdqa64

2020-04-27 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94663 --- Comment #2 from Vladimir Makarov --- (In reply to Jakub Jelinek from comment #1) > I bet IRA is confused by the subregs. > No, I don't think it is the case here. (insn 19 18 20 4 (parallel [

[Bug middle-end/95464] [10/11 Regression] Miscompilation of mesa on x86_64-linux since r10-6426

2020-06-01 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95464 --- Comment #1 from Vladimir Makarov --- Jakub, thank you for working on the PR and providing the test case. It seems to me that the problem occurs in inheritance sub-pass of LRA. It is a very complicated sub-pass. Making a fix and testing it

[Bug rtl-optimization/90174] Bad register spill due to top-down allocation order

2020-06-24 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90174 --- Comment #11 from Vladimir Makarov --- (In reply to Tamar Christina from comment #10) > Hi Vlad, > > Just curious if you had a chance to think about an approach to this that > would be acceptable. Sorry for not working on this issue more a

[Bug rtl-optimization/90174] Bad register spill due to top-down allocation order

2020-06-25 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90174 --- Comment #13 from Vladimir Makarov --- (In reply to Tamar Christina from comment #12) > (In reply to Vladimir Makarov from comment #11) > > I just expressed my point of view to the bottom-up approach. If somebody > > implements any new RA a

[Bug target/95674] Unnecessary move when doing division-by-multiplication

2020-06-26 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95674 --- Comment #3 from Vladimir Makarov --- I looked at this problem. All assignments are done in IRA (LRA does not change them). We can not make a better assignment because scratches do not permit to store any preferences from instruction constra

[Bug target/95674] Unnecessary move when doing division-by-multiplication

2020-06-29 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95674 --- Comment #5 from Vladimir Makarov --- (In reply to rsand...@gcc.gnu.org from comment #4) > (In reply to Vladimir Makarov from comment #3) > > I looked at this problem. > > > > All assignments are done in IRA (LRA does not change them). We ca

[Bug target/87767] Missing AVX512 memory broadcast for constant vector

2020-09-09 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87767 Vladimir Makarov changed: What|Removed |Added CC||vmakarov at gcc dot gnu.org

[Bug rtl-optimization/90007] [9/10 Regression] ICE in extract_constrain_insn_cached, at recog.c:2223

2019-11-18 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90007 --- Comment #11 from Vladimir Makarov --- (In reply to Alexander Monakov from comment #4) > Well, often sel-sched just does not discriminate hardregs and pseudos when > checking if renaming/substitution may be applied. Sure, as a matter of > effi

[Bug ipa/44563] GCC uses a lot of RAM when compiling a large numbers of functions

2019-11-22 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=44563 Vladimir Makarov changed: What|Removed |Added CC||vmakarov at gcc dot gnu.org

[Bug rtl-optimization/92283] [10 Regression] 454.calculix miscomparison since r276645 with -O2 -march=znver2

2019-11-27 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92283 --- Comment #24 from Vladimir Makarov --- (In reply to Richard Biener from comment #23) > Vladimir, can you look into this LRA inheritance issue? Yes, I've started to work on this. I can not reproduce it on the current trunk. But yesterday, I'

[Bug rtl-optimization/90007] [9/10 Regression] ICE in extract_constrain_insn_cached, at recog.c:2223

2019-11-27 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90007 --- Comment #12 from Vladimir Makarov --- Author: vmakarov Date: Wed Nov 27 14:24:47 2019 New Revision: 278770 URL: https://gcc.gnu.org/viewcvs?rev=278770&root=gcc&view=rev Log: 2019-11-27 Vladimir Makarov PR rtl-optimization/90007

[Bug rtl-optimization/90007] [9/10 Regression] ICE in extract_constrain_insn_cached, at recog.c:2223

2019-11-27 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90007 --- Comment #14 from Vladimir Makarov --- (In reply to Segher Boessenkool from comment #13) > Does that work? You cannot put all hard registers in memory I think? > Or do we require that and it is just not documented? It depends on insns. For

[Bug rtl-optimization/92283] [10 Regression] 454.calculix miscomparison since r276645 with -O2 -march=znver2

2019-11-29 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92283 --- Comment #26 from Vladimir Makarov --- I think I find the problem root. We have ** Local #2: ** Choosing alt 0 in insn 1804: (0) =v (1) %0 (2) vm (3) v {*fma_fmadd_df} Creating newreg=4707 from oldreg=1801,

[Bug rtl-optimization/92283] [10 Regression] 454.calculix miscomparison since r276645 with -O2 -march=znver2

2019-11-29 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92283 --- Comment #27 from Vladimir Makarov --- Author: vmakarov Date: Fri Nov 29 22:04:21 2019 New Revision: 278865 URL: https://gcc.gnu.org/viewcvs?rev=278865&root=gcc&view=rev Log: 2019-11-29 Vladimir Makarov PR rtl-optimization/92283

[Bug rtl-optimization/92176] LRA problem with reloads for subreg operands

2019-12-02 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92176 --- Comment #5 from Vladimir Makarov --- (In reply to Andreas Krebbel from comment #3) > 276.ira: > > > /* Give the backend a chance to disallow the mode change. */ > if (GET_MODE_CLASS (xmode) != MODE_COMPLEX_INT > && GET_MODE_

[Bug rtl-optimization/92176] LRA problem with reloads for subreg operands

2019-12-04 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92176 --- Comment #6 from Vladimir Makarov --- (In reply to Vladimir Makarov from comment #5) > > I'll investigate this problem more. Hi, Andreas. The rtlanal code (!lra_in_progress) was added to GCC since the first patch introducing LRA. As I wrot

[Bug rtl-optimization/92176] LRA problem with reloads for subreg operands

2019-12-06 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92176 --- Comment #8 from Vladimir Makarov --- Author: vmakarov Date: Fri Dec 6 19:30:37 2019 New Revision: 279061 URL: https://gcc.gnu.org/viewcvs?rev=279061&root=gcc&view=rev Log: 2019-12-06 Andreas Krebbel Vladimir Makarov

[Bug rtl-optimization/92176] LRA problem with reloads for subreg operands

2019-12-06 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92176 --- Comment #9 from Vladimir Makarov --- Thank you, Andreas. I've committed the patch with your changes in the test.

[Bug rtl-optimization/92796] [10 Regression] ICE in lra_assign, at lra-assigns.c:1646 on powerpc64le-linux-gnu

2019-12-09 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92796 --- Comment #7 from Vladimir Makarov --- (In reply to Peter Bergner from comment #6) > > Vlad (or Jeff), can you point me to where this is supposed to be handled? > I don't think I see where LRA verifies the reg_renumber[regno] values are > stil

[Bug rtl-optimization/92796] [10 Regression] ICE in lra_assign, at lra-assigns.c:1646 on powerpc64le-linux-gnu

2019-12-09 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92796 --- Comment #8 from Vladimir Makarov --- (In reply to Vladimir Makarov from comment #7) > A very interesting case, Peter. I reproduced the case too. I can take it > from here if you don't mind. The solution I see for this problem is to > chec

[Bug rtl-optimization/92796] [10 Regression] ICE in lra_assign, at lra-assigns.c:1646 on powerpc64le-linux-gnu

2019-12-09 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92796 --- Comment #10 from Vladimir Makarov --- (In reply to Vladimir Makarov from comment #7) > > > I'm guessing this was never a problem before I added the code to not add > conflicts for copies. Before then, any two pseudos/registers that were li

[Bug rtl-optimization/92796] [10 Regression] ICE in lra_assign, at lra-assigns.c:1646 on powerpc64le-linux-gnu

2019-12-10 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92796 --- Comment #11 from Vladimir Makarov --- Author: vmakarov Date: Tue Dec 10 22:07:57 2019 New Revision: 279204 URL: https://gcc.gnu.org/viewcvs?rev=279204&root=gcc&view=rev Log: 2019-12-10 Vladimir Makarov PR rtl-optimization/92796

[Bug target/92905] [10 Regression] Spills float-int union to memory

2019-12-18 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92905 --- Comment #5 from Vladimir Makarov --- (In reply to Jakub Jelinek from comment #3) > Note, it isn't about , using rm in the first alternative of the > reverted define_insn works well too, as well as swapping the alternatives > (that is in that

[Bug target/92905] [10 Regression] Spills float-int union to memory

2019-12-19 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92905 --- Comment #6 from Vladimir Makarov --- Author: vmakarov Date: Thu Dec 19 21:59:47 2019 New Revision: 279596 URL: https://gcc.gnu.org/viewcvs?rev=279596&root=gcc&view=rev Log: 2019-12-19 Vladimir Makarov PR target/92905 * lr

[Bug inline-asm/93027] ICE: in match_reload, at lra-constraints.c:1060

2020-01-08 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93027 --- Comment #1 from Vladimir Makarov --- Thank you for the report. I've started working on it. As changes in constraint processing needs a lot of testing, I think the patch will be read on Friday or on the next week.

[Bug c++/93207] [concepts] Variadic concepts refuse to compile when function definition is not inline

2020-01-10 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93207 --- Comment #1 from Vladimir Makarov --- Author: vmakarov Date: Fri Jan 10 20:07:45 2020 New Revision: 280133 URL: https://gcc.gnu.org/viewcvs?rev=280133&root=gcc&view=rev Log: 2020-01-10 Vladimir Makarov PR inline-asm/93207

[Bug c++/93207] [concepts] Variadic concepts refuse to compile when function definition is not inline

2020-01-10 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93207 --- Comment #2 from Vladimir Makarov --- Author: vmakarov Date: Fri Jan 10 20:18:00 2020 New Revision: 280135 URL: https://gcc.gnu.org/viewcvs?rev=280135&root=gcc&view=rev Log: 2020-01-10 Vladimir Makarov PR inline-asm/93207

[Bug inline-asm/93027] ICE: in match_reload, at lra-constraints.c:1060

2020-01-10 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93027 --- Comment #2 from Vladimir Makarov --- Sorry, I did a mistake in PR number and automatic commits reporting did not work. Here are the patches fixing the PR: https://gcc.gnu.org/viewcvs/gcc?view=revision&revision=280133 https://gcc.gnu.org/vie

[Bug inline-asm/93027] ICE: in match_reload, at lra-constraints.c:1060

2020-01-10 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93027 --- Comment #3 from Vladimir Makarov --- Author: vmakarov Date: Fri Jan 10 20:45:19 2020 New Revision: 280138 URL: https://gcc.gnu.org/viewcvs?rev=280138&root=gcc&view=rev Log: 2020-01-10 Vladimir Makarov PR inline-asm/93027

[Bug rtl-optimization/91333] [9/10 Regression] suboptimal register allocation for inline asm

2020-01-17 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91333 --- Comment #6 from Vladimir Makarov --- (In reply to Marc Glisse from comment #5) > > However, if I add -mavx, I get > > vmovapd %xmm0, %xmm2 > vmovapd %xmm1, %xmm4 > vmovapd %xmm1, %xmm0 > vaddsd %xmm0, %xmm4, %xmm0 >

[Bug rtl-optimization/93272] LRA: EH reg allocated to hold local variable

2020-01-27 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93272 --- Comment #4 from Vladimir Makarov --- (In reply to Andreas Krebbel from comment #3) > Created attachment 47714 [details] > IRA EH fix - only when added at start of BB > > A probably better version of the fix. This version only reverts the > a

[Bug target/91320] [9/10 Regression] x86-64 code generation / register allocation regressed.

2020-01-30 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91320 Vladimir Makarov changed: What|Removed |Added CC||vmakarov at gcc dot gnu.org

[Bug target/91320] [9/10 Regression] x86-64 code generation / register allocation regressed.

2020-01-31 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91320 --- Comment #7 from Vladimir Makarov --- I've committed a patch solving PR91333. The patch also solves the current PR. https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=2a07345c4f8dabc286fc470e76c53473e5bc3eb7 So I guess we can close the current

[Bug tree-optimization/93055] [10 Regression] accumulation loops in stepanov_vector benchmark use more instruction level parpallelism

2020-01-31 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93055 --- Comment #10 from Vladimir Makarov --- (In reply to Jakub Jelinek from comment #9) > Vlad, any thoughts on this? A pseudo in the loop happens to be spilled. So the pseudo is changed onto its equivalence which is an invariant to the loop.

[Bug rtl-optimization/91333] [9/10 Regression] suboptimal register allocation for inline asm

2020-02-02 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91333 --- Comment #12 from Vladimir Makarov --- (In reply to Christophe Lyon from comment #10) > (In reply to Jeffrey A. Law from comment #9) > > Fixed by Vlad's patch on the trunk. > > This patch causes regressions: > aarch64: > I've committed one

[Bug rtl-optimization/91333] [9/10 Regression] suboptimal register allocation for inline asm

2020-02-04 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91333 --- Comment #16 from Vladimir Makarov --- (In reply to rsand...@gcc.gnu.org from comment #15) > (In reply to Jakub Jelinek from comment #14) > > I think what matters is whether the new asm for those is the same or better > > than before. If the

[Bug rtl-optimization/93564] [10 Regression] 470.lbm regresses by 25% on znver2 with -Ofast -march=native LTO and PGO since r10-6384-g2a07345c4f8dabc2

2020-02-05 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93564 --- Comment #1 from Vladimir Makarov --- Thank your for reporting this. I've changed RA heuristics. It is very rare case when you change heuristics and there is no one SPEC benchmark with performance degradation. Usually some benchmarks improv

[Bug rtl-optimization/93561] [bounds checking] memory overflow for spill_for

2020-02-06 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93561 --- Comment #1 from Vladimir Makarov --- Thank you for reporting this. It seems the bug did not manifested itself before as the most targets have virtual hard registers as the last hard regs. I'll commit your patch today. Thank you again.

[Bug rtl-optimization/90378] [9/10 regression] -Os -flto miscompiles 454.calculix after r266385 on Arm

2020-02-18 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90378 --- Comment #4 from Vladimir Makarov --- > Miscompilation occurs in same configuration: arm-linux-gnueabihf at -O2 > -flto. > I don't see how these two patches *directly* resulted in miscompilation. Although it might trigger some latent bug.

[Bug rtl-optimization/93564] [10 Regression] 470.lbm regresses by 25% on znver2 with -Ofast -march=native LTO and PGO since r10-6384-g2a07345c4f8dabc2

2020-02-27 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93564 --- Comment #3 from Vladimir Makarov --- I checked the new results https://lnt.opensuse.org/db_default/v4/SPEC/graph?plot.0=288.240.0 It seems the patch solved the problem.

[Bug rtl-optimization/93974] [10 Regression] ICE in decompose_normal_address, at rtlanal.c:6403 on powerpc64le-linux-gnu since r10-6762

2020-03-02 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93974 --- Comment #13 from Vladimir Makarov --- (In reply to Peter Bergner from comment #4) > I'm CCing Vlad, since I need some guidance/help for some LRA questions. > > Vlad, do you have some guidance on what should be done when we see > an address l

[Bug middle-end/55889] [4.8 Regression] ICE: in move_op_ascend, at sel-sched.c:6153 with -fschedule-insns -fselective-scheduling

2013-02-06 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55889 --- Comment #27 from Vladimir Makarov 2013-02-06 21:36:59 UTC --- (In reply to comment #26) > You are right, your suggestions is what I sketched in comment #21 as choices 1 > or 2. Sorry for my unclear expalanation of what was actually ha

[Bug rtl-optimization/56225] [4.8 Regression] ICE in lra-constraints.c when executing the testsuite with -m32 -march=pentium3

2013-02-07 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56225 --- Comment #2 from Vladimir Makarov 2013-02-07 17:15:30 UTC --- Author: vmakarov Date: Thu Feb 7 17:15:02 2013 New Revision: 195856 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=195856 Log: 2013-02-07 Vladimir Makarov

[Bug rtl-optimization/56246] [4.8 regression] ICE in assign_by_spills, at lra-assigns.c:1262

2013-02-08 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56246 --- Comment #2 from Vladimir Makarov 2013-02-08 16:39:37 UTC --- (In reply to comment #1) > -m32 -march=i686 -mtune=generic -O2 -fno-omit-frame-pointer -fpic > needed for me. > Regressed with LRA merge. I'll be working on it.

[Bug rtl-optimization/56246] [4.8 regression] ICE in assign_by_spills, at lra-assigns.c:1262

2013-02-08 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56246 --- Comment #3 from Vladimir Makarov 2013-02-08 21:59:16 UTC --- Author: vmakarov Date: Fri Feb 8 21:59:11 2013 New Revision: 195902 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=195902 Log: 2013-02-08 Vladimir Makarov

[Bug inline-asm/56148] [4.8 Regression] inline asm matching constraint with different mode

2013-02-12 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56148 --- Comment #8 from Vladimir Makarov 2013-02-12 17:44:56 UTC --- Author: vmakarov Date: Tue Feb 12 17:44:47 2013 New Revision: 195988 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=195988 Log: 2013-02-12 Vladimir Makarov

[Bug target/56184] [4.8 Regression] Internal compiler error in push_reload during bootstrap stage 2

2013-02-13 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56184 --- Comment #7 from Vladimir Makarov 2013-02-13 15:15:14 UTC --- (In reply to comment #6) > > Unfortunately I'm not really familiar with the live range splitting code; > maybe > Vladimir can help with this? Yes, Ulrich. I've started

[Bug target/56184] [4.8 Regression] Internal compiler error in push_reload during bootstrap stage 2

2013-02-13 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56184 --- Comment #8 from Vladimir Makarov 2013-02-13 17:40:33 UTC --- Author: vmakarov Date: Wed Feb 13 17:40:22 2013 New Revision: 196019 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=196019 Log: 2013-02-13 Vladimir Makarov

[Bug rtl-optimization/56339] [4.8 Regression]: Suboptimal register allocation

2013-02-15 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56339 --- Comment #5 from Vladimir Makarov 2013-02-15 16:48:19 UTC --- (In reply to comment #4) > Perhaps for regmove IRA classes should be set up unconditionally: > > Index: regmove.c > ===

[Bug rtl-optimization/56348] internal compiler error in assign_by_spills with -m32 -fPIC -msse2

2013-02-15 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56348 Vladimir Makarov changed: What|Removed |Added CC||vmakarov at gcc dot gnu.org

[Bug rtl-optimization/56348] internal compiler error in assign_by_spills with -m32 -fPIC -msse2

2013-02-15 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56348 --- Comment #2 from Vladimir Makarov 2013-02-15 19:17:16 UTC --- Author: vmakarov Date: Fri Feb 15 19:17:02 2013 New Revision: 196090 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=196090 Log: 2013-02-15 Vladimir Makarov

[Bug rtl-optimization/56348] internal compiler error in assign_by_spills with -m32 -fPIC -msse2

2013-02-18 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56348 Vladimir Makarov changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|

[Bug inline-asm/56148] [4.8 Regression] inline asm matching constraint with different mode

2013-02-22 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56148 --- Comment #15 from Vladimir Makarov 2013-02-22 16:30:33 UTC --- Author: vmakarov Date: Fri Feb 22 16:30:22 2013 New Revision: 196223 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=196223 Log: 2013-02-22 Vladimir Makarov

[Bug middle-end/56461] [4.8 Regression] GCC is leaking lots of memory

2013-02-26 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56461 --- Comment #5 from Vladimir Makarov 2013-02-26 20:45:57 UTC --- (In reply to comment #4) > Created attachment 29544 [details] > gcc48-pr56461-2.patch > Sorry, I should have checked on leaks when I submitted LRA first time. The patch

[Bug target/54338] internal compiler error: in find_costs_and_classes, at ira-costs.c:1711

2012-08-31 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54338 --- Comment #2 from Vladimir Makarov 2012-08-31 18:35:17 UTC --- IRA can not find super set of GENERAL_REGS and IWMMXT_GR_REGS. It should not happen as ALL_REGS exits as the last resort for this. GCC documentation contains @findex ALL_REGS @fi

[Bug rtl-optimization/54991] [LRA] internal compiler error: in lra_assign, at lra-assigns.c:1361

2012-10-20 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54991 --- Comment #2 from Vladimir Makarov 2012-10-21 02:47:32 UTC --- Author: vmakarov Date: Sun Oct 21 02:47:28 2012 New Revision: 192645 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=192645 Log: 2012-10-20 Vladimir Makarov

[Bug bootstrap/55048] [4.8 Regression] libjava bootstrap failure on trunk after LRA merge

2012-10-24 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55048 --- Comment #2 from Vladimir Makarov 2012-10-24 15:35:17 UTC --- Author: vmakarov Date: Wed Oct 24 15:35:12 2012 New Revision: 192770 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=192770 Log: 2012-10-24 Vladimir Makarov

[Bug bootstrap/55049] [4.8 Regression] bootstrap failed with --with-multilib-list=m32,m64,mx32

2012-10-24 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55049 --- Comment #1 from Vladimir Makarov 2012-10-24 17:35:50 UTC --- Author: vmakarov Date: Wed Oct 24 17:35:37 2012 New Revision: 192771 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=192771 Log: 2012-10-24 Vladimir Makarov

[Bug rtl-optimization/55055] [4.8 regression] RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1123

2012-10-24 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55055 --- Comment #2 from Vladimir Makarov 2012-10-24 20:02:12 UTC --- Author: vmakarov Date: Wed Oct 24 20:02:08 2012 New Revision: 192779 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=192779 Log: 2012-10-24 Vladimir Makarov

[Bug bootstrap/55067] [4.8 Regression] AIX bootstrap failure due to lra.c loc_t

2012-10-24 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55067 --- Comment #2 from Vladimir Makarov 2012-10-25 02:31:36 UTC --- Author: vmakarov Date: Thu Oct 25 02:31:31 2012 New Revision: 192794 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=192794 Log: 2012-10-24 Vladimir Makarov

[Bug regression/55050] Regression test failure slp-21.c on arm-linux-gnueabi

2012-10-24 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55050 --- Comment #4 from Vladimir Makarov 2012-10-25 04:20:00 UTC --- Author: vmakarov Date: Thu Oct 25 04:19:43 2012 New Revision: 192797 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=192797 Log: 2012-10-24 Vladimir Makarov

[Bug bootstrap/55068] [4.8 Regression] AIX bootstrap in push_reload() after LRA merge

2012-10-24 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55068 --- Comment #2 from Vladimir Makarov 2012-10-25 04:20:00 UTC --- Author: vmakarov Date: Thu Oct 25 04:19:43 2012 New Revision: 192797 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=192797 Log: 2012-10-24 Vladimir Makarov

[Bug rtl-optimization/55106] ice: Maximum number of LRA constraint passes is achieved (15)

2012-10-28 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55106 --- Comment #2 from Vladimir Makarov 2012-10-29 00:42:30 UTC --- Author: vmakarov Date: Mon Oct 29 00:42:25 2012 New Revision: 192904 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=192904 Log: 2012-10-28 Vladimir Makarov

[Bug rtl-optimization/55106] ice: Maximum number of LRA constraint passes is achieved (15)

2012-10-29 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55106 --- Comment #4 from Vladimir Makarov 2012-10-29 14:42:21 UTC --- Author: vmakarov Date: Mon Oct 29 14:42:05 2012 New Revision: 192944 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=192944 Log: 2012-10-29 Vladimir Makarov

[Bug middle-end/55116] [4.8 Regression] LRA failed to decompose ASHIFT

2012-10-29 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55116 --- Comment #2 from Vladimir Makarov 2012-10-29 16:37:08 UTC --- Author: vmakarov Date: Mon Oct 29 16:36:57 2012 New Revision: 192949 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=192949 Log: 2012-10-29 Vladimir Makarov

[Bug middle-end/55150] Crash in copy_rtx

2012-10-31 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55150 --- Comment #2 from Vladimir Makarov 2012-10-31 18:41:26 UTC --- Author: vmakarov Date: Wed Oct 31 18:41:18 2012 New Revision: 193042 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=193042 Log: 2012-10-31 Vladimir Makarov

[Bug middle-end/55150] Crash in copy_rtx

2012-11-01 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55150 --- Comment #5 from Vladimir Makarov 2012-11-01 19:02:48 UTC --- Author: vmakarov Date: Thu Nov 1 19:02:40 2012 New Revision: 193065 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=193065 Log: 2012-11-01 Vladimir Makarov

[Bug middle-end/55130] [4.8 Regression] ICE in insn_rhs_dead_pseudo_p, at lra-constraints.c:3224

2012-11-02 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55130 --- Comment #2 from Vladimir Makarov 2012-11-02 14:44:23 UTC --- Author: vmakarov Date: Fri Nov 2 14:44:12 2012 New Revision: 193096 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=193096 Log: 2012-11-02 Vladimir Makarov

[Bug middle-end/55150] Crash in copy_rtx

2012-11-02 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55150 --- Comment #6 from Vladimir Makarov 2012-11-02 14:44:24 UTC --- Author: vmakarov Date: Fri Nov 2 14:44:12 2012 New Revision: 193096 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=193096 Log: 2012-11-02 Vladimir Makarov

[Bug rtl-optimization/55151] [4.8 Regression] ICE: in assign_by_spills, at lra-assigns.c:1217 with -fPIC

2012-11-05 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55151 --- Comment #2 from Vladimir Makarov 2012-11-05 16:38:34 UTC --- Author: vmakarov Date: Mon Nov 5 16:38:27 2012 New Revision: 193170 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=193170 Log: 2012-11-05 Vladimir Makarov

[Bug rtl-optimization/55122] [4.8 Regression] ICE: maximum number of LRA constraint passes is achieved (15)

2012-11-07 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55122 --- Comment #3 from Vladimir Makarov 2012-11-07 22:11:13 UTC --- Author: vmakarov Date: Wed Nov 7 22:11:08 2012 New Revision: 193310 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=193310 Log: 2012-11-07 Vladimir Makarov

[Bug rtl-optimization/55151] [4.8 Regression] ICE: in assign_by_spills, at lra-assigns.c:1217 with -fPIC

2012-11-07 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55151 --- Comment #4 from Vladimir Makarov 2012-11-07 22:20:26 UTC --- Author: vmakarov Date: Wed Nov 7 22:20:15 2012 New Revision: 193311 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=193311 Log: 2012-11-07 Vladimir Makarov

[Bug rtl-optimization/55151] [4.8 Regression] ICE: in assign_by_spills, at lra-assigns.c:1217 with -fPIC

2012-11-07 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55151 --- Comment #5 from Vladimir Makarov 2012-11-07 22:43:35 UTC --- Author: vmakarov Date: Wed Nov 7 22:43:30 2012 New Revision: 193317 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=193317 Log: 2012-11-07 Vladimir Makarov

[Bug rtl-optimization/55151] [4.8 Regression] ICE: in assign_by_spills, at lra-assigns.c:1217 with -fPIC

2012-11-09 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55151 --- Comment #6 from Vladimir Makarov 2012-11-09 14:28:49 UTC --- Author: vmakarov Date: Fri Nov 9 14:28:40 2012 New Revision: 193361 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=193361 Log: 2012-11-09 Vladimir Makarov

[Bug rtl-optimization/55154] [4.8 Regression] ICE: in curr_insn_transform, at lra-constraints.c:2702 with custom flags

2012-11-09 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55154 --- Comment #4 from Vladimir Makarov 2012-11-09 15:33:27 UTC --- Author: vmakarov Date: Fri Nov 9 15:33:19 2012 New Revision: 193364 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=193364 Log: 2012-11-09 Vladimir Makarov

[Bug rtl-optimization/57468] [4.9 Regression] 26% performance drop on important benchmark after r199298.

2013-06-06 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57468 Vladimir Makarov changed: What|Removed |Added CC||vmakarov at gcc dot gnu.org

[Bug rtl-optimization/55342] [4.8/4.9 Regression] [LRA,x86] Non-optimal code for simple loop with LRA

2013-06-06 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55342 Vladimir Makarov changed: What|Removed |Added CC||vmakarov at gcc dot gnu.org

[Bug rtl-optimization/57447] [4.9 Regression] ICE on 435.gromacs from spec2006 after r199298

2013-06-06 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57447 Vladimir Makarov changed: What|Removed |Added CC||vmakarov at gcc dot gnu.org

[Bug rtl-optimization/57676] [4.8/4.9 Regression] ICE: Maximum number of LRA constraint passes is achieved (30)

2013-06-27 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57676 --- Comment #2 from Vladimir Makarov --- That is a pretty interesting test case. Roughly speaking, we have chains of divmodsi4 insns: p1 / p2 ... p3 / p1 P1 (and many others) gets AX. But it is necessary for P3 in the second insn. So on each

[Bug rtl-optimization/57963] LRA S/390: esa mode failure memcpy-chk

2013-08-01 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57963 --- Comment #1 from Vladimir Makarov --- Thanks, Andreas. I've reproduced the bug. I hope to fix it on this week.

[Bug rtl-optimization/57459] [4.8 Regression] LRA inheritance bug

2013-08-14 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57459 --- Comment #9 from Vladimir Makarov --- (In reply to Jakub Jelinek from comment #8) > Created attachment 30643 [details] > rh995446.i > > We've got this reported in > https://bugzilla.redhat.com/show_bug.cgi?id=995446 too. > I've created a self-

[Bug middle-end/58335] S/390: reload vs lra regression - testcase builtin-in-setjmp

2013-09-10 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58335 Vladimir Makarov changed: What|Removed |Added CC||vmakarov at gcc dot gnu.org

[Bug middle-end/58335] S/390: reload vs lra regression - testcase builtin-in-setjmp

2013-09-12 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58335 --- Comment #2 from Vladimir Makarov --- Author: vmakarov Date: Thu Sep 12 18:23:09 2013 New Revision: 202536 URL: http://gcc.gnu.org/viewcvs?rev=202536&root=gcc&view=rev Log: 2013-09-12 Vladimir Makarov PR middle-end/58335 * lra-elim

[Bug middle-end/58418] [4.9 Regression] wrong code at -O2 and -O3 on x86_64-linux-gnu (in 32-bit mode)

2013-09-16 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58418 --- Comment #2 from Vladimir Makarov --- Author: vmakarov Date: Mon Sep 16 15:12:22 2013 New Revision: 202630 URL: http://gcc.gnu.org/viewcvs?rev=202630&root=gcc&view=rev Log: 2013-09-16 Vladimir Makarov PR middle-end/58418 * lra-cons

[Bug rtl-optimization/58438] [4.9 Regression] ICE: in check_rtl, at lra.c:2036

2013-09-18 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58438 --- Comment #5 from Vladimir Makarov --- Author: vmakarov Date: Wed Sep 18 18:24:49 2013 New Revision: 202714 URL: http://gcc.gnu.org/viewcvs?rev=202714&root=gcc&view=rev Log: 2013-09-18 Vladimir Makarov PR rtl-optimization/58438 * lr

[Bug rtl-optimization/50107] [IRA, i386] allocates regiters in very non-optimal way

2011-08-18 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50107 --- Comment #8 from Vladimir Makarov 2011-08-18 14:56:46 UTC --- Author: vmakarov Date: Thu Aug 18 14:56:36 2011 New Revision: 177865 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=177865 Log: 2011-08-17 Vladimir Makarov PR rtl-op

[Bug rtl-optimization/49890] IRA spill with plenty of available registers

2011-08-18 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=49890 --- Comment #2 from Vladimir Makarov 2011-08-18 17:06:26 UTC --- Author: vmakarov Date: Thu Aug 18 17:06:18 2011 New Revision: 177874 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=177874 Log: 2011-08-18 Vladimir Makarov PR rtl-op

[Bug rtl-optimization/49936] [4.7 Regression] IRA handles CANNOT_CHANGE_MODE_CLASS poorly, + spills to memory on 4.7

2011-08-19 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=49936 --- Comment #5 from Vladimir Makarov 2011-08-19 22:17:29 UTC --- Author: vmakarov Date: Fri Aug 19 22:17:26 2011 New Revision: 177916 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=177916 Log: 2011-08-19 Vladimir Makarov PR rtl-op

[Bug rtl-optimization/53125] Very slow register allocation on SPARC

2012-05-10 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53125 --- Comment #5 from Vladimir Makarov 2012-05-10 19:58:09 UTC --- Author: vmakarov Date: Thu May 10 19:58:01 2012 New Revision: 187373 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=187373 Log: 2012-05-10 Vladimir Makarov PR rtl-op

[Bug rtl-optimization/53700] [4.7 regression] ICE in reload_cse_simplify_operands, at postreload.c:403

2012-06-18 Thread vmakarov at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53700 --- Comment #6 from Vladimir Makarov 2012-06-18 18:34:12 UTC --- Author: vmakarov Date: Mon Jun 18 18:34:01 2012 New Revision: 188750 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=188750 Log: 2012-06-18 Vladimir Makarov PR rtl-op

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