[Bug target/65096] Illegal memory access beyond packed struct ARCH: ppc64

CC||ramana at gcc dot gnu.org --- Comment #3 from Ramana Radhakrishnan --- Andrew, Did you manage to reproduce this on aarch64 or did you really mean ppc64 in target ? Ramana

[Bug target/67474] [6 regression] tree-vect-loop.c:2759:1: error: insn does not satisfy its constraints breaks ARM bootstrap

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67474 Ramana Radhakrishnan changed: What|Removed |Added CC||ramana at gcc dot gnu.org

[Bug target/65697] __atomic memory barriers not strong enough for __sync builtins

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65697 Ramana Radhakrishnan changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug c/65345] ICE with _Generic selection on _Atomic int

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65345 Ramana Radhakrishnan changed: What|Removed |Added CC||clyon at gcc dot gnu.org --- Comm

[Bug target/67848] ICE on gcc.dg/atomic/pr65345-4.c and gcc.dg/pr65345-3.c

||ramana at gcc dot gnu.org Resolution|--- |DUPLICATE --- Comment #1 from Ramana Radhakrishnan --- dup of 65345 *** This bug has been marked as a duplicate of bug 65345 ***

[Bug c/65345] ICE with _Generic selection on _Atomic int

, ||sparc, powerpc* Status|RESOLVED|REOPENED CC||ramana at gcc dot gnu.org Resolution|FIXED |--- --- Comment #18 from Ramana Radhakrishnan --- This is

[Bug middle-end/67868] New: [4.9/5/6 regression] ICE on targets with section anchors.

Priority: P3 Component: middle-end Assignee: unassigned at gcc dot gnu.org Reporter: ramana at gcc dot gnu.org Target Milestone: --- Given this testcase on targets with section anchors. I see the following ICE on arm, aarch64 and powerpc targets. $> cat /tmp/tes

[Bug middle-end/67868] [4.9/5/6 regression] ICE in named section handling on targets with section anchors.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67868 Ramana Radhakrishnan changed: What|Removed |Added Keywords||ice-on-valid-code Tar

[Bug middle-end/67868] [4.9/5/6 regression] ICE in named section handling on targets with section anchors.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67868 --- Comment #2 from Ramana Radhakrishnan --- However the ICE is specific to the VTV feature I think and not generally applicable.

[Bug c/65345] ICE with _Generic selection on _Atomic int

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65345 --- Comment #20 from Ramana Radhakrishnan --- Author: ramana Date: Tue Oct 6 15:09:43 2015 New Revision: 228526 URL: https://gcc.gnu.org/viewcvs?rev=228526&root=gcc&view=rev Log: Fix PR c/65345 for AArch64 2015-10-06 Ramana Radhakrishnan

[Bug other/67868] ICE in handling VTV sections for targets with section anchors.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67868 Ramana Radhakrishnan changed: What|Removed |Added Component|middle-end |other Target Milestone|4.9.4

[Bug c/65345] ICE with _Generic selection on _Atomic int

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65345 --- Comment #23 from Ramana Radhakrishnan --- Author: ramana Date: Wed Oct 7 08:37:35 2015 New Revision: 228562 URL: https://gcc.gnu.org/viewcvs?rev=228562&root=gcc&view=rev Log: Fix PR c/65345 for arm 2015-10-07 Ramana Radhakrishnan

[Bug other/67868] ICE in handling VTV sections for targets with section anchors.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67868 --- Comment #5 from Ramana Radhakrishnan --- (In reply to Richard Biener from comment #3) > What GCC version (with VTV enabled) did work for you? I do not think any version of GCC with VTV enabled has worked for AArch64 or ARM - I failed to noti

[Bug target/67366] Poor assembly generation for unaligned memory accesses on ARM v6 & v7 cpus

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67366 --- Comment #13 from Ramana Radhakrishnan --- Author: ramana Date: Fri Oct 9 10:53:31 2015 New Revision: 228643 URL: https://gcc.gnu.org/viewcvs?rev=228643&root=gcc&view=rev Log: [Patch PR target/67366 1/2] [ARM] - Add movmisalignhi / si patter

[Bug target/63304] Aarch64 pc-relative load offset out of range

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63304 --- Comment #26 from Ramana Radhakrishnan --- Author: ramana Date: Fri Oct 9 10:58:06 2015 New Revision: 228644 URL: https://gcc.gnu.org/viewcvs?rev=228644&root=gcc&view=rev Log: [AArch64] Handle literal pools for functions > 1 MiB in size. T

[Bug target/67366] Poor assembly generation for unaligned memory accesses on ARM v6 & v7 cpus

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67366 Ramana Radhakrishnan changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/63304] Aarch64 pc-relative load offset out of range

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63304 --- Comment #27 from Ramana Radhakrishnan --- (In reply to Ramana Radhakrishnan from comment #26) > Author: ramana > Date: Fri Oct 9 10:58:06 2015 > New Revision: 228644 > > URL: https://gcc.gnu.org/viewcvs?rev=228644&root=gcc&view=rev > Log: >

[Bug target/67366] Poor assembly generation for unaligned memory accesses on ARM v6 & v7 cpus

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67366 --- Comment #15 from Ramana Radhakrishnan --- Author: ramana Revision: 228644 Modified property: svn:log Modified: svn:log at Fri Oct 9 11:08:05 2015 -- --- svn:log (or

[Bug target/63304] Aarch64 pc-relative load offset out of range

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63304 --- Comment #28 from Ramana Radhakrishnan --- Author: ramana Revision: 228644 Modified property: svn:log Modified: svn:log at Fri Oct 9 11:08:05 2015 -- --- svn:log (or

[Bug target/67745] [ARM] wrong alignments when __attribute__ ((optimize,target,align) is used

||2015-10-10 CC||ramana at gcc dot gnu.org Assignee|unassigned at gcc dot gnu.org |chrbr at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #4 from Ramana Radhakrishnan --- Confirmed.

[Bug rtl-optimization/67715] [6 Regression][ARM] ICE in cselib.c during reload_cse_regs

||2015-10-10 CC||ramana at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #1 from Ramana Radhakrishnan --- Confirmed.

[Bug middle-end/67714] [6 Regression] signed char is zero-extended instead of sign-extended

||2015-10-10 CC||ramana at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #4 from Ramana Radhakrishnan --- Confirmed.

[Bug target/63346] xserver_xorg-server-1.15.1 crash on RaspberryPi when compiled with gcc-4.9

||2015-10-10 CC||ramana at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #2 from Ramana Radhakrishnan --- Please try and provide a testcase to figure out what the problem might be. Without this it

[Bug tree-optimization/60919] [arm] gcc fails to tail call __builtin_ffsll

||2015-10-10 CC||ramana at gcc dot gnu.org Component|target |tree-optimization Ever confirmed|0 |1 Severity|minor |enhancement --- Comment #1

[Bug driver/60358] [patch] ARM support broken for Haiku

||2015-10-10 CC||ramana at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #3 from Ramana Radhakrishnan --- No activity on this report for quite a while . Patches need to be on gcc-patc

[Bug target/67366] Poor assembly generation for unaligned memory accesses on ARM v6 & v7 cpus

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67366 --- Comment #17 from Ramana Radhakrishnan --- (In reply to Fredrik Hederstierna from comment #16) > Could this fix also possibly improve: > Bug 67507 - "Code size increase with -Os from GCC 4.8.x to GCC 4.9.x for ARM > thumb1", which also seems r

[Bug target/67880] [ARM] -fno-align-functions does not work for thumb

||ramana at gcc dot gnu.org Resolution|--- |DUPLICATE --- Comment #2 from Ramana Radhakrishnan --- Dup of PR67745. *** This bug has been marked as a duplicate of bug 67745 ***

[Bug target/67745] [ARM] wrong alignments when __attribute__ ((optimize,target,align) is used

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67745 --- Comment #5 from Ramana Radhakrishnan --- *** Bug 67880 has been marked as a duplicate of this bug. ***

[Bug target/67871] LTO falis for ARM big-endian

||2015-10-15 CC||ramana at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #2 from Ramana Radhakrishnan --- Do you have big endian multilibs suitably built ? How did you configure your toolchain ? I

[Bug target/67929] [4.9/5/6 Regression][arm] Wrong code for FP mult-by-power-of-2 + int conversion

||2015-10-15 CC||ramana at gcc dot gnu.org Version|6.0 |4.9.0 Target Milestone|--- |4.9.4 Ever confirmed|0 |1 --- Comment #2 from Ramana

[Bug testsuite/67948] xor-and.c needs updating after r228661

||2015-10-15 CC||ramana at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #1 from Ramana Radhakrishnan --- Confirmed.

[Bug target/67383] reload_cse_simplify_operands fails on ARMV7-M

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67383 Ramana Radhakrishnan changed: What|Removed |Added CC||ramana at gcc dot gnu.org

[Bug other/67868] ICE in handling VTV sections for targets with section anchors.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67868 --- Comment #6 from Ramana Radhakrishnan --- Author: ramana Date: Tue Oct 20 10:36:33 2015 New Revision: 229043 URL: https://gcc.gnu.org/viewcvs?rev=229043&root=gcc&view=rev Log: Fix VTV for targets with section anchors. 2015-10-20 Ramana Rad

[Bug other/67868] ICE in handling VTV sections for targets with section anchors.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67868 --- Comment #7 from Ramana Radhakrishnan --- Author: ramana Date: Tue Oct 20 10:36:54 2015 New Revision: 229044 URL: https://gcc.gnu.org/viewcvs?rev=229044&root=gcc&view=rev Log: Fix VTV for targets with section anchors. 2015-10-20 Ramana Rad

[Bug other/67868] ICE in handling VTV sections for targets with section anchors.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67868 --- Comment #8 from Ramana Radhakrishnan --- Author: ramana Date: Tue Oct 20 10:39:30 2015 New Revision: 229045 URL: https://gcc.gnu.org/viewcvs?rev=229045&root=gcc&view=rev Log: Enable VTV for aarch64 and arm Requires fix for section anchors

[Bug target/66755] [ARM] TARGET_ASM_OUTPUT_MI_THUNK should be rewritten to an RTL implementation

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66755 Ramana Radhakrishnan changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/53440] [arm] generic thunk code fails for method which uses '...'

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=53440 Ramana Radhakrishnan changed: What|Removed |Added CC||jgreenhalgh at gcc dot gnu.org --

[Bug c++/67904] g++ crashes and asks for bugreport

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67904 Ramana Radhakrishnan changed: What|Removed |Added CC||ramana at gcc dot gnu.org

[Bug target/63304] Aarch64 pc-relative load offset out of range

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63304 --- Comment #29 from Ramana Radhakrishnan --- Author: ramana Date: Thu Oct 22 04:26:50 2015 New Revision: 229160 URL: https://gcc.gnu.org/viewcvs?rev=229160&root=gcc&view=rev Log: [Patch AArch64 63304] Fix issue with global state. Jiong pointe

[Bug testsuite/67948] xor-and.c needs updating after r228661

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67948 --- Comment #3 from Ramana Radhakrishnan --- Author: ramana Date: Thu Oct 22 05:12:32 2015 New Revision: 229161 URL: https://gcc.gnu.org/viewcvs?rev=229161&root=gcc&view=rev Log: [PATCH][ARM] Fix for testcase after r228661 This patch addresses

[Bug testsuite/67948] xor-and.c needs updating after r228661

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67948 Ramana Radhakrishnan changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/68143] [5/6 Regression][ARM] Wrong code initialising struct member after zeroing out the whole struct

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68143 Ramana Radhakrishnan changed: What|Removed |Added CC||ramana at gcc dot gnu.org

[Bug tree-optimization/68198] [6 Regression]Excessive code size, compile time and memory usage bloat due to FSM threading in 453.povray

||2015-11-03 CC||ramana at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #2 from Ramana Radhakrishnan --- Confirmed - I'm also seeing this today with a patch that I was testing.

[Bug tree-optimization/68198] [6 Regression]Excessive code size, compile time and memory usage bloat due to FSM threading in 453.povray

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68198 Ramana Radhakrishnan changed: What|Removed |Added Target|arm, aarch64|arm, aarch64,x86_64, ppc64 --- Co

[Bug rtl-optimization/68205] [5 regression] ICE compiling gcc.c-torture/execute/20040709-2.c with -fno-common on arm-none-eabi

||4.9.3 Keywords||ice-on-valid-code Last reconfirmed||2015-11-05 CC||ramana at gcc dot gnu.org Ever confirmed|0 |1 Summary

[Bug target/63304] Aarch64 pc-relative load offset out of range

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63304 --- Comment #31 from Ramana Radhakrishnan --- (In reply to Evandro from comment #30) > The performance impact of always referring to constants as if they were far > away is significant on targets which do not fuse ADRP and LDR together. What ha

[Bug target/63304] Aarch64 pc-relative load offset out of range

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63304 --- Comment #35 from Ramana Radhakrishnan --- (In reply to Evandro from comment #32) > (In reply to Ramana Radhakrishnan from comment #31) > > (In reply to Evandro from comment #30) > > > The performance impact of always referring to constants as

[Bug target/68178] [arm] Relative address expressions bind at as-time, even if symbol is weak

||ramana at gcc dot gnu.org Assignee|unassigned at gcc dot gnu.org |ramana at gcc dot gnu.org --- Comment #9 from Ramana Radhakrishnan --- I'm testing a patch.

[Bug middle-end/67295] [ARM][6 Regression] FAIL: gcc.target/arm/builtin-bswap-1.c scan-assembler-times revshne\\t 1

||2015-11-07 CC||ramana at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #4 from Ramana Radhakrishnan --- (In reply to Alexandre Oliva from comment #3) > Still no luck on a x86_64-linux-gnu bu

[Bug target/68256] New: [6 regression] switching constant pools to rodata sections causes go bootstrap failure.

Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: ramana at gcc dot gnu.org Target Milestone: --- https://gcc.gnu.org/ml/gcc-patches/2015-11/msg00839.html

[Bug target/68256] [6 regression] switching constant pools to rodata sections causes go bootstrap failure.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68256 Ramana Radhakrishnan changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug target/68256] [6 regression] switching constant pools to rodata sections causes go bootstrap failure.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68256 --- Comment #2 from Ramana Radhakrishnan --- Author: ramana Date: Tue Nov 10 08:35:21 2015 New Revision: 230085 URL: https://gcc.gnu.org/viewcvs?rev=230085&root=gcc&view=rev Log: Workaround PR68256 on AArch64 > This is causing a bootstrap comp

[Bug other/58133] GCC should emit arm assembly following the unified syntax

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58133 Ramana Radhakrishnan changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/68223] [6 regression] arm_[su]min_cmp pattern fails

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68223 Ramana Radhakrishnan changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug middle-end/68134] [6 Regression] float64x1_t comparison ICE on aarch64-none-elf

, ||ramana at gcc dot gnu.org --- Comment #3 from Ramana Radhakrishnan --- Add author to CC.

[Bug other/67868] ICE in handling VTV sections for targets with section anchors.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67868 Ramana Radhakrishnan changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug rtl-optimization/67954] [5 / 6 Regression] internal compiler error: in patch_jump_insn, at cfgrtl.c:1303

Status|UNCONFIRMED |NEW Last reconfirmed||2015-11-19 CC||ramana at gcc dot gnu.org Summary|[5 Regression] internal |[5 / 6 Regression] internal |compiler error: in

[Bug rtl-optimization/67954] [5 / 6 Regression] internal compiler error: in patch_jump_insn, at cfgrtl.c:1303

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67954 --- Comment #3 from Ramana Radhakrishnan --- Created attachment 36771 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=36771&action=edit reduced testcase reduced testcase

[Bug target/68494] [ARM] Use vector multiply by lane

||2015-11-23 CC||ramana at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #1 from Ramana Radhakrishnan --- NTAPS is undefined. What's the current output and what output do you expect ?

[Bug target/64240] [5.0 Regression][AArch64] SMS-3.c causes runtime exception(segfault).

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64240 Ramana Radhakrishnan changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/64231] [5 Regression] SIGSEGV building glibc on aarch64-linux-gnu from r217852

||2015-01-13 CC||ramana at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #9 from Ramana Radhakrishnan --- Waiting on this one - no one seems to be able to reproduce this.

[Bug target/64149] -mno-lra bitrots, suggest to remove for GCC 5

||2015-01-13 CC||ramana at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #4 from Ramana Radhakrishnan --- I think there are patches for this one.

[Bug target/64231] [5 Regression] SIGSEGV building glibc on aarch64-linux-gnu from r217852

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64231 --- Comment #11 from Ramana Radhakrishnan --- (In reply to Andrew Pinski from comment #10) > What host compiler are you using? I am running into a similar issue (though > I have not reproduced it myself; only in an automated build) with the host

[Bug target/64379] VFP register restore in ARM epilogue can break indirect tailcalls

|UNCONFIRMED |NEW Last reconfirmed||2015-01-13 CC||ramana at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #8 from Ramana Radhakrishnan --- (In reply to Donn Seeley from comment #7

[Bug target/64379] VFP register restore in ARM epilogue can break indirect tailcalls

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64379 --- Comment #10 from Ramana Radhakrishnan --- (In reply to Eric Botcazou from comment #9) > > Uggh - these ancient options in the backend. mapcs-frame is quite ancient > > and isn't really something that's tested very often, no wonder it's rottin

[Bug target/64379] VFP register restore in ARM epilogue can break indirect tailcalls

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64379 --- Comment #14 from Ramana Radhakrishnan --- (In reply to Donn Seeley from comment #13) > BTW, this issue cropped up in Wind River Linux testing, not VxWorks. I have > no idea whether the VxWorks folks are using -mapcs-frame. WR Linux will > r

[Bug rtl-optimization/57518] [4.8 Regression] Redundant insn generated in LRA

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=57518 Ramana Radhakrishnan changed: What|Removed |Added CC||ramana at gcc dot gnu.org

[Bug ipa/61548] [5 Regression] FAIL: gcc.dg/tls/alias-1.c (internal compiler error)

||ramana at gcc dot gnu.org

[Bug tree-optimization/61523] [5 regression] Commit 211600 appears to have caused section type conflicts for ARM

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61523 Ramana Radhakrishnan changed: What|Removed |Added Status|WAITING |RESOLVED Resolution|---

[Bug rtl-optimization/64532] [4.9, 5 Regression] internal compiler error: Max. number of generated reload insns per insn is achieved (90)

||2015-01-15 CC||ramana at gcc dot gnu.org Summary|[5 Regression] internal |[4.9, 5 Regression] |compiler error: Max. number |internal compiler error: |of generated reload insns

[Bug target/64448] [5.0 regression] New middle-end pattern breaks vector BIF folding on AArch64.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64448 Ramana Radhakrishnan changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |ktkachov at gcc dot gnu.or

[Bug rtl-optimization/64082] virtual register elimination doing bad for local array

Status|UNCONFIRMED |ASSIGNED Last reconfirmed||2015-01-15 CC||ramana at gcc dot gnu.org Ever confirmed|0 |1

[Bug c++/63433] init_priority not working on ARM target

||2015-01-15 CC||ramana at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #1 from Ramana Radhakrishnan --- Please follow instructions on reporting bugs on the gcc website and provide a self contained

[Bug target/63394] Segmentation Fault with -O3 flag on ARM v61 Processor

||ramana at gcc dot gnu.org Resolution|--- |WORKSFORME --- Comment #3 from Ramana Radhakrishnan --- (In reply to Bruce Dale from comment #2) > gcc -v reports: > > Using built-in specs. > COLLECT_GCC=gcc > COLLECT_LTO_WRAPPER=/

[Bug target/64310] libgcc2.c:2051:1: internal compiler error: in curr_insn_transform, at lra-constraints.c:3383

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64310 Ramana Radhakrishnan changed: What|Removed |Added CC||ramana at gcc dot gnu.org

[Bug target/63949] Aarch64 instruction combiner does not optimize subsi_sxth function as expected (gcc.target/aarch64/extend.c fails)

||ramana at gcc dot gnu.org

[Bug target/64172] [4.9/5 Regression] Wrong code with GCC vector extensions on ARM when compiled without NEON

, |arm-none-eabi |arm-none-eabi,arm-none-linu ||x-gnueabihf CC||ramana at gcc dot gnu.org, ||vmakarov at gcc dot gnu.org --- Comment #12

[Bug target/63234] arm used label is removed

-15 00:00:00 |2015-01-15 CC||ramana at gcc dot gnu.org Known to work||5.0 Ever confirmed|0 |1 Known to fail||4.9.2 --- Comment #6 from Ramana

[Bug target/62287] gcc generates near call for extern weak function

||ramana at gcc dot gnu.org Resolution|--- |INVALID --- Comment #1 from Ramana Radhakrishnan --- If you use -mlong-calls in these particular cases, you should be able to work around the problem. The documentation for this feature states the

[Bug target/61578] [4.9/ 5 regression] Code size increase for ARM thumb compared to 4.8.x when compiling with -Os

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61578 Ramana Radhakrishnan changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug bootstrap/59902] Cilk gcc bootstrap for arm target on x86 host

|UNCONFIRMED |SUSPENDED Last reconfirmed||2015-01-15 CC||ramana at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #1 from Ramana Radhakrishnan --- Cilkplus isn't supported o

[Bug target/27759] ICE using -mfloat-abi=softfp -mfpu=vfp -O1

||ramana at gcc dot gnu.org Resolution|--- |WONTFIX --- Comment #1 from Ramana Radhakrishnan --- This bug can't be fixed as this refers to the old pre-ABI linux target. Wont fix.

[Bug target/64600] [5.0 regression] arm-rtems ICE on valid code (-mcpu=xscale)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64600 Ramana Radhakrishnan changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug target/64310] libgcc2.c:2051:1: internal compiler error: in curr_insn_transform, at lra-constraints.c:3383

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64310 Ramana Radhakrishnan changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/64179] fail caused by autovectorization in arm big-endian mode

||2015-01-15 CC||ramana at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #1 from Ramana Radhakrishnan --- Fix is not to disable vectorization in big endian but essentially correct the backend and the

[Bug target/64179] fail caused by autovectorization in arm big-endian mode

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64179 Ramana Radhakrishnan changed: What|Removed |Added Priority|P3 |P4

[Bug bootstrap/64102] ARM bootstrap fails with segfault with -mapcs in BOOT_CFLAGS

|UNCONFIRMED |NEW Last reconfirmed||2015-01-15 CC||ramana at gcc dot gnu.org Ever confirmed|0 |1

[Bug target/63808] [arm] Extra register saving in FIQ handler

Target|ARMv4 |arm Status|UNCONFIRMED |NEW Last reconfirmed||2015-01-15 CC||ramana at gcc dot gnu.org Ever confirmed|0 |1

[Bug rtl-optimization/11222] arm/thumb __Unwind_SjLj_Register prologue optimization causes crash on interrupts

||ramana at gcc dot gnu.org Resolution|--- |WONTFIX --- Comment #11 from Ramana Radhakrishnan --- This is almost gone now. I can't reproduce it with trunk probably because arm-elf is now dead and long gone, as everything is now EABI centric.

[Bug target/64600] [5.0 regression] arm-rtems ICE on valid code (-mcpu=xscale)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64600 Ramana Radhakrishnan changed: What|Removed |Added Target Milestone|--- |5.0 Known to fail|

[Bug target/64606] multiple warnings in arm target code

||2015-01-16 CC||ramana at gcc dot gnu.org Ever confirmed|0 |1

[Bug target/64453] Live high register not saved in function prolog on ARM with -Os

||ramana at gcc dot gnu.org Resolution|--- |FIXED Target Milestone|--- |5.0 --- Comment #2 from Ramana Radhakrishnan --- Fixed presumably.

[Bug target/64516] arm: wrong unaligned load generated

||2015-01-16 CC||ramana at gcc dot gnu.org Ever confirmed|0 |1 Known to fail||4.9.0, 4.9.1, 4.9.2, 5.0 --- Comment #1 from Ramana Radhakrishnan --- Hmmm, I'm not su

[Bug target/64458] [ARM] Redundant ldr when accessing var inside and outside a loop

||2015-01-16 CC||ramana at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #1 from Ramana Radhakrishnan --- Huh, what arch options ? .arm .syntax divided .file"ldr.c"

[Bug libstdc++/55997] build of libstd3++ segfaults armv5tel.

||ramana at gcc dot gnu.org Resolution|--- |WONTFIX --- Comment #3 from Ramana Radhakrishnan --- There is very little here to help reproduce this issue especially as I see others building 4.8.x based compilers on gcc-testresults even today

[Bug tree-optimization/33651] Request warning on null pointer chk optimized after ptr deref

|UNCONFIRMED |NEW Last reconfirmed||2015-01-16 CC||ramana at gcc dot gnu.org Ever confirmed|0 |1

[Bug bootstrap/63771] internal compiler error: in lra_create_copy, at lra.c:1532

||ramana at gcc dot gnu.org Resolution|--- |DUPLICATE --- Comment #4 from Ramana Radhakrishnan --- Marking as duplicate in the absence of any other information. *** This bug has been marked as a duplicate of bug 63740 ***

[Bug bootstrap/63740] [4.9 Regression] GCC 4.9.2 bootstrap fails on ARM, haifa-sched.c:6507:1: internal compiler error: in lra_create

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63740 --- Comment #11 from Ramana Radhakrishnan --- *** Bug 63771 has been marked as a duplicate of this bug. ***

[Bug rtl-optimization/60162] [4.9/5 Regression][lra] mlra appears to be using the FP registers for integer values and then moving on to GPR registers.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=60162 Ramana Radhakrishnan changed: What|Removed |Added Status|WAITING |RESOLVED Resolution|---

[Bug middle-end/57748] [4.8 Regression] ICE when expanding assignment to unaligned zero-sized array

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=57748 --- Comment #57 from Ramana Radhakrishnan --- (In reply to Jakub Jelinek from comment #56) > GCC 4.8.4 has been released. If it's too late to backport this to 4.8 we might as well close this off targeting it for 4.9. Ramana

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