[Bug rtl-optimization/59535] [4.9 regression] -Os code size regressions for Thumb1/Thumb2 with LRA

||2013-12-19 CC||ramana at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #11 from Ramana Radhakrishnan --- (In reply to Vladimir Makarov from comment #9) > (In reply to Richard Earnshaw from comment

[Bug rtl-optimization/59535] [4.9 regression] -Os code size regressions for Thumb1/Thumb2 with LRA

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59535 --- Comment #12 from Ramana Radhakrishnan --- (In reply to Ramana Radhakrishnan from comment #11) > (In reply to Vladimir Makarov from comment #9) > > (In reply to Richard Earnshaw from comment #5) > > > I think major problem is in wrong alternat

[Bug bootstrap/51068] [4.7 Regression] ARM bootstrap failure due to ICE in rtl_verify_flow_info_1 at cfgrtl.c:2001

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51068 Ramana Radhakrishnan changed: What|Removed |Added CC||ramana at gcc dot gnu.org

[Bug rtl-optimization/51051] [4.7 Regression]: build fails on cris-elf building libstdc++-v3

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51051 Ramana Radhakrishnan changed: What|Removed |Added CC||michael.hope at linaro dot

[Bug bootstrap/51068] [4.7 Regression] ARM bootstrap failure due to ICE in rtl_verify_flow_info_1 at cfgrtl.c:2001

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51068 Ramana Radhakrishnan changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|

[Bug target/51122] ICE in change_address_1, at emit-rtl.c:2001

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51122 Ramana Radhakrishnan changed: What|Removed |Added CC||ramana at gcc dot gnu.org

[Bug target/51122] ICE in change_address_1, at emit-rtl.c:2001

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51122 Ramana Radhakrishnan changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug target/43999] Gcc (lib1funcs.asm) doesn't build on ARM/Thumb2

||ramana at gcc dot gnu.org Known to work||4.6.0, 4.7.0 Known to fail||4.5.0 --- Comment #10 from Ramana Radhakrishnan 2011-11-16 13:41:54 UTC --- (In reply to comment #8) > Correct patch (h

[Bug target/45102] mm/page-writeback.c:820: internal compiler error: Segmentation fault

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=45102 Ramana Radhakrishnan changed: What|Removed |Added CC||ramana at gcc dot gnu.org

[Bug c++/45012] Invalid ambiguity on partial class specialization matching

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=45012 Ramana Radhakrishnan changed: What|Removed |Added CC||ramana at gcc dot gnu.org

[Bug target/51381] Internal compiler error for arm target

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51381 Ramana Radhakrishnan changed: What|Removed |Added CC||ramana at gcc dot gnu.org

[Bug target/51509] Inefficient neon intrinsic code sequence

, ||arm-linux-gnueabi Status|UNCONFIRMED |NEW Keywords||missed-optimization Last reconfirmed||2011-12-12 CC||ramana at gcc

[Bug rtl-optimization/38644] [4.4/4.5/4.6 Regression] Optimization flag -O1 -fschedule-insns2 causes wrong code

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=38644 --- Comment #62 from Ramana Radhakrishnan 2012-01-09 16:55:24 UTC --- Author: ramana Date: Mon Jan 9 16:55:16 2012 New Revision: 183019 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=183019 Log: 2012-01-09 Ramana Radhakrishnan B

[Bug target/51797] Arm backend missed the mls related optimization

||missed-optimization Last reconfirmed||2012-01-11 CC||ramana at gcc dot gnu.org Ever Confirmed|0 |1 Severity|normal |enhancement

[Bug middle-end/51442] volatile bitfields broken on arm

||ramana at gcc dot gnu.org Resolution||FIXED Target Milestone|--- |4.6.3 --- Comment #5 from Ramana Radhakrishnan 2012-01-11 12:12:07 UTC --- This should now be fixed by the commit as indicated below

[Bug target/51381] Internal compiler error for arm target

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51381 Ramana Radhakrishnan changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|

[Bug tree-optimization/51799] [4.7 Regression] Compiler ICE in vect_is_simple_use_1

Status|UNCONFIRMED |NEW Last reconfirmed||2012-01-11 CC||ramana at gcc dot gnu.org Ever Confirmed|0 |1

[Bug target/51659] [4.7 regression] ICE in function output_move_double

||4.6.0 Keywords||ice-on-valid-code Last reconfirmed||2012-01-11 CC||ramana at gcc dot gnu.org Ever Confirmed|0 |1 Summary

[Bug target/51819] [4.7 Regression] Neon wrong code generation, Error: unsupported alignment for instruction -- `vst1.32 {d2[0]},[r0:64]'

||2012-01-11 CC||ramana at gcc dot gnu.org Ever Confirmed|0 |1 --- Comment #1 from Ramana Radhakrishnan 2012-01-11 14:51:37 UTC --- Completely untested but I think this is the correct fix for this

[Bug target/48308] [4.6/4.7 Regression] crosscompiling to arm fails with assembler: can't resolve '.LC4' {.rodata.str1.1 section} - '.LPIC4' {*UND* section}

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48308 --- Comment #18 from Ramana Radhakrishnan 2012-01-11 18:15:05 UTC --- (In reply to comment #14) > Note, can't be reproduced on the trunk, the strcmp isn't DCEd there, but guess > the problem is just latent there. > > It looks like a target bug t

[Bug target/48308] [4.6/4.7 Regression] crosscompiling to arm fails with assembler: can't resolve '.LC4' {.rodata.str1.1 section} - '.LPIC4' {*UND* section}

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48308 --- Comment #19 from Ramana Radhakrishnan 2012-01-13 09:07:48 UTC --- (In reply to comment #14) > Note, can't be reproduced on the trunk, the strcmp isn't DCEd there, but guess > the problem is just latent there. Latent still in trunk with the t

[Bug target/50313] ARM: PIC code references a non-existant label

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50313 Ramana Radhakrishnan changed: What|Removed |Added Status|RESOLVED|REOPENED Last reconfirmed|

[Bug target/50313] ARM: PIC code references a non-existant label

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50313 --- Comment #4 from Ramana Radhakrishnan 2012-01-13 12:06:33 UTC --- Created attachment 26314 --> http://gcc.gnu.org/bugzilla/attachment.cgi?id=26314 smaller testcase Better reduced testcase. Fails on trunk with -Os -fPIC -mcpu=arm9tdmi or -Os

[Bug target/51709] armv7 target is not using unaligned access to packed fields sometimes (halfwords, loads?)

Status|UNCONFIRMED |NEW Last reconfirmed||2012-01-13 CC||ramana at gcc dot gnu.org Version|4.6.1 |4.7.0 Ever Confirmed|0 |1 Severity

[Bug target/51876] New: [4.7 regression] Recent extra neon related testsuite regressions on arm-linux-gnueabi

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51876 Bug #: 51876 Summary: [4.7 regression] Recent extra neon related testsuite regressions on arm-linux-gnueabi Classification: Unclassified Product: gcc Version: unknown

[Bug target/51876] [4.7 regression] Recent extra neon related testsuite regressions on arm-linux-gnueabi

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51876 Ramana Radhakrishnan changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug target/51876] [4.7 regression] Recent extra neon related testsuite regressions on arm-linux-gnueabi

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51876 --- Comment #3 from Ramana Radhakrishnan 2012-01-17 13:48:12 UTC --- (In reply to comment #2) > Created attachment 26349 [details] > gcc47-pr51876.patch > > Untested fix (well, tested that the ICEs are gone on all these tests with a > cross). v

[Bug target/51178] FAIL: g++.dg/lookup/builtin5.C scan-assembler _ZSt5atanhd

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51178 Ramana Radhakrishnan changed: What|Removed |Added Target|arm-none-eabi |arm-none-eabi, |

[Bug target/51876] [4.7 regression] Recent extra neon related testsuite regressions on arm-linux-gnueabi

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51876 --- Comment #6 from Ramana Radhakrishnan 2012-01-19 15:40:58 UTC --- (In reply to comment #5) > I did, but I'm waiting for testing results from Ramana. Testresults look good. Yeah , ok. Ramana

[Bug target/51835] ARM EABI violation when passing arguments to helper floating functions like __aeabi_d2iz

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51835 Ramana Radhakrishnan changed: What|Removed |Added CC||ramana at gcc dot gnu.org

[Bug target/50313] ARM: PIC code references a non-existant label

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50313 --- Comment #5 from Ramana Radhakrishnan 2012-01-20 09:22:21 UTC --- Author: ramana Date: Fri Jan 20 09:22:14 2012 New Revision: 183328 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=183328 Log: Fix PR target/50313 Modified: trunk/

[Bug tree-optimization/51914] New: [4.7] All vect-intfloat-conversion tests fail for arm-linux-gnueabi

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51914 Bug #: 51914 Summary: [4.7] All vect-intfloat-conversion tests fail for arm-linux-gnueabi Classification: Unclassified Product: gcc Version: unknown Status: UNCONFIRM

[Bug tree-optimization/51914] [4.7] vect-intfloat-conversion4a/b tests fail for arm-linux-gnueabi

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51914 --- Comment #1 from Ramana Radhakrishnan 2012-01-20 09:50:52 UTC --- arch specific command line options used: -mcpu=cortex-a9 -mfpu=neon -mfloat-abi=softfp

[Bug target/51819] [4.7 Regression] Neon wrong code generation, Error: unsupported alignment for instruction -- `vst1.32 {d2[0]},[r0:64]'

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51819 Ramana Radhakrishnan changed: What|Removed |Added Status|NEW |ASSIGNED

[Bug target/51819] [4.7 Regression] Neon wrong code generation, Error: unsupported alignment for instruction -- `vst1.32 {d2[0]},[r0:64]'

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51819 --- Comment #4 from Ramana Radhakrishnan 2012-01-20 13:24:53 UTC --- Author: ramana Date: Fri Jan 20 13:24:47 2012 New Revision: 183338 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=183338 Log: Fix PR target/51819 Modified: trunk

[Bug target/51819] [4.7 Regression] Neon wrong code generation, Error: unsupported alignment for instruction -- `vst1.32 {d2[0]},[r0:64]'

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51819 Ramana Radhakrishnan changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|

[Bug target/51882] ICE: in extract_insn, at recog.c:2109 (unrecognizable insn) when building Mesa on ARM

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51882 --- Comment #1 from Ramana Radhakrishnan 2012-01-21 12:29:02 UTC --- Created attachment 26403 --> http://gcc.gnu.org/bugzilla/attachment.cgi?id=26403 reduced testcase Reduced testcase. Configured with : --target=arm-linux-gnueabi --with-c

[Bug target/51882] ICE: in extract_insn, at recog.c:2109 (unrecognizable insn) when building Mesa on ARM

||2012-01-21 CC||ramana at gcc dot gnu.org Ever Confirmed|0 |1

[Bug lto/51642] Weak variable reference triggers ICE with -flto option

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51642 Ramana Radhakrishnan changed: What|Removed |Added CC||ramana at gcc dot gnu.org

[Bug middle-end/45416] [4.5/4.6 Regression] Code size regression from 4.4 for ARM

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=45416 --- Comment #16 from Ramana Radhakrishnan 2012-01-23 17:59:56 UTC --- Author: ramana Date: Mon Jan 23 17:59:51 2012 New Revision: 183446 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=183446 Log: 2012-01-23 Ramana Radhakrishnan

[Bug target/48308] [4.6/4.7 Regression] crosscompiling to arm fails with assembler: can't resolve '.LC4' {.rodata.str1.1 section} - '.LPIC4' {*UND* section}

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48308 --- Comment #20 from Ramana Radhakrishnan 2012-01-25 08:52:43 UTC --- Author: ramana Date: Wed Jan 25 08:52:39 2012 New Revision: 183512 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=183512 Log: 2012-01-25 Ramana Radhakrishnan P

[Bug bootstrap/51985] [4.7 Regression] Bootstrap failure due to revision 183457

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51985 Ramana Radhakrishnan changed: What|Removed |Added CC||ramana at gcc dot gnu.org

[Bug target/51980] ARM - Neon code polluted by useless stores to the stack with vuzpq / vzipq / vtrnq

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51980 Ramana Radhakrishnan changed: What|Removed |Added Keywords||missed-optimization Ta

[Bug target/48941] [arm gcc] NEON: Stack pointer operations performed even tho stack is not accessed at all in function.

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48941 --- Comment #9 from Ramana Radhakrishnan 2012-01-27 16:20:07 UTC --- (In reply to comment #8) > Any chance of seeing the work on this restart ? > > I found this bug while looking for something that would help (I raised bug > 51980 for the same k

[Bug target/50313] ARM: PIC code references a non-existant label

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50313 --- Comment #6 from Ramana Radhakrishnan 2012-01-30 14:35:10 UTC --- Author: ramana Date: Mon Jan 30 14:35:05 2012 New Revision: 183727 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=183727 Log: Fix PR target/50313 2012-01-30 Ramana R

[Bug target/50313] ARM: PIC code references a non-existant label

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50313 Ramana Radhakrishnan changed: What|Removed |Added Status|REOPENED|RESOLVED Resolution|

[Bug target/88013] can't vectorize rgb to grayscale conversion code

||2018-12-14 CC||ramana at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #8 from Ramana Radhakrishnan --- > vshr.u16q9, q9, #8 > vshr.u16q8, q8, #8 >

[Bug rtl-optimization/87871] [9 Regression] testcases fail after r265398 on arm

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87871 Ramana Radhakrishnan changed: What|Removed |Added CC||ramana at gcc dot gnu.org

[Bug rtl-optimization/87871] [9 Regression] testcases fail after r265398 on arm

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87871 Ramana Radhakrishnan changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug target/88510] GCC generates inefficient U64x2/v2di scalar multiply for NEON32

|UNCONFIRMED |NEW Last reconfirmed||2019-01-14 CC||ramana at gcc dot gnu.org Target Milestone|--- |10.0 Ever confirmed|0 |1 --- Comment #3 from Ramana

[Bug target/88734] [8 Regression] AArch64's ACLE intrinsics give an ICE instead of compile error when option mismatch.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88734 Ramana Radhakrishnan changed: What|Removed |Added CC||ramana at gcc dot gnu.org

[Bug target/84923] [8 regression] gcc.dg/attr-weakref-1.c failed on aarch64

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84923 Ramana Radhakrishnan changed: What|Removed |Added Status|RESOLVED|NEW Resolution|FIXED

[Bug target/89093] [9 Regression] C++ exception handling clobbers d8 VFP register

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89093 Ramana Radhakrishnan changed: What|Removed |Added CC||ramana at gcc dot gnu.org

[Bug target/89093] [9 Regression] C++ exception handling clobbers d8 VFP register

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89093 --- Comment #10 from Ramana Radhakrishnan --- Created attachment 45547 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=45547&action=edit untested prototype patch. Not sure if this is complete yet but it gives a framework to dig further.

[Bug target/89093] [9 Regression] C++ exception handling clobbers d8 VFP register

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89093 Ramana Radhakrishnan changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug target/89093] [9 Regression] C++ exception handling clobbers d8 VFP register

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89093 Ramana Radhakrishnan changed: What|Removed |Added Attachment #45547|0 |1 is obsolete|

[Bug target/89093] [9 Regression] C++ exception handling clobbers d8 VFP register

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89093 --- Comment #16 from Ramana Radhakrishnan --- (In reply to Jakub Jelinek from comment #14) > We require GNU make, so one can use something like: > unwind-arm.o unwind-c.o libunwind.o pr-support.o: CFLAGS += -mfpu=none > or similar in libgcc/confi

[Bug target/89093] [9 Regression] C++ exception handling clobbers d8 VFP register

|unassigned at gcc dot gnu.org |ramana at gcc dot gnu.org --- Comment #21 from Ramana Radhakrishnan --- (In reply to Jakub Jelinek from comment #19) > (In reply to Florian Weimer from comment #18) > > (In reply to Ramana Radhakrishnan from comment #15) > > > Testing this and wou

[Bug target/89093] [9 Regression] C++ exception handling clobbers d8 VFP register

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89093 --- Comment #27 from Ramana Radhakrishnan --- (In reply to Bernd Edlinger from comment #25) > you might consider adding something like that to your patch: > > Index: elf.h > === > -

[Bug target/85203] cmse_nonsecure_caller intrinsic returns incorrect results

||ramana at gcc dot gnu.org Resolution|--- |FIXED Target Milestone|--- |7.4 --- Comment #4 from Ramana Radhakrishnan --- Fixed I'm assuming ?

[Bug ada/85380] gnatbind fails with small executable & restricted runtime

, ||ramana at gcc dot gnu.org --- Comment #1 from Ramana Radhakrishnan --- Adding Eric to the CC list as someone who could comment on this ?

[Bug target/68256] Defining TARGET_USE_CONSTANT_BLOCKS_P causes go bootstrap failure on aarch64.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68256 --- Comment #12 from Ramana Radhakrishnan --- (In reply to Steve Ellcey from comment #11) > FYI: This caused a regression on aarch64. > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84923 I have marked 84923 as an 8 regression as it wasn't do

[Bug target/84923] [8/9 regression] gcc.dg/attr-weakref-1.c failed on aarch64

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84923 --- Comment #4 from Ramana Radhakrishnan --- (In reply to Richard Biener from comment #3) > For x86_64 if I append > > const int *dat[] = { &Wv12, &wv12 }; > > the testcase links fine irrespective of where I place the > > .weakref

[Bug target/85593] GCC on ARM allocates R3 for local variable when calling naked function with O2 optimizations enabled

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85593 Ramana Radhakrishnan changed: What|Removed |Added CC||ramana at gcc dot gnu.org

[Bug target/85593] [5,6,7,8 Regression] GCC on ARM allocates R3 for local variable when calling naked function with O2 optimizations enabled

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85593 Ramana Radhakrishnan changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug target/85733] [8 regression] ARM -mbe8 behaviour doesn't match documentation

||2018-05-11 CC||ramana at gcc dot gnu.org Target Milestone|--- |8.2 Summary|ARM -mbe8 behaviour doesn't |[8 regression] ARM -mbe8 |match documentation |behaviour do

[Bug target/85733] [8 regression] ARM -mbe8 behaviour doesn't match documentation

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85733 Ramana Radhakrishnan changed: What|Removed |Added Status|NEW |ASSIGNED Assignee|unass

[Bug debug/84342] Location views breaks cross builds of arm including gnueabihf

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84342 Ramana Radhakrishnan changed: What|Removed |Added CC||ramana at gcc dot gnu.org

[Bug debug/84342] Location views breaks cross builds of arm including gnueabihf

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84342 --- Comment #13 from Ramana Radhakrishnan --- (In reply to Jeffrey A. Law from comment #12) > I'm not familiar enough with the ccfsm bits to know if there's something we > ought to be doing generically to improve CC handling further. I think > d

[Bug tree-optimization/85804] [8/9 Regression][AArch64] Mis-compilation of loop with strided array access and xor reduction

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85804 Ramana Radhakrishnan changed: What|Removed |Added CC||ramana at gcc dot gnu.org

[Bug tree-optimization/64946] [AArch64] gcc.target/aarch64/vect-abs-compile.c - "abs" vectorization fails for char/short types

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64946 --- Comment #25 from Ramana Radhakrishnan --- (In reply to kugan from comment #24) > Author: kugan > Date: Sat Jun 16 21:34:29 2018 > New Revision: 261681 > > URL: https://gcc.gnu.org/viewcvs?rev=261681&root=gcc&view=rev > Log: > gcc/ChangeLog:

[Bug tree-optimization/64946] [AArch64] gcc.target/aarch64/vect-abs-compile.c - "abs" vectorization fails for char/short types

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64946 Ramana Radhakrishnan changed: What|Removed |Added Target Milestone|--- |9.0

[Bug target/86209] Peephole does not happen because the type of zero/sign extended operands is not the same.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86209 Ramana Radhakrishnan changed: What|Removed |Added CC||ramana at gcc dot gnu.org

[Bug target/86209] Peephole does not happen because the type of zero/sign extended operands is not the same.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86209 --- Comment #3 from Ramana Radhakrishnan --- (In reply to sameerad from comment #2) > Ramana, it is another peephole that I am trying to explore for falkor. It > combines loads/stores of shorter types (QI/HI/SI) into single load/store of > larger

[Bug middle-end/83623] [8 Regression] ICE: in convert_move, at expr.c:248 with -march=knl and 16bit vector bswap/rotate

||ramana at gcc dot gnu.org Resolution|FIXED |--- --- Comment #8 from Ramana Radhakrishnan --- Seems to need a fix for gcc 6 branch based on PR86166

[Bug ipa/83178] [8 regression] g++.dg/ipa/devirt-22.C fail

Status|UNCONFIRMED |NEW Last reconfirmed||2017-12-12 CC||ramana at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #3 from Ramana Radhakrishnan --- Confirmed then.

[Bug target/89093] [9 Regression] C++ exception handling clobbers d8 VFP register

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89093 --- Comment #30 from Ramana Radhakrishnan --- (In reply to Jakub Jelinek from comment #29) > Ramana, any progress on this? I'm still trying to get the various spec files and the t-multilib bits sorted and half-term has intervened here in the UK.

[Bug target/89093] [9 Regression] C++ exception handling clobbers d8 VFP register

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89093 Ramana Radhakrishnan changed: What|Removed |Added Attachment #45552|0 |1 is obsolete|

[Bug target/89093] [9 Regression] C++ exception handling clobbers d8 VFP register

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89093 --- Comment #45 from Ramana Radhakrishnan --- (In reply to Jakub Jelinek from comment #42) > Thanks for the explanation. > In that case, I think it would be better to just add > __attribute__((target("general-regs-only"))) > to the > #ifdef __AR

[Bug middle-end/90075] [7/8 Regression] [AArch64] ICE during RTL pass when member of union passed to copysignf

||ramana at gcc dot gnu.org Assignee|unassigned at gcc dot gnu.org |ramana at gcc dot gnu.org --- Comment #2 from Ramana Radhakrishnan --- I'll take a look.

[Bug middle-end/90075] [7/8 Regression] [AArch64] ICE during RTL pass when member of union passed to copysignf

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90075 Ramana Radhakrishnan changed: What|Removed |Added CC||rearnsha at gcc dot gnu.org --- C

[Bug target/86538] GCC should define a macro to specify if LSE is enabled or not

||2019-04-30 CC||ramana at gcc dot gnu.org Resolution|WONTFIX |--- Assignee|unassigned at gcc dot gnu.org |ramana at gcc dot gnu.org Target Milestone|--- |7.5

[Bug target/86538] GCC should define a macro to specify if LSE is enabled or not

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86538 --- Comment #4 from Ramana Radhakrishnan --- Author: ramana Date: Tue Apr 30 11:22:11 2019 New Revision: 270686 URL: https://gcc.gnu.org/viewcvs?rev=270686&root=gcc&view=rev Log: [Patch AArch64] Add __ARM_FEATURE_ATOMICS This keeps coming up r

[Bug target/86538] GCC should define a macro to specify if LSE is enabled or not

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86538 --- Comment #5 from Ramana Radhakrishnan --- Author: ramana Date: Tue Apr 30 12:02:30 2019 New Revision: 270689 URL: https://gcc.gnu.org/viewcvs?rev=270689&root=gcc&view=rev Log: [Patch AArch64] Add __ARM_FEATURE_ATOMICS This keeps coming u

[Bug target/86538] GCC should define a macro to specify if LSE is enabled or not

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86538 --- Comment #6 from Ramana Radhakrishnan --- Author: ramana Date: Tue Apr 30 14:57:50 2019 New Revision: 270702 URL: https://gcc.gnu.org/viewcvs?rev=270702&root=gcc&view=rev Log: [Patch AArch64] Add __ARM_FEATURE_ATOMICS This keeps coming up

[Bug target/86538] GCC should define a macro to specify if LSE is enabled or not

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86538 --- Comment #7 from Ramana Radhakrishnan --- Author: ramana Date: Wed May 1 15:27:40 2019 New Revision: 270770 URL: https://gcc.gnu.org/viewcvs?rev=270770&root=gcc&view=rev Log: [Patch AArch64] Add __ARM_FEATURE_ATOMICS This keeps coming up

[Bug target/86538] GCC should define a macro to specify if LSE is enabled or not

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86538 Ramana Radhakrishnan changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/90308] ICE in output_operand: invalid %-code

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90308 Ramana Radhakrishnan changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/89400] [7/8/9/10 Regression] ICE: output_operand: invalid %-code with -march=armv6kz -mthumb -munaligned-access

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89400 Ramana Radhakrishnan changed: What|Removed |Added CC||marxin at gcc dot gnu.org --- Com

[Bug tree-optimization/88709] Improve store-merging

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88709 Ramana Radhakrishnan changed: What|Removed |Added CC||ramana at gcc dot gnu.org

[Bug libgcc/85967] [ARM] No unwinding support for division functions

||2018-07-11 CC||ramana at gcc dot gnu.org Assignee|unassigned at gcc dot gnu.org |ramana at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #3 from Ramana Radhakrishnan --- This patch

[Bug target/85910] config/aarch64/aarch64.c:15653:12: warning: duplicated ‘if’ condition

||2018-07-11 CC||ramana at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #1 from Ramana Radhakrishnan --- Confirmed.

[Bug target/86209] Peephole does not happen because the type of zero/sign extended operands is not the same.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86209 Ramana Radhakrishnan changed: What|Removed |Added Keywords||missed-optimization S

[Bug target/86209] Peephole does not happen because the type of zero/sign extended operands is not the same.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86209 --- Comment #13 from Ramana Radhakrishnan --- Sameera, If you are working on this , can you please assign this to yourself ? Ramana

[Bug target/85854] Performance regression from gcc 4.9.2

||2018-07-11 CC||ramana at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #1 from Ramana Radhakrishnan --- I'm unable to build the pre-processed file with 4.9 - is it possible for you to att

[Bug tree-optimization/85804] [8/9 Regression][AArch64] Mis-compilation of loop with strided array access and xor reduction

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85804 --- Comment #3 from Ramana Radhakrishnan --- (In reply to Ramana Radhakrishnan from comment #2) > Patch being discussed here. > https://gcc.gnu.org/ml/gcc-patches/2018-05/msg01026.html Bin are you still working on this ?

[Bug tree-optimization/80641] missed optimization with with std::vector resize in loop

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80641 --- Comment #12 from Ramana Radhakrishnan --- (In reply to Martin Sebor from comment #11) > *** Bug 86516 has been marked as a duplicate of this bug. *** (In reply to Paul Gotch from comment #10) > I'm afraid the changes made to libstdc++ have o

[Bug tree-optimization/80641] missed optimization with with std::vector resize in loop

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80641 Ramana Radhakrishnan changed: What|Removed |Added Known to work||6.4.1, 8.1.0 Known to fail|

[Bug tree-optimization/80641] missed optimization with with std::vector resize in loop

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80641 Ramana Radhakrishnan changed: What|Removed |Added Known to fail||7.3.1 --- Comment #14 from Ramana

[Bug target/86555] unaligned address for ldrd/strd on armv5e

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86555 --- Comment #4 from Ramana Radhakrishnan --- (In reply to Khem Raj from comment #2) > we can avoid the problem by altering the structure, thats not an issue, but > do you think compiler is right here by assuming to generate LDRD on a 4byte > ali

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