[Bug target/118601] [15] RISC-V: unrecognizable insn ICE in xtheadvector/pr114194.c on 32bit targets

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118601 Jin Ma changed: What|Removed |Added Last reconfirmed||2025-02-07 Status|UNCONFIRMED

[Bug target/118872] New: RISCV: internal compiler error: in emit_move_insn, at expr.cc:4636 for rvv

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118872 Bug ID: 118872 Summary: RISCV: internal compiler error: in emit_move_insn, at expr.cc:4636 for rvv Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: nor

[Bug target/116594] [meta-bug] xtheadvector brokeness

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116594 --- Comment #4 from Jin Ma --- Hi, if there are no other related issues, I will close this in a day. :) Best regards, Jin Ma

[Bug target/118901] New: RISC-V: bfloat16-complex.c:(.text.startup+0x5f6): undefined reference to `__divbc3' when zfh or zvfh

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118901 Bug ID: 118901 Summary: RISC-V: bfloat16-complex.c:(.text.startup+0x5f6): undefined reference to `__divbc3' when zfh or zvfh Product: gcc Version: 15.0 Status: UNCONFIRM

[Bug target/118601] [15] RISC-V: unrecognizable insn ICE in xtheadvector/pr114194.c on 32bit targets

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118601 Jin Ma changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/118872] RISCV: internal compiler error: in emit_move_insn, at expr.cc:4636 for rvv

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118872 Jin Ma changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/116594] [meta-bug] xtheadvector brokeness

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116594 --- Comment #3 from Jin Ma --- (In reply to Andrew Pinski from comment #1) > All known brokeness of xtheadvector . Hi, I conducted regression testing on XTheadVector and compared it with rv64gcv_zvfh. The results indicate that XTheadVector has

[Bug target/116594] [meta-bug] xtheadvector brokeness

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116594 Jin Ma changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/118872] RISCV: internal compiler error: in emit_move_insn, at expr.cc:4636 for rvv

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118872 Jin Ma changed: What|Removed |Added Ever confirmed|0 |1 Last reconfirmed|

[Bug target/119007] RISC-V: The optimization ignored the side effects of the rounding mode, resulting in incorrect results for rvv

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119007 Jin Ma changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |majin at gcc dot gnu.org Ta

[Bug target/119007] New: RISC-V: The optimization ignored the side effects of the rounding mode, resulting in incorrect results for rvv

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119007 Bug ID: 119007 Summary: RISC-V: The optimization ignored the side effects of the rounding mode, resulting in incorrect results for rvv Product: gcc Version: 15.0

[Bug target/119007] RISC-V: The optimization ignored the side effects of the rounding mode, resulting in incorrect results for rvv

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119007 --- Comment #2 from Jin Ma --- (In reply to Jeffrey A. Law from comment #1) > I think when we discussed his several weeks ago the conclusion was this was > a problem in the intrinsics space. > > Essentially the intrinsics can modify FRM and whe

[Bug target/120642] ICE: in validate_change_or_fail, at config/riscv/riscv-v.cc:5705 with -O -mcpu=xt-c920 -mrvv-vector-bits=zvl

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120642 --- Comment #2 from Jin Ma --- > Which doesn't match because the vector_length_operand predicate rejects > nonzero constants for XTHEADVECTOR. > > I think the right fix here is to just guard the transformation in AVL > propagation like this: >