[Bug rtl-optimization/116244] [15 Regression] reload ICE building libstdc++ for coldfire

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116244 Jeffrey A. Law changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug rtl-optimization/115876] [15 regression] ext-dce.cc has ubsan issues; shifting negative values

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115876 --- Comment #15 from Jeffrey A. Law --- It's on my list, just higher priority items to deal with right now.

[Bug target/116282] [15 Regression] RISC-V rv64id_zba_zbkb ICE: could not split insn

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116282 --- Comment #3 from Jeffrey A. Law --- So yes, this is a problem with the const costing giving two different answers at different times. That in turn causes the relevant pattern to match at one point and fail to match at another. It's a bit of

[Bug rtl-optimization/116244] [15 Regression] reload ICE building libstdc++ for coldfire

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116244 Jeffrey A. Law changed: What|Removed |Added Resolution|FIXED |--- Status|RESOLVED

[Bug target/113035] RISC-V: regression testsuite errors -mtune=sifive-7-series

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113035 --- Comment #4 from Jeffrey A. Law --- Thanks! It actually looks like there's two vsetvls in both output files. But in the case of the sifive-7 tuning, the two vsetvls set different vector configurations. for sifive-7 we have these: vsetvli

[Bug rtl-optimization/116389] [avr][15 regression] ICE in extract_constrain_insn for avrtiny and -O2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116389 --- Comment #2 from Jeffrey A. Law --- Yes, a paradoxical is precisely what we expect and want here. This sounds like either a reload bug (definitely possible, I'm still chasing one of these over on the m68k) or a backend bug with avr.

[Bug target/116280] [15 Regression] RISC-V: expected mode RVVMF8QI for operand 2 of insn pred_vwsllrvvmf4hi but got mode RVVMF2SI

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116280 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/116282] [15 Regression] RISC-V rv64id_zba_zbkb ICE: could not split insn

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116282 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/116390] [15 regression] [avr] Another ICE for avrtiny and optimization

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116390 --- Comment #7 from Jeffrey A. Law --- WRT the question in c#1. A paradoxical subreg is the canonical way to say I want to view this pseudo (or expression) in a mode wider than its native mode and I don't care about the state of the bits outsid

[Bug rtl-optimization/116389] [avr][15 regression] ICE in extract_constrain_insn for avrtiny and -O2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116389 --- Comment #4 from Jeffrey A. Law --- I'm pretty confident IRA knows the basics of paradoxicals. The concept of paradoxicals has been around since the gcc-1 era and Vlad is well aware of how paradoxicals work. So while there may be a bug, I d

[Bug rtl-optimization/116389] [avr][15 regression] ICE in extract_constrain_insn for avrtiny and -O2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116389 --- Comment #6 from Jeffrey A. Law --- Sorry should have written "is _not_ a reasonable assessment" in my prior message. RA does assess validity and there's nothing special about avr here and paradoxicals, unless the backend is doing something

[Bug rtl-optimization/115876] [15 regression] ext-dce.cc has ubsan issues; shifting negative values

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115876 --- Comment #16 from Jeffrey A. Law --- At least part of these are coming from the use-side processing of TImode operations in carry_backpropagate. The right thing to do in that case is just return the mode mask indicating all the chunks are po

[Bug rtl-optimization/115876] [15 regression] ext-dce.cc has ubsan issues; shifting negative values

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115876 --- Comment #17 from Jeffrey A. Law --- And the other case is (subreg:SI (reg:TF) 12). No great surprise that the bit position is problematical for that. Should be an easy fix.

[Bug other/63426] [meta-bug] Issues found with -fsanitize=undefined

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63426 Bug 63426 depends on bug 115876, which changed state. Bug 115876 Summary: [15 regression] ext-dce.cc has ubsan issues; shifting negative values https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115876 What|Removed |

[Bug rtl-optimization/115876] [15 regression] ext-dce.cc has ubsan issues; shifting negative values

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115876 Jeffrey A. Law changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug tree-optimization/116409] New: [15 Regression] Recent phiopt change causing ICE on riscv64

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116409 Bug ID: 116409 Summary: [15 Regression] Recent phiopt change causing ICE on riscv64 Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal P

[Bug rtl-optimization/115876] [15 regression] ext-dce.cc has ubsan issues; shifting negative values

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115876 --- Comment #21 from Jeffrey A. Law --- Just sorry it took so long

[Bug rtl-optimization/116437] [15 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1934 with -O2 -march=emeraldrapids -fno-split-wide-types -m32

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116437 Jeffrey A. Law changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |law at gcc dot gnu.org --- Comm

[Bug rtl-optimization/116437] [15 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1934 with -O2 -march=emeraldrapids -fno-split-wide-types -m32

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116437 Jeffrey A. Law changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug rtl-optimization/116420] [15 Regression] wrong code at -O{2,3} with "-fno-forward-propagate -fno-tree-ch" on x86_64-linux-gnu

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116420 Jeffrey A. Law changed: What|Removed |Added Status|NEW |ASSIGNED Assignee|unassigned

[Bug rtl-optimization/116420] [15 Regression] wrong code at -O{2,3} with "-fno-forward-propagate -fno-tree-ch" on x86_64-linux-gnu

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116420 --- Comment #3 from Jeffrey A. Law --- Fun. The DF framework provides us a way to run dataflow problems on sub-graphs. Naturally a bitmap of interesting blocks is passed into those routines. At a confluence point, the DF framework will not m

[Bug rtl-optimization/116420] [15 Regression] wrong code at -O{2,3} with "-fno-forward-propagate -fno-tree-ch" on x86_64-linux-gnu

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116420 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug debug/116470] [15 regression] Enabling -gvariable-location-views breaks Solaris/x86 bootstrap

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116470 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org --- Comment #8

[Bug target/116466] The standard instruction pattern of RISC-V addv has generated an unnecessary instruction.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116466 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org --- Comment #1

[Bug target/116466] The standard instruction pattern of RISC-V addv has generated an unnecessary instruction.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116466 --- Comment #2 from Jeffrey A. Law --- Looking at this, I would fully expect that in an optimizing compilation that the redundant extension would be eliminated. Are you seeing the redundant sign extensions in the final assembly output or just

[Bug target/116466] The standard instruction pattern of RISC-V addv has generated an unnecessary instruction.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116466 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/116466] The standard instruction pattern of RISC-V addv has generated an unnecessary instruction.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116466 --- Comment #6 from Jeffrey A. Law --- Created attachment 59003 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=59003&action=edit Hack from the RAU team Attached is the hack from the RAU team. It was initially used to help identify cases

[Bug rtl-optimization/116488] [15 Regression] wrong code at -O{s,2,3} with "-fno-forward-propagate" on x86_64-linux-gnu

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116488 Jeffrey A. Law changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |law at gcc dot gnu.org

[Bug target/113939] Switch m68k to LRA

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113939 --- Comment #2 from Jeffrey A. Law --- Andreas, do you think the m68k port is ready to try bootstrapping with LRA enabled by default? It'd be relatively simple to flip it in my tester.

[Bug target/113939] Switch m68k to LRA

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113939 --- Comment #4 from Jeffrey A. Law --- Spinning. Should have some results tomorrow.

[Bug target/116131] [14/15 Regression] RISC-V: Unrecognizable insn with xtheadmemidx on rv32

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116131 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/116504] wrong code with -mcpu=sifive-x280

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116504 --- Comment #4 from Jeffrey A. Law --- It's not failing for me, either when using QEMU or when running the resultant binary on the BPI. Zdenek, can you (privately) pass along the resulting binary you're testing. It's pretty easy for me to run

[Bug target/116152] RISC-V: Proposed deprecation of LP64E abi

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116152 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/115142] [14 Regression] Unrecognizable insn in extract_insn, at recog.cc:2812 with -ftree-ter

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115142 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug target/113941] Switch mn10300 to LRA

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113941 --- Comment #1 from Jeffrey A. Law --- Not really working on this and I'm not going to lose sleep if this port is deprecated. But in case someone does care, here's a couple hints. First the mn103 port will trip an internal consistency check in

[Bug target/116256] [15 Regression] RISC-V: testsuite failures since late-combine-pass

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116256 Jeffrey A. Law changed: What|Removed |Added Ever confirmed|0 |1 Status|UNCONFIRMED

[Bug target/116278] [15] RISC-V: Miscompile at -O2 -fwrapv -fno-strict-aliasing

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116278 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED CC|

[Bug rtl-optimization/116544] [15] RISC-V: Miscompile at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116544 Jeffrey A. Law changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/115921] Missed optimization: and->ashift might be cheaper than ashift->and on typical RISC targets

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115921 --- Comment #3 from Jeffrey A. Law --- IIRC, the reason for that condition to to avoid spoiling certain cases where we want to ultimately generate shNadd instructions. It's a tradeoff. The shadd case is probably more important than avoiding th

[Bug rtl-optimization/108039] Unnecessary extension storing same value twice to small location

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108039 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug tree-optimization/116573] New: [15 Regression] Recent SLP work appears to generate significantly worse code on RISC-V

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116573 Bug ID: 116573 Summary: [15 Regression] Recent SLP work appears to generate significantly worse code on RISC-V Product: gcc Version: 15.0 Status: UNCONFIRMED S

[Bug target/111372] libgcc: RISCV C++ exception handling stack usage grew in 13.1

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111372 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org Resolut

[Bug target/111020] RFE: RISC-V: ability to cherry-pick additional instructions

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111020 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org Sta

[Bug target/110632] RISC-V: SLP optimisation

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110632 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org Resolut

[Bug target/109989] [13 Regression] RISC-V: Missing sign extension with int to float conversion with 64bit soft floats caused by r13-2105

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109989 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug target/113939] Switch m68k to LRA

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113939 --- Comment #5 from Jeffrey A. Law --- So the m68k bootstrap with LRA enabled blows up. It looks like the stage1 compiler is mis-compiling the stage2 compiler. The result is a metric ton of errors building the stage2 libgcc. A .o bisection la

[Bug rtl-optimization/116488] [15 Regression] wrong code at -O{s,2,3} with "-fno-forward-propagate" on x86_64-linux-gnu

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116488 --- Comment #3 from Jeffrey A. Law --- *** Bug 116579 has been marked as a duplicate of this bug. ***

[Bug tree-optimization/116579] [15 Regression] wrong code at -O{2, 3} with "-fno-thread-jumps" on x86_64-linux-gnu since r15-1901 (ext-dce)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116579 Jeffrey A. Law changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/116615] New: Investigate LOGICAL_OP_NON_SHORT_CIRCUIT for RISC-V

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116615 Bug ID: 116615 Summary: Investigate LOGICAL_OP_NON_SHORT_CIRCUIT for RISC-V Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Priority: P3 Compone

[Bug target/116662] The value of __GCC_DESTRUCTIVE_SIZE for riscv64 could be improved

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116662 --- Comment #9 from Jeffrey A. Law --- So the question in my mind, how important is this? On modern kernels & toolchains it's possible to query the cboz extension & its block size which effectively gives you the size of a cache line. But not e

[Bug middle-end/108892] [13 Regression] unable to generate reloads for at -Og on riscv64 since r13-4907

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108892 --- Comment #5 from Jeffrey A. Law --- Right. The fix is a 1-liner. I had it going through a test on x86 and riscv and lost power. Finally got it re-spun and just need to look at the results.

[Bug target/109040] [13 Regression] wrong code with v16hi compare & mask on riscv64 at -O2 since r13-4907-g2e886eef7f2b5a

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109040 Jeffrey A. Law changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/108947] [13 Regression] wrong code with -O2 -fno-forward-propagate and vector compare on riscv64

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108947 --- Comment #2 from Jeffrey A. Law --- *** Bug 109040 has been marked as a duplicate of this bug. ***

[Bug middle-end/108892] [13 Regression] unable to generate reloads for at -Og on riscv64 since r13-4907

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108892 Jeffrey A. Law changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/109402] v850: non-v850e version of __muldi3() in /libgcc/config/v850/lib1funcs.S operates sp in reversed direction

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109402 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org Resolut

[Bug tree-optimization/109434] [12/13 Regression] std::optional weird -Wmaybe-unitialized and behaviour with -O2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109434 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org Prior

[Bug c++/109381] [10/11/12/13 Regression] Ambiguous member lookup with this-> accepted when it should be rejected

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109381 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P2 CC|

[Bug target/109104] [13 Regression] ICE: in gen_reg_rtx, at emit-rtl.cc:1171 with -fzero-call-used-regs=all -march=rv64gv

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109104 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org Prior

[Bug target/108947] [13 Regression] wrong code with -O2 -fno-forward-propagate and vector compare on riscv64

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108947 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P1 --- Comment #4 from Jeffrey A. Law

[Bug libgomp/108895] [13.0.1 (exp)] Fortran + gfx90a !$acc update device produces a segfault.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108895 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P4 CC|

[Bug tree-optimization/108360] [13 Regression] Dead Code Elimination Regression at -Os since r13-2048-g418b71c0d535bf

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108360 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P2 CC|

[Bug tree-optimization/108358] [13 Regression] Dead Code Elimination Regression at -Os since r13-3378-gf6c168f8c06047

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108358 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org Prior

[Bug tree-optimization/108355] [13 Regression] Dead Code Elimination Regression at -O2 since r13-2772-g9baee6181b4e42

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108355 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org Prior

[Bug tree-optimization/108351] [13 Regression] Dead Code Elimination Regression at -O3 since r13-4240-gfeeb0d68f1c708

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108351 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P2 CC|

[Bug tree-optimization/108197] [12/13 Regression] -Wstringop-overread emitted on simple boost small_vector code

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108197 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org Prior

[Bug tree-optimization/107823] [13 Regression] Dead Code Elimination Regression at -Os (trunk vs. 12.2.0)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107823 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org Prior

[Bug target/107270] [10/11/12/13 Regression] return for structure is not as good as before

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107270 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org Prior

[Bug tree-optimization/106511] [13 Regression] New -Werror=maybe-uninitialized since r13-1268-g8c99e307b20c502e

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106511 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P2 CC|

[Bug target/106240] [13 Regression] missed vectorization opportunity (cond move) on mips since r13-707-g68e0063397ba82

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106240 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P2

[Bug tree-optimization/105834] [13 Regression] Dead Code Elimination Regression at -O2 (trunk vs. 12.1.0)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105834 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P2 CC|

[Bug tree-optimization/105832] [13 Regression] Dead Code Elimination Regression at -O3 (trunk vs. 12.1.0)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105832 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org Prior

[Bug rtl-optimization/105715] [13 Regression] missed RTL if-conversion with COND_EXPR change

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105715 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P2 CC|

[Bug c/105628] [12/13 Regression] False positive with -Waddress

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105628 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org Prior

[Bug middle-end/109478] FAIL: g++.dg/other/pr104989.C -std=gnu++14 (internal compiler error: Segmentation fault)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109478 --- Comment #2 from Jeffrey A. Law --- The pa.cc bits look reasonable. It's been forever since I looked at this code, but clearly using a HOST_WIDE_INT is the right thing to be doing. While it may not fix this bug completely, consider it pre-a

[Bug analyzer/109027] [13 Regression] ICE: SIGSEGV (infinite recursion in ana::constraint_manager::eval_condition / ana::constraint_manager::impossible_derived_conditions_p) with -fanalyzer since r13-

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109027 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P2 CC|

[Bug analyzer/107943] [11/12/13 Regression] gcc -fanalyzer hangs in openssl curve25519.c since r11-3840-gaf66094d03779377

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107943 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org Prior

[Bug rtl-optimization/103829] [10/11/12/13 Regression] missing shrink wrapping for simple/obvious code

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103829 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org Prior

[Bug middle-end/103637] [12/13 Regression] missing warning writing past the end of one of multiple elements of the same array

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103637 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P2 CC|

[Bug analyzer/103602] [11/12/13 regression] Analyzer takes excessive amount of memory and time linking GNU grep with LTO

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103602 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org Prior

[Bug target/109508] [13 Regression] ICE: in extract_insn, at recog.cc:2791 with -mcpu=sifive-s76 on riscv64

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109508 Jeffrey A. Law changed: What|Removed |Added Ever confirmed|0 |1 Last reconfirmed|

[Bug target/109508] [13 Regression] ICE: in extract_insn, at recog.cc:2791 with -mcpu=sifive-s76 on riscv64

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109508 Jeffrey A. Law changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |law at gcc dot gnu.org

[Bug target/108807] [11/12/13 regression] gcc.target/powerpc/vsx-builtin-10d.c fails after r11-6857-gb29225597584b6 on power 9 BE

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108807 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org --- Comment #5

[Bug target/108807] [11/12 regression] gcc.target/powerpc/vsx-builtin-10d.c fails after r11-6857-gb29225597584b6 on power 9 BE

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108807 --- Comment #7 from Jeffrey A. Law --- Once you've committed to the active release branches where this bug is active (11/12 in this case), you can just close the bug as resolved/fixed. No need to update the summary/title in that case. Thanks,

[Bug target/109508] [13 Regression] ICE: in extract_insn, at recog.cc:2791 with -mcpu=sifive-s76 on riscv64

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109508 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/109549] [14 Regression] cmov6.c test fail after commit r14-53-g675b1a7f113adb1d737adaf78b4fd90be7a0ed1a

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109549 --- Comment #4 from Jeffrey A. Law --- x86's tuning does have some support for avoiding multiple cmovs in a single if-converted sequence. I'll double check if that's kicking in here.

[Bug target/109549] [14 Regression] cmov6.c test fail after commit r14-53-g675b1a7f113adb1d737adaf78b4fd90be7a0ed1a

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109549 Jeffrey A. Law changed: What|Removed |Added Ever confirmed|0 |1 Status|UNCONFIRMED

[Bug target/109549] [14 Regression] cmov6.c test fail after commit r14-53-g675b1a7f113adb1d737adaf78b4fd90be7a0ed1a

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109549 --- Comment #6 from Jeffrey A. Law --- And just an FYI, the tester is flagging conditional move failures for mips64-* rx-elf and s390-linux-gnu. Most likely these are additional cases where the hook is indicating the transformation isn't profit

[Bug target/108248] Some insns in the risc-v backend do not have mappings to functional units

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108248 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/108247] Missed opportunity to generate shNadd on risc-v

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108247 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug tree-optimization/106888] [RISCV] Negative optimization that excess andi instructions are generated in gcc.dg/pr90838.c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106888 --- Comment #4 from Jeffrey A. Law --- Vineet, we've got some bits here you might want to play with. I'm about to leave for the evening, but I'll put you in touch with Raphael tomorrow afternoon.

[Bug tree-optimization/106888] [RISCV] Negative optimization that excess andi instructions are generated in gcc.dg/pr90838.c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106888 --- Comment #6 from Jeffrey A. Law --- Comment on attachment 54905 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=54905 proposed patch So that's a subset of what we've done. We initially thought that was going to be enough to solve this

[Bug tree-optimization/106888] [RISCV] Negative optimization that excess andi instructions are generated in gcc.dg/pr90838.c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106888 --- Comment #8 from Jeffrey A. Law --- So coming back to this after a couple months, I'm confident the match.pd change is unnecessary and in fact wrong. So we definitely want to set that aside.

[Bug rtl-optimization/109592] New: Failure to recognize shifts as sign/zero extension

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109592 Bug ID: 109592 Summary: Failure to recognize shifts as sign/zero extension Product: gcc Version: 13.0 Status: UNCONFIRMED Severity: normal Priority: P3 Componen

[Bug tree-optimization/106888] [RISCV] Negative optimization that excess andi instructions are generated in gcc.dg/pr90838.c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106888 --- Comment #10 from Jeffrey A. Law --- The sign_extend later gets turned into zero_extend. Presumably because we know the value is never negative. That in and of itself wouldn't be a big deal as it should be easily recognizable using any_exte

[Bug rtl-optimization/109592] Failure to recognize shifts as sign/zero extension

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109592 --- Comment #4 from Jeffrey A. Law --- If we need to handle subregs here, I would suggest something like this if (SUBREG_P (XEXP (op0, 0)) && subreg_lowpart_p (op0) ... other tests ... That way we know we're extracting the low word of

[Bug target/106585] RISC-V: Mis-optimized code gen for zbs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106585 --- Comment #11 from Jeffrey A. Law --- Coming back to this. WRT extension elimination. I've been pondering if we want a late pass to do a bit of this that can't be handled by REE. So let's take the case of a Zbs instruction operating on a va

[Bug testsuite/109549] [14 Regression] Conditional move regressions after r14-53-g675b1a7f113adb1d737adaf78b4fd90be7a0ed1a

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109549 Jeffrey A. Law changed: What|Removed |Added Target|x86_64-*-* |s390 Summary|[14 Regression

[Bug tree-optimization/109672] [14 regression] many ICEs after r14-323-g977a43f5ba778b

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109672 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug tree-optimization/109721] New: [14 Regression] predcom-2 fails after recent changes

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109721 Bug ID: 109721 Summary: [14 Regression] predcom-2 fails after recent changes Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3 Compon

[Bug testsuite/109776] New: [14 Regression] pr81192 fails on some targets after recent propagator changes

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109776 Bug ID: 109776 Summary: [14 Regression] pr81192 fails on some targets after recent propagator changes Product: gcc Version: 14.0 Status: UNCONFIRMED Severity:

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