[Bug target/116589] [15 regression] vectorization regressions on aarch64 since r15-1575-gea8061f46a30

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116589 --- Comment #4 from Andrew Pinski --- gcc.target/aarch64/sve/vec_bool_cmp_1.c and gcc.target/aarch64/sve/ptest_1.c looks like the same issue.

[Bug middle-end/116358] [15 Regression] undefined reference to `__umindi3' at -O3 when compiling with SVE since r15-2890-g72c9b5f438f22c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116358 Andrew Pinski changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/115910] [15 Regression] ((unsigned)x)/3 with a range for (unsigned)x that does not have the sign bit set seems to produce much worse code

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115910 Andrew Pinski changed: What|Removed |Added Component|middle-end |target --- Comment #2 from Andrew Pinsk

[Bug rtl-optimization/116028] [15 regression] gcc.dg/pr10474.c test failure since r15-1619-g3b9b8d6cfdf593

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116028 Thiago Jung Bauermann changed: What|Removed |Added CC||thiago.bauermann at linaro dot

[Bug target/116589] [15 regression] vectorization regressions on aarch64 since r15-1575-gea8061f46a30

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116589 --- Comment #5 from Thiago Jung Bauermann --- Thank you for the quick analysis and the testcase fix!

[Bug target/55212] [SH] Switch to LRA

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55212 --- Comment #229 from John Paul Adrian Glaubitz --- (In reply to John Paul Adrian Glaubitz from comment #228) > I'll have a go at Ada now. Ada still fails in subreg1: mkdir -p ada/libgnat/ /srv/glaubitz/gcc/build/./prev-gcc/xgcc -B/srv/glaubitz

[Bug target/116590] New: unrecognized opcode th.vmv8r.v th.vfrec7.v when compiling for risc-v xtheadvector

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116590 Bug ID: 116590 Summary: unrecognized opcode th.vmv8r.v th.vfrec7.v when compiling for risc-v xtheadvector Product: gcc Version: 15.0 Status: UNCONFIRMED Severi

[Bug target/116590] unrecognized opcode th.vmv8r.v th.vfrec7.v when compiling for risc-v xtheadvector

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116590 Andrew Pinski changed: What|Removed |Added Status|UNCONFIRMED |WAITING Last reconfirmed|

[Bug tree-optimization/116591] New: internal compiler error: in to_constant or extract_insn when compiling for risc-v xtheadvector

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116591 Bug ID: 116591 Summary: internal compiler error: in to_constant or extract_insn when compiling for risc-v xtheadvector Product: gcc Version: 15.0 Status: UNCONFIRMED

[Bug target/116590] unrecognized opcode th.vmv8r.v th.vfrec7.v when compiling for risc-v xtheadvector

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116590 --- Comment #2 from nihui --- (In reply to Andrew Pinski from comment #1) > What version of binutils are you using? binutils master branch commit 5cca20f614694ba6af3c10ca5bb93c32cdb9522b (HEAD -> master, origin/master, origin/HEAD) Author: GD

[Bug target/116590] unrecognized opcode th.vmv8r.v th.vfrec7.v when compiling for risc-v xtheadvector

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116590 --- Comment #3 from Andrew Pinski --- To me xtheadvector support Should never have been added.

[Bug target/116592] New: illegal operands th.vsetvli zero,0,e32,m8 with -O2 -O3 when compiling for risc-v xtheadvector

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116592 Bug ID: 116592 Summary: illegal operands th.vsetvli zero,0,e32,m8 with -O2 -O3 when compiling for risc-v xtheadvector Product: gcc Version: 15.0 Status: UNCONFIRMED

[Bug tree-optimization/116593] New: internal compiler error: in get_attr_type, at config/riscv/riscv.md:28048 with -O2 -O3 when compiling for risc-v xtheadvector

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116593 Bug ID: 116593 Summary: internal compiler error: in get_attr_type, at config/riscv/riscv.md:28048 with -O2 -O3 when compiling for risc-v xtheadvector Product: gcc

[Bug target/116592] illegal operands th.vsetvli zero,0,e32,m8 with -O2 -O3 when compiling for risc-v xtheadvector

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116592 --- Comment #1 from Andrew Pinski --- I think it is time to remove xtheadvector support it is just broken.

[Bug target/116594] New: [meta-bug] xtheadvector brokeness

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116594 Bug ID: 116594 Summary: [meta-bug] xtheadvector brokeness Product: gcc Version: 15.0 Status: UNCONFIRMED Keywords: meta-bug Severity: normal Priority: P3

[Bug target/116594] [meta-bug] xtheadvector brokeness

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116594 --- Comment #1 from Andrew Pinski --- All known brokeness of xtheadvector .

[Bug target/116590] unrecognized opcode th.vmv8r.v th.vfrec7.v when compiling for risc-v xtheadvector

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116590 Andrew Pinski changed: What|Removed |Added Ever confirmed|1 |0 Status|WAITING

[Bug target/116591] internal compiler error: in to_constant or extract_insn when compiling for risc-v xtheadvector

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116591 --- Comment #1 from Andrew Pinski --- The to_constant issue happens with -march=rv64gcv so filing it seperately.

[Bug target/116595] New: default-initialization of vfloat32m1x4_t causes ICE

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116595 Bug ID: 116595 Summary: default-initialization of vfloat32m1x4_t causes ICE Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Priority: P3 Compone

[Bug c++/116595] default-initialization of vfloat32m1x4_t (RISCV V) or svfloat32x4_t (Armv9-a SVE) causes ICE

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116595 Andrew Pinski changed: What|Removed |Added Summary|default-initialization of |default-initialization of

[Bug target/116591] internal compiler error: in extract_insn when compiling for risc-v xtheadvector

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116591 --- Comment #2 from Andrew Pinski --- Filed PR 116595 for the ICE in to_constant since it also happens with SVE code.

[Bug target/115910] [15 Regression] ((unsigned)x)/3 with a range for (unsigned)x that does not have the sign bit set seems to produce much worse code

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115910 --- Comment #3 from GCC Commits --- The trunk branch has been updated by Andrew Pinski : https://gcc.gnu.org/g:dbd0eb39c690f80e7a9bb7697aaa3f85ff4dbadd commit r15-3440-gdbd0eb39c690f80e7a9bb7697aaa3f85ff4dbadd Author: Andrew Pinski Date: Tu

[Bug target/116592] illegal operands th.vsetvli zero,0,e32,m8 with -O2 -O3 when compiling for risc-v xtheadvector

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116592 Kito Cheng changed: What|Removed |Added CC||cmuellner at gcc dot gnu.org,

[Bug c++/116595] default-initialization of vfloat32m1x4_t (RISCV V) or svfloat32x4_t (Armv9-a SVE) causes ICE

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116595 --- Comment #2 from Kito Cheng --- Hmmm, it's not well defined in the rvv intrinsic doc, but I suppose this should at least work (compile-able) without crash, also it seems works fine on GCC 14

[Bug c++/116595] default-initialization of vfloat32m1x4_t (RISCV V) or svfloat32x4_t (Armv9-a SVE) causes ICE

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116595 --- Comment #3 from Andrew Pinski --- (In reply to Kito Cheng from comment #2) > Hmmm, it's not well defined in the rvv intrinsic doc, but I suppose this > should at least work (compile-able) without crash, also it seems works fine > on GCC 14

[Bug c++/116595] default-initialization of vfloat32m1x4_t (RISCV V) or svfloat32x4_t (Armv9-a SVE) causes ICE

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116595 Andrew Pinski changed: What|Removed |Added Keywords||ice-checking --- Comment #4 from Andrew

[Bug c++/116595] default-initialization of vfloat32m1x4_t (RISCV V) or svfloat32x4_t (Armv9-a SVE) causes ICE

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116595 --- Comment #5 from Kito Cheng --- GCC 14 with enable checking will trigger that as well, thanks for remind that detail, I forgot trunk will enable checking by default but release branch isn't

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