[Bug target/106602] riscv: suboptimal codegen for zero_extendsidi2_shifted w/o bitmanip

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106602 --- Comment #11 from Vineet Gupta --- This definitely seems worth pursuing: For bitmanip, following four insn seq matches Trying 7, 8, 6 -> 9: 7: r78:DI=0x40 8: r77:DI=r78:DI-0x40 REG_EQUAL 0x3fffc0 6: r76:DI

[Bug target/106602] riscv: suboptimal codegen for zero_extendsidi2_shifted w/o bitmanip

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106602 --- Comment #12 from Jeffrey A. Law --- But insns 6, 7 and 8 aren't important here. We have a REG_EQUAL on insn 9 which indicates that (reg:DI 77) has the value 0xffc0. So I would have expected combine to substitute that into the u

[Bug target/106602] riscv: suboptimal codegen for zero_extendsidi2_shifted w/o bitmanip

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106602 --- Comment #13 from Jeffrey A. Law --- Trying 7, 8, 9 -> 10: 7: r140:DI=0x1 8: r141:DI=r140:DI<<0x26 REG_DEAD r140:DI REG_EQUAL 0x40 9: r139:DI=r141:DI-0x40 REG_DEAD r141:DI REG_EQUAL 0x3fffc0

[Bug fortran/107489] Runtime segfault in finalization routine of derived type with allocatable components

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107489 Jerry DeLisle changed: What|Removed |Added CC||jvdelisle at gcc dot gnu.org --- Commen

[Bug target/106602] riscv: suboptimal codegen for zero_extendsidi2_shifted w/o bitmanip

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106602 --- Comment #14 from Vineet Gupta --- (In reply to Jeffrey A. Law from comment #13) > Trying 7, 8, 9 -> 10: > 7: r140:DI=0x1 > 8: r141:DI=r140:DI<<0x26 > REG_DEAD r140:DI > REG_EQUAL 0x40 > 9: r139:DI=r141:DI-0x40

[Bug target/106602] riscv: suboptimal codegen for zero_extendsidi2_shifted w/o bitmanip

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106602 --- Comment #15 from Jeffrey A. Law --- THe hope is the shift 6 combines with the first shift you emit for (set (reg:DI 137) (and:DI (reg:DI 138) (const_int 274877906880 [0x3fffc0]))) Conceptually this is similar to creating br

[Bug target/106602] riscv: suboptimal codegen for zero_extendsidi2_shifted w/o bitmanip

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106602 --- Comment #16 from Andrew Pinski --- (In reply to Vineet Gupta from comment #14) > (In reply to Jeffrey A. Law from comment #13) > > Trying 7, 8, 9 -> 10: > > 7: r140:DI=0x1 > > 8: r141:DI=r140:DI<<0x26 > > REG_DEAD r140:DI > >

[Bug target/106602] riscv: suboptimal codegen for zero_extendsidi2_shifted w/o bitmanip

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106602 Andrew Pinski changed: What|Removed |Added Severity|normal |enhancement

[Bug tree-optimization/105532] UBSAN: gcc/hwint.h:293:61: runtime error: shift exponent 64 is too large for 64-bit type 'long unsigned int'

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105532 --- Comment #1 from Andrew Pinski --- Hmm, so prec is 0 here. gcc_checking_assert (prec < HOST_BITS_PER_WIDE_INT); int shift = HOST_BITS_PER_WIDE_INT - prec; return ((HOST_WIDE_INT) ((unsigned HOST_WIDE_INT) src << shift)) >> s

[Bug tree-optimization/105532] [11/12/13 Regression] UBSAN: gcc/hwint.h:293:61: runtime error: shift exponent 64 is too large for 64-bit type 'long unsigned int'

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105532 Andrew Pinski changed: What|Removed |Added Ever confirmed|0 |1 Summary|UBSAN: gcc/hwint.h

[Bug tree-optimization/105532] [11/12/13 Regression] UBSAN: gcc/hwint.h:293:61: runtime error: shift exponent 64 is too large for 64-bit type 'long unsigned int'

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105532 Andrew Pinski changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |pinskia at gcc dot gnu.org

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