https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116773
Bug 116773 depends on bug 113238, which changed state.
Bug 113238 Summary: [14] RISC-V: gcc.dg vect-tsvc flakey test timeouts when
under heavy workload
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113238
What|Removed
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116773
Bug 116773 depends on bug 114887, which changed state.
Bug 114887 Summary: RISC-V: expect M8 but M4 generated with dynamic LMUL for
TSVC s319
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114887
What|Removed |A
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116773
Bug 116773 depends on bug 114516, which changed state.
Bug 114516 Summary: RISC-V: TSVC2 s315 has spill with dynamic lmul
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114516
What|Removed |Added
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116773
Bug 116773 depends on bug 118188, which changed state.
Bug 118188 Summary: aarch64: worse code with -mtune=grace (vs -mtune=generic)
in TSVC s4115
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118188
What|Removed
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116773
Andrew Pinski changed:
What|Removed |Added
Ever confirmed|0 |1
Last reconfirmed|
