https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94135
--- Comment #5 from Segher Boessenkool ---
Please try it out on hardware (or on a cycle-accurate simulator) if you don't
believe me ;-)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94135
--- Comment #4 from Jens Seifert ---
Setting CA in XER increases issue to issue latency by 1 on Power8.
See:
Table 10-14. Issue-to-Issue Latencies
In addition, setting the CA restricts instruction reordering.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94135
--- Comment #3 from Segher Boessenkool ---
Both subfic and neg are 1-2 if run on the integer units. neg can run on
more units, but it is always 2 cycles then! (And the conditions where you
*can* have 1 cycle are not very often satisfied, anyway
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94135
--- Comment #2 from Jens Seifert ---
POWER8 Processor User’s Manual for the Single-Chip Module:
addi addis add add. subf subf. addic subfic adde addme subfme addze. subfze neg
neg. nego
1 - 2 cycles (GPR)
2 cycles (XER)
5 cycles (CR)
6/cycle,
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94135
Segher Boessenkool changed:
What|Removed |Added
Ever confirmed|0 |1
Last reconfirmed|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94135
Segher Boessenkool changed:
What|Removed |Added
CC||segher at gcc dot gnu.org
--- Comme
