https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90424
Richard Biener changed:
What|Removed |Added
Status|ASSIGNED|NEW
CC|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90424
--- Comment #6 from Richard Biener ---
Author: rguenth
Date: Thu May 16 08:03:49 2019
New Revision: 271279
URL: https://gcc.gnu.org/viewcvs?rev=271279&root=gcc&view=rev
Log:
2019-05-16 Richard Biener
PR tree-optimization/90424
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90424
--- Comment #5 from Richard Biener ---
(In reply to Matthias Kretz from comment #2)
> I can't read the SSA code with certainty, but bit-inserting sounds like what
> I want to have. Alternatively, the partial vector load could be implemented
> lik
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90424
--- Comment #4 from Richard Biener ---
One complication is that V2SFmode isn't valid on the target so at least
lowpart sets of V4SFmode are not easily possible (stupid MMX?), for
V8QImode we get a corresponding integer mode which works in the end
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90424
--- Comment #3 from Richard Biener ---
OK, so the "easier" way to allow aligned sub-vector inserts produces for
typedef unsigned char v16qi __attribute__((vector_size(16)));
v16qi load (const void *p)
{
v16qi r;
__builtin_memcpy (&r, p, 8);
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90424
--- Comment #2 from Matthias Kretz ---
FWIW, I agree that "bit-inserting into a default-def" isn't a good idea. My
code, in the meantime, looks more like this (https://godbolt.org/z/D-yfZJ):
template
using V [[gnu::vector_size(16)]] = T;
templ
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90424
Richard Biener changed:
What|Removed |Added
Status|UNCONFIRMED |ASSIGNED
Last reconfirmed|
