--- Comment #11 from ubizjak at gmail dot com 2008-11-25 09:15 ---
Should we fix __sync_synchronize in 4.3 too?
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=36793
--- Comment #10 from ubizjak at gmail dot com 2008-11-24 16:59 ---
Fixed.
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ubizjak at gmail dot com changed:
What|Removed |Added
Status|ASSIGNED
--- Comment #9 from uros at gcc dot gnu dot org 2008-11-24 16:57 ---
Subject: Bug 36793
Author: uros
Date: Mon Nov 24 16:55:49 2008
New Revision: 142160
URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=142160
Log:
* config/i386/i386.md (UNSPECV_CMPXCHG): Rename from
--- Comment #8 from samuel dot thibault at ens-lyon dot org 2008-11-22
19:41 ---
Ah, well, by "nop", I was thinking about things like what Linux does: lock;
addl $0,0(%%esp)
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=36793
--- Comment #7 from ubizjak at gmail dot com 2008-11-22 18:29 ---
Patch that implements "memory_barrier" for x86 at [1].
[1] http://gcc.gnu.org/ml/gcc-patches/2008-11/msg01181.html
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ubizjak at gmail dot com changed:
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--- Comment #6 from hjl dot tools at gmail dot com 2008-11-21 23:38 ---
I think it is a bug.
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=36793
--- Comment #5 from samuel dot thibault at ens-lyon dot org 2008-11-21
23:20 ---
We do already know which x86 memory barrier instruction we need, that's not the
problem, no need to give us pointers to documentations. The problem is that
we'd like to not use explicit x86 instructions but
--- Comment #4 from hjl dot tools at gmail dot com 2008-11-21 17:37 ---
The Intel Memory Ordering White Paper is at
http://www.intel.com/products/processor/manuals/318147.pdf
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=36793
--- Comment #3 from hjl dot tools at gmail dot com 2008-11-21 17:36 ---
__sync_synchronize isn't specified for IA32/Intel64. You can check
out Intel Memory Ordering White Paper:
www.intel.com/products/processor/manuals/318147.pdf
to see what is the most appropriate.
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http://gcc.
--- Comment #2 from ubizjak at gmail dot com 2008-11-21 17:22 ---
H.J. can probably confirm this.
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ubizjak at gmail dot com changed:
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--- Comment #1 from samuel dot thibault at ens-lyon dot org 2008-11-21
11:16 ---
Just to confirm the bug: the gcc doc says it follows the Intel itanium binary
interface. The Intel documentation says « Associated with each instrinsic are
certain memory barrier properties that restrict th
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