--
pinskia at gcc dot gnu dot org changed:
What|Removed |Added
Target Milestone|--- |4.1.3
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=31361
--- Comment #8 from rth at gcc dot gnu dot org 2007-04-04 23:13 ---
Subject: Bug 31361
Author: rth
Date: Wed Apr 4 23:13:13 2007
New Revision: 123505
URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=123505
Log:
PR target/31361
* config/i386/i386.c (ix86_init_mmx_s
--- Comment #7 from rth at gcc dot gnu dot org 2007-04-04 23:11 ---
Subject: Bug 31361
Author: rth
Date: Wed Apr 4 23:11:30 2007
New Revision: 123504
URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=123504
Log:
PR target/31361
* config/i386/i386.c (ix86_init_mmx_s
--- Comment #6 from prakash at punnoor dot de 2007-03-27 08:35 ---
Well, you commited the fix for the trunk, ie 4.2? But what about 4.1?
--
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=31361
--- Comment #5 from rth at gcc dot gnu dot org 2007-03-27 01:37 ---
You can shift the 32-bit portions individually. But your test case will now
result in 0,0,0,0 for all optimization levels, since the shift count is taken
from the entire xmm register. In this case, since there is an 8
--- Comment #4 from rth at gcc dot gnu dot org 2007-03-27 01:30 ---
Subject: Bug 31361
Author: rth
Date: Tue Mar 27 01:30:32 2007
New Revision: 123250
URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=123250
Log:
PR target/31361
* config/i386/i386.c (IX86_BUILTIN_PS
--- Comment #3 from rth at gcc dot gnu dot org 2007-03-26 19:14 ---
Confirmed. We've modeled the instruction incorrectly; it takes the shift
count from the entire 128-bit xmm register, not the low 32 or 8 bits.
--
rth at gcc dot gnu dot org changed:
What|Removed
