[Bug target/111246] PPC64 Sequentially Consistent Load allows Reordering of Stores

2023-08-31 Thread luke.geeson at cs dot ucl.ac.uk via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111246 --- Comment #18 from Luke Geeson --- Indeed that is a plus - I have 167k concurrency tests that I feed through LLVM/GCC -O1/2/3/fast and for GCC -Og that test compilation from the C/C++ to PPC memory models. If you are interested I can provide t

[Bug target/111246] PPC64 Sequentially Consistent Load allows Reordering of Stores

2023-08-31 Thread dje at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111246 --- Comment #17 from David Edelsohn --- I'm glad that we have confirmed that the GCC and LLVM code generation for PowerPC are correct for the memory model. And now your translation tool is more accurate.

[Bug target/111246] PPC64 Sequentially Consistent Load allows Reordering of Stores

2023-08-31 Thread luke.geeson at cs dot ucl.ac.uk via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111246 Luke Geeson changed: What|Removed |Added Resolution|--- |INVALID Status|NEW

[Bug target/111246] PPC64 Sequentially Consistent Load allows Reordering of Stores

2023-08-31 Thread luke.geeson at cs dot ucl.ac.uk via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111246 --- Comment #15 from Luke Geeson --- I am sorry to you all - I have wasted your time. It was a bug in the translation tool. In the future I will make absolutely sure that I check everything before submitting a bug - this is an embarrassing mis

[Bug target/111246] PPC64 Sequentially Consistent Load allows Reordering of Stores

2023-08-31 Thread dje at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111246 --- Comment #14 from David Edelsohn --- The conditional branch always will proceed to the next instruction, so the code that you showed in the PR is a correct "optimization" of the original code, but the processor does execute the conditional br

[Bug target/111246] PPC64 Sequentially Consistent Load allows Reordering of Stores

2023-08-31 Thread luke.geeson at cs dot ucl.ac.uk via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111246 --- Comment #13 from Luke Geeson --- Please bear with me whilst I figure out what has happened here.

[Bug target/111246] PPC64 Sequentially Consistent Load allows Reordering of Stores

2023-08-31 Thread pinskia at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111246 --- Comment #12 from Andrew Pinski --- (In reply to Luke Geeson from comment #11) > Do you have a trunk build of binutils to hand to test? Godbolt doesn't > support objdump. I will try to install binutils from source to reproduce. Yes it does.

[Bug target/111246] PPC64 Sequentially Consistent Load allows Reordering of Stores

2023-08-31 Thread luke.geeson at cs dot ucl.ac.uk via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111246 --- Comment #11 from Luke Geeson --- I'm using `powerpc64le-linux-gnu-objdump -Dr --disassemble --section=.text --no-show-raw-insn`. installed using `binutils-powerpc64le-linux-gnu` under Ubuntu 20:04 (in a docker container running on an Arm

[Bug target/111246] PPC64 Sequentially Consistent Load allows Reordering of Stores

2023-08-31 Thread dje at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111246 --- Comment #10 from David Edelsohn --- If I compile your testcase with either GCC 11.3 or GCC trunk, GCC produces P1: .LFB1: .cfi_startproc .localentry P1,1 pld 9,.LANCHOR0+8@pcrel sync lwz 9,0(9)

[Bug target/111246] PPC64 Sequentially Consistent Load allows Reordering of Stores

2023-08-31 Thread luke.geeson at cs dot ucl.ac.uk via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111246 --- Comment #9 from Luke Geeson --- apologies typos: bc -> bee bee -> beq

[Bug target/111246] PPC64 Sequentially Consistent Load allows Reordering of Stores

2023-08-31 Thread luke.geeson at cs dot ucl.ac.uk via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111246 --- Comment #8 from Luke Geeson --- I have not, but I will contact him and link this discussion. In the meantime, I read that page and provide some more testing. Consider the passage: ``` bc;isync: this is a very low-overhead and very weak form

[Bug target/111246] PPC64 Sequentially Consistent Load allows Reordering of Stores

2023-08-31 Thread dje at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111246 --- Comment #7 from David Edelsohn --- Have you reached out to Paul McKenney (now at Meta) who suggested the instruction sequences to implement the C/C++ memory for PowerPC? https://open-std.org/jtc1/sc22/wg21/docs/papers/2008/n2745.html

[Bug target/111246] PPC64 Sequentially Consistent Load allows Reordering of Stores

2023-08-31 Thread luke.geeson at cs dot ucl.ac.uk via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111246 --- Comment #6 from Luke Geeson --- Apologies - I've been thinking in syncs and fences too much! Yes I mean `lwsync`, for clarity I repeat the above so you know it is the correct fix: ``` lukegeeson@machine:~/Dev/tv-dev/herdtools7$ cat test.li

[Bug target/111246] PPC64 Sequentially Consistent Load allows Reordering of Stores

2023-08-31 Thread dje at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111246 David Edelsohn changed: What|Removed |Added Ever confirmed|0 |1 Status|UNCONFIRMED

[Bug target/111246] PPC64 Sequentially Consistent Load allows Reordering of Stores

2023-08-30 Thread luke.geeson at cs dot ucl.ac.uk via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111246 --- Comment #4 from Luke Geeson --- Add Wilco also addressed this for AArch64 in GCC: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108891

[Bug target/111246] PPC64 Sequentially Consistent Load allows Reordering of Stores

2023-08-30 Thread luke.geeson at cs dot ucl.ac.uk via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111246 --- Comment #3 from Luke Geeson --- According to the latest C/C++ and PPC models, yes. If x was non-atomic, then this would be a racy (UB) test, but making x atomic with relaxed order is well-defined according to the C model (and therefore any

[Bug target/111246] PPC64 Sequentially Consistent Load allows Reordering of Stores

2023-08-30 Thread pinskia at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111246 Andrew Pinski changed: What|Removed |Added Target||powerpc64le --- Comment #2 from Andrew

[Bug target/111246] PPC64 Sequentially Consistent Load allows Reordering of Stores

2023-08-30 Thread luke.geeson at cs dot ucl.ac.uk via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111246 --- Comment #1 from Luke Geeson --- Edit: The godbolt link points to the same bug in LLVM I am reporting, here is the GCC godbolt link https://godbolt.org/z/Tan5jrvKa