https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101200
--- Comment #8 from Andrew Pinski ---
(In reply to Andrew Pinski from comment #3)
> For aarch64 we get:
> adrpx1, .LANCHOR0
> add x0, x1, :lo12:.LANCHOR0
> add x0, x0, 8
> ldrbw1, [x1, #:lo12:.LANC
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101200
--- Comment #7 from Jeffrey A. Law ---
FWIW, it might be worth considering using a mode iterator for the shift count
to allow multiple modes.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101200
--- Comment #6 from Steinar H. Gunderson ---
You're right, I don't know why the shrq happened. When I run now, I get shrb.
Doesn't matter for the bug, though.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101200
--- Comment #5 from Jakub Jelinek ---
BTW, I certainly can't reproduce what #c0 shows, while I see movzbl in there
because QImode loads are done that way in most tunings,
I certainly see
shrb$4, %al
rather than 64-bit right shift.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101200
Jakub Jelinek changed:
What|Removed |Added
CC||jakub at gcc dot gnu.org,
