[Bug rtl-optimization/64537] Aarch64 redundant sxth instruction gets generated

2021-08-22 Thread pinskia at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64537 Andrew Pinski changed: What|Removed |Added Status|RESOLVED|NEW Resolution|FIXED

[Bug rtl-optimization/64537] Aarch64 redundant sxth instruction gets generated

2021-08-22 Thread pinskia at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64537 Andrew Pinski changed: What|Removed |Added Resolution|--- |FIXED Target Milestone|---

[Bug rtl-optimization/64537] Aarch64 redundant sxth instruction gets generated

2016-08-11 Thread pinskia at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64537 Andrew Pinski changed: What|Removed |Added Severity|normal |enhancement

[Bug rtl-optimization/64537] Aarch64 redundant sxth instruction gets generated

2015-01-28 Thread ramana at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64537 Ramana Radhakrishnan changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug rtl-optimization/64537] Aarch64 redundant sxth instruction gets generated

2015-01-18 Thread kugan at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64537 --- Comment #5 from kugan at gcc dot gnu.org --- Is this sort of multiple-use potential candidate for ree pass? Haven't looked ree in detail yet.

[Bug rtl-optimization/64537] Aarch64 redundant sxth instruction gets generated

2015-01-08 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64537 --- Comment #4 from Richard Earnshaw --- b is used twice, once shifted left by 3 and once directly. We could write this as subsx3, x0, x1, sxth 3 beq .L5 add w0, w2, w1, sxth <= Now extended

[Bug rtl-optimization/64537] Aarch64 redundant sxth instruction gets generated

2015-01-08 Thread kugan at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64537 --- Comment #3 from kugan at gcc dot gnu.org --- But isn't w1 is passed with 16bit value (short b) here. Am I missing something here?

[Bug rtl-optimization/64537] Aarch64 redundant sxth instruction gets generated

2015-01-08 Thread pinskia at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64537 --- Comment #2 from Andrew Pinski --- (In reply to kugan from comment #1) > According to AAPCS64 > (http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055c/ > IHI0055C_beta_aapcs64.pdf), the unused parm register bits have "unspecified > value".

[Bug rtl-optimization/64537] Aarch64 redundant sxth instruction gets generated

2015-01-08 Thread kugan at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64537 kugan at gcc dot gnu.org changed: What|Removed |Added CC||kugan at gcc dot gnu.org --- C