https://gcc.gnu.org/bugzilla/show_bug.cgi?id=18041
Richard Biener changed:
What|Removed |Added
Status|ASSIGNED|RESOLVED
Resolution|---
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=18041
--- Comment #11 from Richard Biener ---
Author: rguenth
Date: Tue Nov 6 08:09:03 2018
New Revision: 265829
URL: https://gcc.gnu.org/viewcvs?rev=265829&root=gcc&view=rev
Log:
2018-11-06 Richard Biener
PR middle-end/18041
* si
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=18041
--- Comment #10 from Segher Boessenkool ---
If combine tries to split RTL into two instructions, it tries to do that
one way (and one way only). It picked the AND here. It did not work.
You can add some define_split to your target to help comb
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=18041
Richard Biener changed:
What|Removed |Added
CC||segher at gcc dot gnu.org
--- Comment #
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=18041
--- Comment #8 from Richard Biener ---
We're still "stuck" on GIMPLE, on x86_64 we manage to elide the redundant load
now and get
foo:
.LFB0:
.cfi_startproc
movzbl (%rdi), %eax
movl%eax, %edx
shrb%dl
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=18041
--- Comment #7 from Richard Biener ---
GCC 6 at -O2 on x86_64 produces
foo:
.LFB0:
.cfi_startproc
movzbl (%rdi), %eax
movl%eax, %edx
shrb%dl
orl %eax, %edx
andl$-2, %eax
an
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=18041
--- Comment #6 from Richard Guenther 2011-05-11
10:53:00 UTC ---
Author: rguenth
Date: Wed May 11 10:52:57 2011
New Revision: 173650
URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=173650
Log:
2011-05-11 Richard Guenther
PR tree-op
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=18041
--- Comment #5 from Richard Guenther 2011-05-10
11:38:50 UTC ---
With a patch I have we now optimize at the tree level to
:
D.2686_2 = b_1(D)->bit0;
D.2688_4 = b_1(D)->bit1;
D.2693_10 = D.2688_4 ^ D.2686_2;
b_1(D)->bit0 = D.2693_10;
re
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=18041
Richard Guenther changed:
What|Removed |Added
Status|NEW |ASSIGNED
AssignedTo|unassigned
--- Additional Comments From pinskia at gcc dot gnu dot org 2005-02-07
06:02 ---
This is a much harder problem than doing a simplification at combine time
because we have five
instructions to worry about.
--
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=18041
--- Additional Comments From pinskia at gcc dot gnu dot org 2004-10-17 17:05
---
Confirmed about the extra and (I don't know why the extra load is in x86).
--
What|Removed |Added
--- Additional Comments From pinskia at gcc dot gnu dot org 2004-10-17 17:01
---
Hmm, there is only one load on PPC (with either side):
same bit layout as below:
lwz r0,0(r3)
rlwinm r2,r0,0,31,31
rlwinm r9,r0,31,31,31
or r2,r2,r9
rlwimi r0,r2,0,31,
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