https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94502
Richard Earnshaw changed:
What|Removed |Added
Resolution|FIXED |INVALID
--- Comment #7 from Richard E
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94502
Luis Machado changed:
What|Removed |Added
Status|UNCONFIRMED |RESOLVED
Resolution|---
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94502
--- Comment #5 from Luis Machado ---
Thanks for confirming this behavior. There have been some changes to the DWARF
unwinding code that exposed this particular case. I'm guessing this will need
to go back to GDB for a fixup.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94502
--- Comment #4 from Wilco ---
(In reply to Luis Machado from comment #3)
> The lack of a rule for LR means GDB will assume the register is UNSPECIFIED.
> Is GCC assuming this register is considered to have the same value as an
> inner frame?
Ri
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94502
--- Comment #3 from Luis Machado ---
Here's a DWARF and asm dump from the same binary:
00d0 001c FDE cie=
pc=07f4..0830
DW_CFA_advance_loc: 4 to 07f8
DW_CFA_def_cfa_offset: 32
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94502
Wilco changed:
What|Removed |Added
CC||wilco at gcc dot gnu.org
--- Comment #2 from Wil
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94502
--- Comment #1 from Luis Machado ---
CC-ing ARM folks so they can assign this to whoever is more appropriate.
