[Bug target/117013] aarch64 should define spaceship4 optab

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117013 Richard Sandiford changed: What|Removed |Added Status|NEW |ASSIGNED --- Comment #5 from Richar

[Bug target/118531] [14/15 Regression] aarch64/ins_bitfield_1.c generates INS instructions even for +nosimd

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118531 Richard Sandiford changed: What|Removed |Added Ever confirmed|0 |1 Last reconfirmed|

[Bug target/118531] New: [14/15 Regression] aarch64/ins_bitfield_1.c generates INS instructions even for +nosimd

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118531 Bug ID: 118531 Summary: [14/15 Regression] aarch64/ins_bitfield_1.c generates INS instructions even for +nosimd Product: gcc Version: 15.0 Status: UNCONFIRMED

[Bug ipa/117432] [12/13/14/15 Regression] IPA ICF disregards types of variadic arguments since r10-4643-ga37f58f506e436

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117432 Richard Sandiford changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org --- Com

[Bug target/118328] Implement preserve_none for AArch64

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118328 --- Comment #11 from Richard Sandiford --- Created attachment 60175 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=60175&action=edit Proof-of-concept patch Here's a lightly-tested proof-of-concept patch for preserve_none on AArch64. In p

[Bug target/118377] ICE when using C division operator with svint8 and svint16

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118377 --- Comment #10 from Richard Sandiford --- (In reply to Tejas Belagod from comment #9) > Technically, as this is not a regression, can we fix this to sorry more > gracefully for GCC15 as 'Not yet implemented'? Yeah. The testcase is IMO valid AC

[Bug fortran/118471] New: Missed folding of descriptor span field for contiguous Fortran pointers

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118471 Bug ID: 118471 Summary: Missed folding of descriptor span field for contiguous Fortran pointers Product: gcc Version: 15.0 Status: UNCONFIRMED Keywords: missed

[Bug target/118418] [15 Regression][gcn] Compiler selftest ICE in assert_rtx_eq_at, at selftest-rtl.cc:57 / FAIL: ASSERT_RTX_EQ (val, folded) since r15-6777-g06c4cf398947b5

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118418 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/118418] [15 Regression][gcn] Compiler selftest ICE in assert_rtx_eq_at, at selftest-rtl.cc:57 / FAIL: ASSERT_RTX_EQ (val, folded) since r15-6777-g06c4cf398947b5

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118418 Richard Sandiford changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org

[Bug rtl-optimization/117186] [12/13/14 Regression] aarch64 wrong code for (a < b) < (b < a)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117186 Richard Sandiford changed: What|Removed |Added Summary|[12/13/14/15 Regression]|[12/13/14 Regression]

[Bug target/107102] SVE function fails to realize it doesn't need the frame-pointer in the tail call.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107102 Richard Sandiford changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug c++/118301] Feature request: CLI parament std with explicit experimental values

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118301 --- Comment #6 from Richard Sandiford --- (In reply to Jonathan Wakely from comment #5) > We already have -std=c++2a for that and it doesn't solve anything. You obviously know better than me :), but I thought c++2a was used for things that aren'

[Bug c++/118301] Feature request: CLI parament std with explicit experimental values

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118301 Richard Sandiford changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org --- Com

[Bug target/118328] Implement preserve_none for AArch64

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118328 --- Comment #2 from Richard Sandiford --- (In reply to Andrew Pinski from comment #1) > Note most of the use cases in my view for these attributes. These attributes > are there specifically to work around the fact that llvm does not do ipa ra >

[Bug target/107102] SVE function fails to realize it doesn't need the frame-pointer in the tail call.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107102 Richard Sandiford changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org

[Bug target/118328] New: Implement preserve_none for AArch64

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118328 Bug ID: 118328 Summary: Implement preserve_none for AArch64 Product: gcc Version: 15.0 Status: UNCONFIRMED Keywords: ABI Severity: enhancement Priority: P3

[Bug rtl-optimization/117938] [15 Regression] wrong code with -O2 --param=max-cse-insns=1 with late-combine (since r15-1735-ge62ea4fb8ffcab)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117938 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug rtl-optimization/117186] [12/13/14/15 Regression] aarch64 wrong code for (a < b) < (b < a)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117186 Richard Sandiford changed: What|Removed |Added Status|NEW |ASSIGNED Assignee|unassig

[Bug rtl-optimization/117938] [15 Regression] wrong code with -O2 --param=max-cse-insns=1 with late-combine (since r15-1735-ge62ea4fb8ffcab)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117938 Richard Sandiford changed: What|Removed |Added Status|NEW |ASSIGNED Assignee|unassig

[Bug target/118184] [14 backport] glibc regression on aarch64 due to early_ra deleting movti instruction since r15-5422-g279475fd7236a9

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118184 Richard Sandiford changed: What|Removed |Added Summary|[15 regression] glibc |[14 backport] glibc

[Bug target/118184] [15 regression] glibc regression on aarch64 due to early_ra deleting movti instruction since r15-5422-g279475fd7236a9

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118184 Richard Sandiford changed: What|Removed |Added Status|NEW |ASSIGNED Assignee|unassig

[Bug tree-optimization/118215] Miss runtime alias check for vectorization

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118215 Richard Sandiford changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org --- Com

[Bug target/118133] Consider alternative ways of writing aarch64-simd-pragma-builtins.def

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118133 --- Comment #3 from Richard Sandiford --- The reason I went for m4 is that it means we don't need to write a parser, or come up with a DSL. I was hoping that the scaffolding would be pretty much write-and-forget, with only the main (declarative

[Bug driver/117968] running "cpp" with malformed arguments can cause input file deletion

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117968 Richard Sandiford changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org --- Com

[Bug target/118151] New: Relax the SVE PTEST matching conditions for any/none (ne/eq)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118151 Bug ID: 118151 Summary: Relax the SVE PTEST matching conditions for any/none (ne/eq) Product: gcc Version: 15.0 Status: UNCONFIRMED Keywords: aarch64-sve, miss

[Bug target/118150] New: Failure to fold NOT+PTEST to NOTS for SVE

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118150 Bug ID: 118150 Summary: Failure to fold NOT+PTEST to NOTS for SVE Product: gcc Version: 15.0 Status: UNCONFIRMED Keywords: aarch64-sve, missed-optimization Severity: nor

[Bug target/118133] New: Consider alternative ways of writing aarch64-simd-pragma-builtins.def

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118133 Bug ID: 118133 Summary: Consider alternative ways of writing aarch64-simd-pragma-builtins.def Product: gcc Version: 15.0 Status: UNCONFIRMED Keywords: build

[Bug target/117978] Optimise 128-bit-predicated SVE loads to Advanced SIMD LDRs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117978 --- Comment #3 from Richard Sandiford --- I think this would be better done in expand rather than gimple. The gimple representation would be a vector load in a 128-bit type, followed by a zeroing extension to the original SVE type. I'm not sur

[Bug target/117989] New: aarch64: FMV attaches symvers to the wrong decl

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117989 Bug ID: 117989 Summary: aarch64: FMV attaches symvers to the wrong decl Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component:

[Bug middle-end/117987] New: Function multiversioning does not respect decl asms

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117987 Bug ID: 117987 Summary: Function multiversioning does not respect decl asms Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Priority: P3 Compone

[Bug target/96340] Extend AArch64 "omp declare simd" support to general simdlen

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96340 --- Comment #2 from Richard Sandiford --- (In reply to Andrew Pinski from comment #1) > was this also fixed by r14-6416-gf5fc001a84a7db ? No, it's still unfixed due to: /* We currently do not support generating simdclones where vector argument

[Bug target/117850] GCC emits DUP, UMULL instead of UMULL2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117850 --- Comment #3 from Richard Sandiford --- (In reply to rguent...@suse.de from comment #2) > I dont See how this is easier? It's not to simplify things :) But isn't gimple_fold_builtin restricted to the same search/valueisation domain as match.

[Bug target/117850] GCC emits DUP, UMULL instead of UMULL2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117850 Richard Sandiford changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org --- Com

[Bug rtl-optimization/117838] [12/13/14/15 regression] IRA issues: The higher cost variable a is spilled for the lower cost variable conflict_a in improve_allocation() since r12-6416-g037cc0b4a6646c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117838 Richard Sandiford changed: What|Removed |Added Last reconfirmed||2024-11-29 Ever confirmed|0

[Bug target/107704] [13/14/15 Regression] Testsuite regression after recent DCE changes

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107704 --- Comment #9 from Richard Sandiford --- That's because clobbers of hard-coded registers have usually been treated as kind-of an earlyclobbers: - When a @code{clobber} expression for a register appears insid

[Bug rtl-optimization/117297] [15 Regression] late combine undoes too much

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117297 Richard Sandiford changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/116371] The SME2 svpext intrinsics are missing a _lane suffix

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116371 Richard Sandiford changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/116629] [14 Regression] Building openvino with -flto ICEs in aarch64_sve::gimple_folder::redirect_pred_x

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116629 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug rtl-optimization/117297] [15 Regression] late combine undoes too much

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117297 Richard Sandiford changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org

[Bug target/117248] gcc/libgcc/libgcc2.h:232:25: internal compiler error: Arithmetic exception

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117248 --- Comment #2 from Richard Sandiford --- Also, could you check whether g:9bd19ff515c95af71b29bc6e232785532afa6823 makes a difference?

[Bug target/117169] New: Missed opportunity to combine sign and bitmask tests

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117169 Bug ID: 117169 Summary: Missed opportunity to combine sign and bitmask tests Product: gcc Version: 15.0 Status: UNCONFIRMED Keywords: missed-optimization Severity: enhan

[Bug rtl-optimization/116550] [lra][avr] internal compiler error: in final_scan_insn_1, at final.cc:2807

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116550 --- Comment #12 from Richard Sandiford --- (In reply to denisc from comment #4) > Explanation. > […] Thanks for the great explanation! Based on that, the patch LGTM FWIW, although Vlad should have the final say.

[Bug target/55212] [SH] Switch to LRA

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55212 --- Comment #389 from Richard Sandiford --- (In reply to Oleg Endo from comment #304) > (define_insn "block_lump_real" > [(set (mem:BLK (match_operand:SI 2 "sfunc_arg0_reg" "=r,r")) > (mem:BLK (match_operand:SI 3 "sfunc_arg1_reg" "=r,r

[Bug target/116629] [14 Regression] Building openvino with -flto ICEs in aarch64_sve::gimple_folder::redirect_pred_x

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116629 Richard Sandiford changed: What|Removed |Added Known to work||15.0 Summary|[14/15 Regr

[Bug target/117045] Incorrect fold of SVE's svwhilele

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117045 --- Comment #3 from Richard Sandiford --- Ah, yeah, the patch fixes that too. The easiest fix seemed to be to handle the degenerate cases up-front rather than as part of constant folding. I deliberately left off folding svwhilelt(INT_MAX, x) t

[Bug target/117045] Incorrect fold of SVE's svwhilele

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117045 Richard Sandiford changed: What|Removed |Added Status|UNCONFIRMED |ASSIGNED Ever confirmed|0

[Bug target/117045] New: Incorrect fold of SVE's svwhilele

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117045 Bug ID: 117045 Summary: Incorrect fold of SVE's svwhilele Product: gcc Version: 15.0 Status: UNCONFIRMED Keywords: wrong-code Severity: normal Priority: P3

[Bug target/109498] SVE support for ctz

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109498 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug tree-optimization/116578] vectorizer SLP transition issues / dependences

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116578 Bug 116578 depends on bug 116583, which changed state. Bug 116583 Summary: vectorizable_slp_permutation cannot handle even/odd extract from VLA vector https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116583 What|Removed

[Bug tree-optimization/116583] vectorizable_slp_permutation cannot handle even/odd extract from VLA vector

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116583 Richard Sandiford changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug tree-optimization/116583] vectorizable_slp_permutation cannot handle even/odd extract from VLA vector

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116583 --- Comment #10 from Richard Sandiford --- I have a proof-of-concept hack (far from submission quality). But it looks like some cases will also require us to extend aarch64_evpc_reencode to handle SVE modes, which is also worthwhile for its own

[Bug tree-optimization/116583] vectorizable_slp_permutation cannot handle even/odd extract from VLA vector

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116583 Richard Sandiford changed: What|Removed |Added Status|NEW |ASSIGNED Assignee|unassig

[Bug target/116629] [14/15 Regression] Building openvino with -flto ICEs in aarch64_sve::gimple_folder::redirect_pred_x

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116629 Richard Sandiford changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org

[Bug tree-optimization/116583] vectorizable_slp_permutation cannot handle even/odd extract from VLA vector

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116583 --- Comment #7 from Richard Sandiford --- ...actually, they probably don't need to bijective. I suppose [0, 0] for two-lane SLP is handled too.

[Bug tree-optimization/116583] vectorizable_slp_permutation cannot handle even/odd extract from VLA vector

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116583 --- Comment #6 from Richard Sandiford --- Sorry for the slow response (here and in general). Been having to spend my time on other things recently :( I agree that this case is regular enough to handle for VLA, but it seems to me like a separat

[Bug rtl-optimization/116326] [lra] internal compiler error: in get_reload_reg, at lra-constraints.cc:755

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116326 --- Comment #8 from Richard Sandiford --- (In reply to Georg-Johann Lay from comment #7) > What about the following line in reload1.h: > > // Used during roload -> LRA transition because ELIMINABLE_REGS may depend > // on command line options.

[Bug rtl-optimization/116326] [lra] internal compiler error: in get_reload_reg, at lra-constraints.cc:755

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116326 --- Comment #6 from Richard Sandiford --- (In reply to Georg-Johann Lay from comment #5) > > But either way, I think we should start with the assumption that the entry > > should be removed and make everything else work to that. Unfortunately t

[Bug rtl-optimization/116326] [lra] internal compiler error: in get_reload_reg, at lra-constraints.cc:755

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116326 --- Comment #4 from Richard Sandiford --- (In reply to Georg-Johann Lay from comment #3) > It was due to problems with multi-reg frame-pointer. (AFAIR, using a > hard-frame-poiner besides frame-poiner didn't resolve the issues.) > > My problem

[Bug rtl-optimization/116326] [lra] internal compiler error: in get_reload_reg, at lra-constraints.cc:755

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116326 Richard Sandiford changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org --- Com

[Bug rtl-optimization/116516] [15 Regression] [lra] ICE in decompose_normal_address, at rtlanal.cc:6712 by r15-3213-g708ee71808ea61

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116516 Richard Sandiford changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug tree-optimization/116481] [12/13/14/15 Regression] `arrays of functions are not meaningful` error message happens with -W -Wall -O2 even though there are no arrays of function types used

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116481 --- Comment #10 from Richard Sandiford --- (In reply to Richard Sandiford from comment #9) > If the tag bit is dropped by going > out of bounds, that's a feature, not a bug, and would happen equally for > void*/char* arithmetic as for (u)intptr_

[Bug tree-optimization/116481] [12/13/14/15 Regression] `arrays of functions are not meaningful` error message happens with -W -Wall -O2 even though there are no arrays of function types used

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116481 Richard Sandiford changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org --- Com

[Bug rtl-optimization/116516] [15 Regression] [lra] ICE in decompose_normal_address, at rtlanal.cc:6712 by r15-3213-g708ee71808ea61

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116516 Richard Sandiford changed: What|Removed |Added Status|NEW |ASSIGNED Assignee|unassig

[Bug fortran/116254] new test case gfortran.dg/class_transformational_2.f90 from r15-2739-g4cb07a38233aad fails

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116254 Richard Sandiford changed: What|Removed |Added Status|UNCONFIRMED |NEW Ever confirmed|0

[Bug fortran/116254] new test case gfortran.dg/class_transformational_2.f90 from r15-2739-g4cb07a38233aad fails

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116254 Richard Sandiford changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org --- Com

[Bug rtl-optimization/116238] [12/13/14 Regression] ICE building 526.blender_r on aarch64 SVE after r15-1619-g3b9b8d6cfdf593

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116238 Richard Sandiford changed: What|Removed |Added Known to fail|15.0|14.2.1 Summary|[12/13/14

[Bug target/116413] [LRA] [M68K] ICE: unrecognized insn in lra_set_insn_recog_data, at lra.cc:1036

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116413 --- Comment #17 from Richard Sandiford --- Hmm, but if the ICE is coming from vregs then it doesn't sound like it's related to LRA. vregs is the first RTL pass to run.

[Bug target/116413] [LRA] [M68K] ICE: unrecognized insn in lra_set_insn_recog_data, at lra.cc:1036

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116413 --- Comment #14 from Richard Sandiford --- Created attachment 58967 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=58967&action=edit Patch for the decompse_mem_address ICE Thanks. Can you try the attached patch?

[Bug target/116413] [LRA] [M68K] ICE: unrecognized insn in lra_set_insn_recog_data, at lra.cc:1036

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116413 --- Comment #11 from Richard Sandiford --- I can't reproduce this with m68k-elf. Do you have any local changes beyond making TARGET_LRA_P return true?

[Bug rtl-optimization/116321] [lra][avr] internal compiler error: in avr_out_lpm_no_lpmx, at config/avr/avr.cc:4572

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116321 Richard Sandiford changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org --- Com

[Bug rtl-optimization/116238] [15 Regression] ICE building 526.blender_r on aarch64 SVE after r15-1619-g3b9b8d6cfdf593

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116238 Richard Sandiford changed: What|Removed |Added Status|NEW |ASSIGNED Assignee|unassig

[Bug target/116413] [LRA] [M68K] ICE: unrecognized insn in lra_set_insn_recog_data, at lra.cc:1036

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116413 Richard Sandiford changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org --- Com

[Bug target/115683] [15 Regression] SSE2 regressions after obselete of vcond{,u,eq}.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115683 --- Comment #8 from Richard Sandiford --- (In reply to Uroš Bizjak from comment #7) > Richi, maybe tree optimizers can perform their optimizations with > vec_cmp{,u} and vcond_mask, and at the end provide the true coditional > vector move (that

[Bug target/114603] aarch64: Invalid SVE cnot optimisation

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114603 Richard Sandiford changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/114607] aarch64: Incorrect expansion of svsudot

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114607 Richard Sandiford changed: What|Removed |Added Known to work||12.4.1, 13.3.1, 14.1.0,

[Bug target/115464] [14 Backport] ICE when building libaom on arm64 (neon sve bridge usage with tbl/perm)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115464 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/113939] Switch m68k to LRA

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113939 Bug 113939 depends on bug 116236, which changed state. Bug 116236 Summary: [LRA] [M68K] ICE insn does not satisfy its constraints https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116236 What|Removed |Added

[Bug target/116236] [LRA] [M68K] ICE insn does not satisfy its constraints

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116236 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/116343] [15 regression] ICE on valid code at -Os with "-fschedule-insns -fno-thread-jumps -fno-dce" on x86_64-linux-gnu: in extract_insn, at recog.cc:2869

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116343 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/116236] [LRA] [M68K] ICE insn does not satisfy its constraints

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116236 --- Comment #22 from Richard Sandiford --- (In reply to Michael Matz from comment #21) > (In reply to Richard Sandiford from comment #17) > > > But if LRA needs to be extended for correctness, then, ... meh. > > But this is how it's always worke

[Bug target/116371] The SME2 svpext intrinsics are missing a _lane suffix

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116371 --- Comment #2 from Richard Sandiford --- Fixed on trunk. I'll wait a bit before backporting.

[Bug target/116371] The SME2 svpext intrinsics are missing a _lane suffix

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116371 Richard Sandiford changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org

[Bug target/116371] New: The SME2 svpext intrinsics are missing a _lane suffix

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116371 Bug ID: 116371 Summary: The SME2 svpext intrinsics are missing a _lane suffix Product: gcc Version: 14.1.0 Status: UNCONFIRMED Keywords: rejects-valid Severity: normal

[Bug target/116236] [LRA] [M68K] ICE insn does not satisfy its constraints

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116236 --- Comment #19 from Richard Sandiford --- Of course, immediately after posting I realise it should be address_mode instead of pointer_mode, but that shouldn't affect m68k.

[Bug target/116236] [LRA] [M68K] ICE insn does not satisfy its constraints

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116236 --- Comment #18 from Richard Sandiford --- Created attachment 58927 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=58927&action=edit Candidate patch Could you try the attached patch? It seems to fix the reduced testcase for me.

[Bug target/116236] [LRA] [M68K] ICE insn does not satisfy its constraints

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116236 Richard Sandiford changed: What|Removed |Added Status|NEW |ASSIGNED Assignee|unassig

[Bug target/116236] [LRA] [M68K] ICE insn does not satisfy its constraints

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116236 --- Comment #15 from Richard Sandiford --- (In reply to Michael Matz from comment #14) > (In reply to Richard Sandiford from comment #13) > > (In reply to Michael Matz from comment #12) > > > That's why I struggle a bit, I lack the bigger pictur

[Bug target/116343] [15 regression] ICE on valid code at -Os with "-fschedule-insns -fno-thread-jumps -fno-dce" on x86_64-linux-gnu: in extract_insn, at recog.cc:2869

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116343 Richard Sandiford changed: What|Removed |Added Status|NEW |ASSIGNED Assignee|unassig

[Bug target/116343] [15 regression] ICE on valid code at -Os with "-fschedule-insns -fno-thread-jumps -fno-dce" on x86_64-linux-gnu: in extract_insn, at recog.cc:2869

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116343 --- Comment #4 from Richard Sandiford --- (In reply to Andrew Pinski from comment #3) > Note I think late_combine 1 depends on DCE later on to delete the > noop_move_p instructions but since -fno-dce was passed on the command line, > it is not d

[Bug target/116312] Use LDP instead of LD2 on for Advanced SIMD when possible

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116312 Richard Sandiford changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org --- Com

[Bug target/116236] [LRA] [M68K] ICE insn does not satisfy its constraints

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116236 Richard Sandiford changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org --- Com

[Bug other/30920] Incorrect splaying that fails to assure the caching property

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=30920 --- Comment #8 from Richard Sandiford --- The patch in comment 7 is just one step.

[Bug target/116145] SVE constant pool loads not hoisted outside loops

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116145 Richard Sandiford changed: What|Removed |Added Resolution|FIXED |--- Status|RESOLVED

[Bug rtl-optimization/116200] [15 regression] ICE in stage 2 since r15-2696-gba730fd10934e4

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116200 Richard Sandiford changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug other/30920] Incorrect splaying that fails to assure the caching property

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=30920 Richard Sandiford changed: What|Removed |Added Status|UNCONFIRMED |ASSIGNED Ever confirmed|0

[Bug target/116145] SVE constant pool loads not hoisted outside loops

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116145 Richard Sandiford changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/116145] Suboptimal SVE immediate synthesis

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116145 Richard Sandiford changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org

[Bug target/116145] Suboptimal SVE immediate synthesis

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116145 Richard Sandiford changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org --- Com

[Bug target/115881] [15 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1934 with -O2 -mx32 -maddress-mode=long

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115881 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug tree-optimization/116109] Missed optimisation: unnecessary register dependency on reduction

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116109 Richard Sandiford changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org --- Com

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