[Bug target/121415] New: aarch64: Failure to handle PSTATE.SM & ZA for tlsdesc calls

2025-08-05 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
-sme, wrong-code Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: rsandifo at gcc dot gnu.org Target Milestone: --- Target: aarch64*-*-* For: extern __thread int x; i

[Bug target/121414] aarch64: streaming & streaming-compatible functions should be marked as variant PCS

2025-08-05 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
|1 Last reconfirmed||2025-08-05 Assignee|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org --- Comment #1 from Richard Sandiford --- Mine.

[Bug target/121414] New: aarch64: streaming & streaming-compatible functions should be marked as variant PCS

2025-08-05 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
RMED Keywords: aarch64-sme, wrong-code Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: rsandifo at gcc dot gnu.org Target Milestone: --- Target: aarch64*-*-* For: vo

[Bug target/120718] ICE (unrecognizable insn) with const_poly_int in v2si vector

2025-08-04 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120718 Richard Sandiford changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org

[Bug target/121294] [13/14/15 Backport] Incorrect optimisation of b16/32/64 forms of SVE permute intrinsics

2025-08-04 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121294 Richard Sandiford changed: What|Removed |Added Summary|Incorrect optimisation of |[13/14/15 Backport]

[Bug target/121293] svdupq_lane produces suboptimal code for big-endian SVE

2025-08-04 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121293 Richard Sandiford changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/121358] [15/16 Regression] SVE ICE compiling highway since r15-4235

2025-08-04 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121358 --- Comment #6 from Richard Sandiford --- That makes it sound like the same issue as PR120718: https://inbox.sourceware.org/gcc-patches/mpta55xpfro@arm.com/

[Bug target/121294] Incorrect optimisation of b16/32/64 forms of SVE permute intrinsics

2025-07-29 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121294 Richard Sandiford changed: What|Removed |Added Last reconfirmed||2025-07-29 Ever confirmed|0

[Bug target/121294] New: Incorrect optimisation of b16/32/64 forms of SVE permute intrinsics

2025-07-29 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
-sve, wrong-code Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: rsandifo at gcc dot gnu.org Target Milestone: --- Target: aarch64*-*-* #include svbool_t foo () { return svtrn1_b16

[Bug target/121293] svdupq_lane produces suboptimal code for big-endian SVE

2025-07-29 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
||2025-07-29 Ever confirmed|0 |1 Assignee|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org --- Comment #1 from Richard Sandiford --- I have a patch.

[Bug target/121293] New: svdupq_lane produces suboptimal code for big-endian SVE

2025-07-29 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: rsandifo at gcc dot gnu.org Target Milestone: --- Target: aarch64*-*-* Compiling: #pragma GCC aarch64 "arm_sve.h" svint32_t f(s

[Bug target/121027] [14 Regression] ICE with BF16 and SVE at -O2 -msve-vector-bits=256

2025-07-26 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121027 Richard Sandiford changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/121027] [14 Regression] ICE with BF16 and SVE at -O2 -msve-vector-bits=256

2025-07-26 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121027 --- Comment #10 from Richard Sandiford --- Fixed. I backported both r15-4111-g4fd473f66faf5bd95c84fe5c0fa41be735a7c09f and the trunk fix for the code quality regression.

[Bug target/118891] [14 regression] gcc 14 fails to build from source on aarch64_be: "error: ‘dynamic_cast’ not permitted with ‘-fno-rtti’"

2025-07-26 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118891 Richard Sandiford changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug rtl-optimization/121218] [15/16 regression] highway miscompiled at -O2 -march=znver2 since r15-3036-gb8ea13ebf12117

2025-07-23 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121218 --- Comment #12 from Richard Sandiford --- On the REG_DEAD thing: REG_DEAD notes are not kept up-to-date, so any pass that wants to use them needs to ask for them to be recomputed. The REG_DEAD usage in scalar_chain::convert_insn_common suggest

[Bug target/121118] ICE when constructing a fixed-length SVE predicate

2025-07-16 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
|1 Assignee|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org Last reconfirmed||2025-07-16 --- Comment #1 from Richard Sandiford --- Mine.

[Bug target/121118] New: ICE when constructing a fixed-length SVE predicate

2025-07-16 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: rsandifo at gcc dot gnu.org Target Milestone: --- Target: aarch64*-*-* [https://godbolt.org/z/fYffh9bn8] Compiling: typedef __SVBool_t fixed_bool

[Bug tree-optimization/121059] [15/16 regression] ICE when building imagemagick-7.1.1-47 (vect_get_loop_mask, at tree-vect-loop.cc:10960) since r15-5383-g8f68d9cb7897df

2025-07-14 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121059 --- Comment #11 from Richard Sandiford --- > if (masked_loop_p > && code == BIT_AND_EXPR > && VECTOR_BOOLEAN_TYPE_P (vectype)) > { > if (loop_vinfo->scalar_cond_masked_set.contains

[Bug tree-optimization/121059] [15/16 regression] ICE when building imagemagick-7.1.1-47 (vect_get_loop_mask, at tree-vect-loop.cc:10960) since r15-5383-g8f68d9cb7897df

2025-07-14 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121059 --- Comment #10 from Richard Sandiford --- (In reply to Richard Biener from comment #9) > vectorizable_operation during transform does > > /* When combining two masks check if either of them is elsewhere > combined with a

[Bug target/121027] [14 Regression] ICE with BF16 and SVE at -O2 -msve-vector-bits=256

2025-07-11 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org --- Comment #5 from Richard Sandiford --- Mine for the backport. I'll have a look at the code quality regression too.

[Bug target/118891] [14/15 regression] gcc 14 fails to build from source on aarch64_be: "error: ‘dynamic_cast’ not permitted with ‘-fno-rtti’"

2025-07-07 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118891 Richard Sandiford changed: What|Removed |Added Summary|[14/15/16 regression] gcc |[14/15 regression] gcc 14

[Bug target/118891] [14/15/16 regression] gcc 14 fails to build from source on aarch64_be: "error: ‘dynamic_cast’ not permitted with ‘-fno-rtti’"

2025-07-04 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org --- Comment #23 from Richard Sandiford --- I've posted a couple of patches that should help with this: * https://gcc.gnu.org/pipermail/gcc-patches/2025-July/688599.html * https://gcc.gnu.org/pipermail/gcc-patches/2025-July/688605.html

[Bug target/120624] [14 Backport] aarch64: Incorrect DCE of a ZA restore in SME code

2025-07-03 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120624 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/120733] [16 Regression][aarch64] ICE in gen_highpart, at lra.cc:1484 since r16-1565-g2dcc6dbd8a00ca

2025-06-30 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120733 Richard Sandiford changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/120347] [15 regression] invalid arm32/thumb assembly output

2025-06-25 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120347 Richard Sandiford changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/120733] [16 Regression][aarch64] ICE in gen_highpart, at lra.cc:1484 since r16-1565-g2dcc6dbd8a00ca

2025-06-24 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org --- Comment #7 from Richard Sandiford --- Testing a patch.

[Bug rtl-optimization/120750] SEGV in remove_use, at rtl-ssa/accesses.cc:1276

2025-06-23 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120750 Richard Sandiford changed: What|Removed |Added Last reconfirmed||2025-06-23 Status|UNCON

[Bug rtl-optimization/120745] SEGV in process_uses_of_deleted_def, at rtl-ssa/changes.cc:271

2025-06-23 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120745 --- Comment #2 from Richard Sandiford --- Created attachment 61697 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=61697&action=edit Candidate patch Hmm, yeah. Could you try the attached patch? It seems to work for this testcase and pass

[Bug middle-end/120721] [16 regression] ICE when building llvm-20.1.7 on arm64 (instantiate_virtual_regs_in_insn, at function.cc:1737)

2025-06-23 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120721 Richard Sandiford changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug middle-end/120721] [16 regression] ICE when building llvm-20.1.7 on arm64 (instantiate_virtual_regs_in_insn, at function.cc:1737)

2025-06-20 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120721 Richard Sandiford changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org

[Bug target/113027] aarch64 is missing vec_set and vec_extract for structure modes

2025-06-17 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113027 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug target/120624] [14/15 Backport] aarch64: Incorrect DCE of a ZA restore in SME code

2025-06-12 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120624 Richard Sandiford changed: What|Removed |Added Known to work||16.0 Summary|aarch64: In

[Bug target/120624] aarch64: Incorrect DCE of a ZA restore in SME code

2025-06-10 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
|1 Assignee|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org Last reconfirmed||2025-06-10 --- Comment #1 from Richard Sandiford --- Testing a patch.

[Bug target/120624] New: aarch64: Incorrect DCE of a ZA restore in SME code

2025-06-10 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: rsandifo at gcc dot gnu.org Target Milestone: --- Target: aarch64*-*-* For: #include void callee(); __arm_new("za") __arm_locally_streamin

[Bug target/119210] [SME] 'smstart za' seems not to dominate the block that uses za register

2025-06-10 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
|UNCONFIRMED |WAITING CC||rsandifo at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #8 from Richard Sandiford --- I'm not sure why you're getting an illegal instruction, but the conditional SMS

[Bug target/120447] [16 Regression] cpython fails to compile on AArch64 after r16-446-g210d06502f22964c7214586c54f8eb54a6965bfd

2025-06-04 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120447 Richard Sandiford changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/120447] [16 Regression] cpython fails to compile on AArch64 after r16-446-g210d06502f22964c7214586c54f8eb54a6965bfd

2025-06-02 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120447 --- Comment #9 from Richard Sandiford --- I think the ICE is caused by a bad interaction between the AArch64 optimisation and r16-718, which added more checks for paradoxical subregs. The testcase works if r16-718 is reverted. I think the shou

[Bug target/120447] [16 Regression] cpython fails to compile on AArch64 after r16-446-g210d06502f22964c7214586c54f8eb54a6965bfd

2025-06-02 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120447 --- Comment #8 from Richard Sandiford --- I think we've already got the right condition for partial modes: /* If the predicate in operands[2] is a patterned SVE PTRUE predicate with patterns VL1, VL2, VL4, VL8, or VL16 and at most the bo

[Bug target/120447] [16 Regression] cpython fails to compile on AArch64 after r16-446-g210d06502f22964c7214586c54f8eb54a6965bfd

2025-06-02 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120447 --- Comment #6 from Richard Sandiford --- I think a paradoxical VNx4QI subreg of QI is logically ok, but I'd need to think a bit more about what the exact conditions should be. I don't think we should rush into an aarch64 workaround.

[Bug target/119610] [12 regression] aarch64: Wrong unwind info with -fstack-clash-protection -fstack-protector-strong since r14-3900-g3e4afea3b192c2

2025-05-30 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119610 Richard Sandiford changed: What|Removed |Added Known to work||12.4.1 Resolution|---

[Bug rtl-optimization/111901] Apparently bogus CSE of inline asm with memory clobber

2025-05-30 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111901 --- Comment #14 from Richard Sandiford --- ISTM that the problem is that cselib doesn't consider: (clobber (mem:BLK (scratch))) to be a read from memory (unlike note_uses, which gets this right). cselib instead assumes that the SET_SRC of t

[Bug target/120347] [15/16 regression] invalid arm32/thumb assembly output

2025-05-19 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org CC||rsandifo at gcc dot gnu.org --- Comment #3 from Richard Sandiford --- Mine then.

[Bug target/120292] New: amdgcn: Infinite recursion in vec_cmpudi_exec

2025-05-15 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: rsandifo at gcc dot gnu.org Target Milestone: --- Target: amdgcn*-*-* The following pattern is infinitely recursive. It looks like it should be calling "vec_cmp..." r

[Bug target/117978] Optimise 128-bit-predicated SVE loads to Advanced SIMD LDRs

2025-05-09 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117978 Richard Sandiford changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/120050] [15/16 Regression] ICE bootstrapping on mips64el with --with-arch=gs464 --with-build-config=bootstrap-O3 --enable-checking=yes,extra

2025-05-07 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120050 Richard Sandiford changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org

[Bug target/119966] [16 regression] pru: Invalid register in RTL expression starting with r16-160-ge6f89d78c1a752

2025-04-30 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119966 --- Comment #6 from Richard Sandiford --- (In reply to Andrew Pinski from comment #4) > validate_subreg allows the paradoxical subreg even in the case of hard > register: > ``` > /* Paradoxical subregs must have offset zero. */ > if (maybe_

[Bug target/120007] New: AArch64 incorrectly handles 16-bit HFAs

2025-04-29 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: rsandifo at gcc dot gnu.org Target Milestone: --- Target: aarch64*-*-* AAPCS64 defined __fp16 and __bf16 to map to the same fundamental data type: a half-precision floating-point

[Bug target/119974] Missing combination of SVE RDFFRS

2025-04-29 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
||rsandifo at gcc dot gnu.org Status|UNCONFIRMED |WAITING Ever confirmed|0 |1 --- Comment #1 from Richard Sandiford --- Removing the PTEST wouldn't be correct in isolation, since RDFFRS+B.LAST would test the

[Bug target/96191] aarch64 stack_protect_test canary leak

2025-04-25 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96191 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug tree-optimization/113416] ICE: in force_constant_size, at gimplify.cc:742 (in convert_move, at expr.cc:223) with -march=rv64gcv (-march=rv32gcv) and -ftree-parallelize-loops=2

2025-04-25 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113416 Bug 113416 depends on bug 101018, which changed state. Bug 101018 Summary: ICE when enabling OpenMP on a simple loop with SVE intrinsics (aarch64) https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101018 What|Removed

[Bug middle-end/101018] ICE when enabling OpenMP on a simple loop with SVE intrinsics (aarch64)

2025-04-25 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101018 Richard Sandiford changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug tree-optimization/119399] [12 Backport] Overlap check in vectorized code may invoke UB

2025-04-25 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119399 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug middle-end/118443] [Meta bug] Bugs triggered by and blocking more smtgcc testing

2025-04-25 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118443 Bug 118443 depends on bug 119399, which changed state. Bug 119399 Summary: [12 Backport] Overlap check in vectorized code may invoke UB https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119399 What|Removed |Added --

[Bug tree-optimization/53947] [meta-bug] vectorizer missed-optimizations

2025-04-25 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=53947 Bug 53947 depends on bug 116125, which changed state. Bug 116125 Summary: [12 Regression] Does not fully checking for overlapping memory regions with the vectorizer https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116125 What|Removed

[Bug tree-optimization/116125] [12 Regression] Does not fully checking for overlapping memory regions with the vectorizer

2025-04-25 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116125 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/118501] [14 regression] aarch64: ICE in simplify_context::simplify_subreg

2025-04-16 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118501 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/119133] [14 Regression] ICE: SIGSEGV in mark_label_nuses (emit-rtl.cc:3896) with -O -fno-tree-ter and _Float16 since r14-1131

2025-04-16 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119133 Richard Sandiford changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/115258] [14 Regression] register swaps for vector perm in some cases after r14-6290

2025-04-16 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115258 Richard Sandiford changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug tree-optimization/119399] [12/13/14 Backport] Overlap check in vectorized code may invoke UB

2025-04-10 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119399 Richard Sandiford changed: What|Removed |Added Summary|Overlap check in vectorized |[12/13/14 Backport] Overlap

[Bug target/119610] [12/13/14/15 regression] aarch64: Wrong unwind info with -fstack-clash-protection -fstack-protector-strong since r14-3900-g3e4afea3b192c2

2025-04-10 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org --- Comment #5 from Richard Sandiford --- Mine.

[Bug tree-optimization/119399] Overlap check in vectorized code may invoke UB

2025-04-10 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119399 --- Comment #5 from Richard Sandiford --- (In reply to rguent...@suse.de from comment #4) > >, so for a 4-element > > vector, the only problem cases are p==q+4, p==q+8 and p==q+12. That's > > equivalent to testing whether the unsigned value p-(

[Bug tree-optimization/119399] Overlap check in vectorized code may invoke UB

2025-04-09 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org --- Comment #3 from Richard Sandiford --- Taking for the pointer difference. (In reply to Richard Biener from comment #2) > Still the actual alias check looks prone to overflow issues since we do > not distinguish before/after pla

[Bug bootstrap/119689] [15 Regression] Bootstrap comparison failure on i586-linux since r15-9239

2025-04-09 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119689 --- Comment #14 from Richard Sandiford --- (In reply to Richard Biener from comment #13) > diff --git a/gcc/lra-remat.cc b/gcc/lra-remat.cc > index 2f3afffcf5b..5f823193aa7 100644 > --- a/gcc/lra-remat.cc > +++ b/gcc/lra-remat.cc > @@ -460,7 +46

[Bug bootstrap/119689] [15 Regression] Bootstrap comparison failure on i586-linux since r15-9239

2025-04-09 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org --- Comment #10 from Richard Sandiford --- Mine.

[Bug tree-optimization/104200] [12/13/14/15 Regression] FAIL: gcc.target/aarch64/atomic-inst-cas.c (test for excess errors) fails

2025-04-09 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104200 Richard Sandiford changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org

[Bug rtl-optimization/116398] [15 Regression] gcc.target/aarch64/ashltidisi.c fails since r15-268

2025-04-07 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116398 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug c++/116595] default-initialization of vfloat32m1x4_t (RISCV V) or svfloat32x4_t (Armv9-a SVE) causes ICE

2025-04-03 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116595 Richard Sandiford changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org

[Bug rtl-optimization/97286] simplified subreg used outside of the loop can cause conflict and cause an extra move inside the loop

2025-04-01 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97286 --- Comment #9 from Richard Sandiford --- (In reply to ktkachov from comment #8) > Richard, do you think this is something early-ra in aarch64 is well-placed > to address? Or is there perhaps a realistic IRA solution? I don't think the RAs can ha

[Bug rtl-optimization/97286] simplified subreg used outside of the loop can cause conflict and cause an extra move inside the loop

2025-04-01 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97286 --- Comment #10 from Richard Sandiford --- (In reply to Richard Sandiford from comment #9) > … Or perhaps we > could do the optimisation in gimple, so that there is only one loop-carried > dependency coming into expand. That is, replace: [loc

[Bug rtl-optimization/116398] [15 Regression] gcc.target/aarch64/ashltidisi.c fails since r15-268

2025-03-31 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org --- Comment #28 from Richard Sandiford --- I'm back from holiday, so taking. (In reply to Segher Boessenkool from comment #26) > So, the one thing I really worry about a bit: will everything still work if > we can lose some l

[Bug target/119495] 8% slowdown of 436.cactusADM on AMD Zen2 since r15-7895-gb191e8bdecf881

2025-03-31 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119495 --- Comment #2 from Richard Sandiford --- (In reply to Filip Kastl from comment #0) > So my understanding is that this slowdown isn't really that important. > However, it seemed reasonable to at least notify Richard Sandiford about > this in ca

[Bug rtl-optimization/116398] [15 Regression] gcc.target/aarch64/ashltidisi.c fails since r15-268

2025-03-14 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116398 --- Comment #23 from Richard Sandiford --- (In reply to Segher Boessenkool from comment #22) > (In reply to Richard Sandiford from comment #18) > > but: the problem in PR101523 was that, after each > > successful 2->2 attempt, distribute_links w

[Bug rtl-optimization/116398] [15 Regression] gcc.target/aarch64/ashltidisi.c fails since r15-268

2025-03-14 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116398 --- Comment #20 from Richard Sandiford --- (In reply to Richard Sandiford from comment #18) > Still more than 0% of course, but nevertheless much less than before. than before the fix for PR101523 went in, I mean.

[Bug rtl-optimization/116398] [15 Regression] gcc.target/aarch64/ashltidisi.c fails since r15-268

2025-03-14 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116398 --- Comment #18 from Richard Sandiford --- Created attachment 60754 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=60754&action=edit Proof of concept patch with hard-coded limit I'd been reluctant to get involved in this for fear of creat

[Bug tree-optimization/119287] [15 regression] ICE when building linux-6.12.19 (error: type mismatch in binary expression) since r15-8025

2025-03-14 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119287 --- Comment #4 from Richard Sandiford --- (In reply to Jakub Jelinek from comment #3) > tree_nop_conversion_p certainly doesn't imply the two types are compatible > types. > So, I think we should go with > --- gcc/match.pd.jj 2025-03-13 14:05:

[Bug testsuite/113965] gcc.target/aarch64/sve/mask_struct_load_3_run.c still fails with qemu due to _Float16 rounding error

2025-03-13 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113965 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug testsuite/113965] gcc.target/aarch64/sve/mask_struct_load_3_run.c still fails with qemu due to _Float16 rounding error

2025-03-13 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org CC||rsandifo at gcc dot gnu.org Ever confirmed|0 |1 Last reconfirmed||2025-03-13 --- Comment #4 from Richard Sandiford --- Mine

[Bug target/115248] [15 regresion] aarch64/sve/pre_cond_share_1.c fails since r15-276-gbed6ec161be8c5

2025-03-13 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115248 Richard Sandiford changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/115248] [15 regresion] aarch64/sve/pre_cond_share_1.c fails since r15-276-gbed6ec161be8c5

2025-03-12 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115248 Richard Sandiford changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org

[Bug target/116901] [15 Regression] pr110625_4.c fails on aarch64 since r15-3794-g2c04f175de4f39

2025-03-12 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116901 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug rtl-optimization/118956] [15 regression] gcc.target/aarch64/sve/pred-not-gen-[14].c fail after r15-268-g9dbff9c05520a74e

2025-03-11 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118956 --- Comment #4 from Richard Sandiford --- XFAILed for GCC 15, keeping open for the actual fix.

[Bug tree-optimization/118976] [12 Regression] Correctness Issue: SVE vectorization results in data corruption when cpu has 128bit vectors but compiled with -mcpu=neoverse-v1 (which is only for 256bit

2025-03-11 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118976 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug middle-end/26163] [meta-bug] missed optimization in SPEC (2k17, 2k and 2k6 and 95)

2025-03-11 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=26163 Bug 26163 depends on bug 116238, which changed state. Bug 116238 Summary: [12 Regression] ICE building 526.blender_r on aarch64 SVE after r15-1619-g3b9b8d6cfdf593 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116238 What|Removed

[Bug rtl-optimization/116238] [12 Regression] ICE building 526.blender_r on aarch64 SVE after r15-1619-g3b9b8d6cfdf593

2025-03-11 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116238 Richard Sandiford changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/117045] [12 Backport] Incorrect fold of SVE's svwhilele

2025-03-11 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117045 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/117045] [12 Backport] Incorrect fold of SVE's svwhilele

2025-03-11 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117045 --- Comment #8 from Richard Sandiford --- Fixed

[Bug rtl-optimization/116564] [12/13/14/15 Regression] aarch64: gcc hangs when compiling vst2_f64 instrinsic at -O1 and above since r12-4910-g66f206b853

2025-03-11 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116564 --- Comment #7 from Richard Sandiford --- (In reply to Alex Coplan from comment #6) > So I'm testing the following to do this (which so far survives bootstrap on > aarch64): > > diff --git a/gcc/df-problems.cc b/gcc/df-problems.cc > index f3218

[Bug target/119114] [14/15 regression] RISC-V: miscompile at -O3 since r14-4077-g86451305d8b

2025-03-11 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119114 --- Comment #21 from Richard Sandiford --- Perhaps I'm missing the point, but I don't think we should look at 1 vs -1 for . has only a single bit. That bit is interpreted as a sign bit for extension purposes, but that only matters when an ext

[Bug target/116901] [15 Regression] pr110625_4.c fails on aarch64 since r15-3794-g2c04f175de4f39

2025-03-10 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116901 Richard Sandiford changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org

[Bug rtl-optimization/119174] [15 Regression] IRA allocating value live across a call to call clobbered register

2025-03-10 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119174 --- Comment #13 from Richard Sandiford --- (In reply to Jeffrey A. Law from comment #11) > Andrew. You're missing the point. This scenario isn't the kind of thing > that reload and LRA are supposed to fix. They fix constraint problems. ie, >

[Bug target/119133] [14 Regression] ICE: SIGSEGV in mark_label_nuses (emit-rtl.cc:3896) with -O -fno-tree-ter and _Float16 since r14-1131

2025-03-07 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119133 Richard Sandiford changed: What|Removed |Added Summary|[14/15 Regression] ICE: |[14 Regression] ICE:

[Bug tree-optimization/116125] [12/13/14 Regression] Does not fully checking for overlapping memory regions with the vectorizer

2025-03-07 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116125 Richard Sandiford changed: What|Removed |Added Summary|[12/13/14/15 Regression]|[12/13/14 Regression] Does

[Bug target/119156] Placement of PTRUE instructions prevents PTEST elimination

2025-03-07 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119156 Richard Sandiford changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org

[Bug target/119156] New: Placement of PTRUE instructions prevents PTEST elimination

2025-03-07 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
-optimization Severity: enhancement Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: rsandifo at gcc dot gnu.org CC: tnfchris at gcc dot gnu.org Target Milestone: --- Target: aarch64*-*-* Tamar

[Bug tree-optimization/116125] [12/13/14/15 Regression] Does not fully checking for overlapping memory regions with the vectorizer

2025-03-06 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116125 --- Comment #5 from Richard Sandiford --- (In reply to Richard Biener from comment #3) > We document > > class dr_with_seg_len > { > ... > /* The minimum common alignment of DR's start address, SEG_LEN and > ACCESS_SIZE. */ > unsign

[Bug target/119142] [15 Regression] Many regressions since r15-7852 on i686-linux

2025-03-06 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119142 --- Comment #1 from Richard Sandiford --- Sorry, I thought Honza had regression-tested it on x86, but I realise now that I didn't confirm whether he had. I reverted the patch in r15-7862-g2c6ab4c443ae3278.

[Bug target/118957] [15 Regression] 5-9% slowdown of 511.povray_r and 453.povray since r15-7400-gd3ff498c478ace

2025-03-06 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118957 Richard Sandiford changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org

[Bug target/118959] [15 Regression] 5-14% slowdown of 400.perlbench since r15-7400-gd3ff498c478ace

2025-03-06 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118959 Richard Sandiford changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org

[Bug target/117477] Register allocator chooses a slot location instead a new callee saved register and not taking inot account pair allocation

2025-03-06 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117477 Richard Sandiford changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/119133] [14/15 Regression] ICE: SIGSEGV in mark_label_nuses (emit-rtl.cc:3896) with -O -fno-tree-ter and _Float16 since r14-1131

2025-03-06 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org --- Comment #2 from Richard Sandiford --- Mine.

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