[Bug target/115458] [15 regression] [RISC-V] ICE in lra_split_hard_reg_for, at lra-assigns.cc:1868 unable to find a register to spill since r15-518-g99b1daae18c095

2025-01-28 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115458 Palmer Dabbelt changed: What|Removed |Added CC||palmer at gcc dot gnu.org --- Comment

[Bug middle-end/118356] RISC-V: -falign-labels=0 should (probably) default to 4

2025-01-08 Thread palmer at gcc dot gnu.org via Gcc-bugs
||2025-01-08 Keywords||missed-optimization CC||palmer at gcc dot gnu.org Status|UNCONFIRMED |NEW --- Comment #1 from Palmer Dabbelt --- (In reply to Javier Mora from comment

[Bug target/117544] Lack of vsetvli after function call for whole register move

2024-11-20 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117544 Palmer Dabbelt changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug target/117544] Lack of vsetvli after function call for whole register move

2024-11-12 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117544 --- Comment #1 from Palmer Dabbelt --- (In reply to Kito Cheng from comment #0) > I'm not sure if it's reasonable to ask the Linux kernel maintainers to fix > this by keeping VILL consistent across system calls. That doesn't fix the problem: we

[Bug target/116693] [RISC-V] @tlsdesc generates duplicate assembler labels

2024-09-12 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116693 --- Comment #2 from Palmer Dabbelt --- I think something like this diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 9f94b5aa023..c64c881d152 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -2334

[Bug target/116615] Investigate LOGICAL_OP_NON_SHORT_CIRCUIT for RISC-V

2024-09-05 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116615 --- Comment #9 from Palmer Dabbelt --- (In reply to Xi Ruoyao from comment #3) > FYI on LoongArch it's claimed LOGICAL_OP_NON_SHORT_CIRCUIT=0 mostly helps FP > benchmarks, something like > > /* { dg-options "-O2 -ffast-math -fdump-tree-gimple"

[Bug target/116615] Investigate LOGICAL_OP_NON_SHORT_CIRCUIT for RISC-V

2024-09-05 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116615 --- Comment #8 from Palmer Dabbelt --- (In reply to Andrew Pinski from comment #7) > History on LOGICAL_OP_NON_SHORT_CIRCUIT being able to defined differently > from BRANCH_COST. It was originally added for powerpc (2002/2003ish) which > had exp

[Bug target/116615] Investigate LOGICAL_OP_NON_SHORT_CIRCUIT for RISC-V

2024-09-05 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116615 Palmer Dabbelt changed: What|Removed |Added CC||palmer at gcc dot gnu.org --- Comment

[Bug target/115687] RISC-V optimization when "lui" instructions can be merged

2024-06-27 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115687 --- Comment #8 from Palmer Dabbelt --- (In reply to Andrew Waterman from comment #6) > I note MIPS sets TARGET_CONST_ANCHOR to 0x8000, and that architecture's > ADDIU instruction has a 16-bit immediate. RISC-V's ADDI instruction has a > 12-bit

[Bug target/115687] RISC-V optimization when "lui" instructions can be merged

2024-06-27 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115687 --- Comment #5 from palmer at gcc dot gnu.org --- (In reply to Andrew Pinski from comment #3) > (In reply to Andrew Pinski from comment #2) > > There is some code in cse.cc which does handle this. > > See > > https://g

[Bug target/115687] RISC-V optimization when "lui" instructions can be merged

2024-06-27 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115687 --- Comment #4 from palmer at gcc dot gnu.org --- Just poking around a bit: I think this is coming from CSE, which is replacing (insn 5 2 6 2 (set (reg:DI 135) (const_int 16384 [0x4000])) "pr115687.c":7:12 275 {*movdi_64bit}

[Bug target/115687] RISC-V optimization when "lui" instructions can be merged

2024-06-27 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115687 palmer at gcc dot gnu.org changed: What|Removed |Added Last reconfirmed||2024-06-27 Ever

[Bug target/115217] New: Register pairs can't be encoded in RISC-V inline asm blocks

2024-05-24 Thread palmer at gcc dot gnu.org via Gcc-bugs
ormal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: palmer at gcc dot gnu.org Target Milestone: --- Alex is trying to do the amocas.q support in Linux, which operates on paired X registers by providing only the even register i

[Bug target/114809] [RISC-V RVV] Counting elements might be simpler

2024-04-22 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114809 palmer at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |NEW Keywords

[Bug target/114175] [13/14] RISC-V: Execution test failures on gcc.dg/c23-stdarg-6.c

2024-02-29 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114175 --- Comment #18 from palmer at gcc dot gnu.org --- (In reply to palmer from comment #17) > (In reply to Edwin Lu from comment #16) > > So if I understand correctly, there may also be a problem where it's trying > > to cre

[Bug target/114175] [13/14] RISC-V: Execution test failures on gcc.dg/c23-stdarg-6.c

2024-02-29 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114175 --- Comment #17 from palmer at gcc dot gnu.org --- (In reply to Edwin Lu from comment #16) > (In reply to palmer from comment #15) > > It's a little easier to see from the float version of the code. > > > > $ cat gcc/t

[Bug target/114175] [13/14] RISC-V: Execution test failures on gcc.dg/c23-stdarg-6.c

2024-02-29 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114175 --- Comment #15 from palmer at gcc dot gnu.org --- It's a little easier to see from the float version of the code. $ cat gcc/testsuite/gcc.dg/c23-stdarg-6.c /* Test C23 variadic functions with no named parameters, or last named para

[Bug target/114175] [13/14] RISC-V: Execution test failures on gcc.dg/c23-stdarg-6.c

2024-02-29 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114175 palmer at gcc dot gnu.org changed: What|Removed |Added Last reconfirmed||2024-02-29 Ever

[Bug target/114175] [13/14] RISC-V: Execution test failures on gcc.dg/c23-stdarg-6.c

2024-02-29 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114175 palmer at gcc dot gnu.org changed: What|Removed |Added CC||palmer at gcc dot gnu.org

[Bug other/109668] 'python' vs. 'python3'

2024-02-09 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109668 palmer at gcc dot gnu.org changed: What|Removed |Added CC||palmer at gcc dot gnu.org

[Bug target/113686] [RISC-V] TLS (Local Exec) relaxation on structures (LE)

2024-01-31 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113686 palmer at gcc dot gnu.org changed: What|Removed |Added CC||nelsonc1225 at sourceware

[Bug libstdc++/84568] libstdc++-v3 configure checks for atomic operations fail on riscv

2024-01-18 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84568 --- Comment #13 from palmer at gcc dot gnu.org --- I just stumbled back into this one. I think it's fixed?

[Bug target/113087] [14] RISC-V rv64gcv vector: Runtime mismatch with rv64gc

2023-12-22 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113087 palmer at gcc dot gnu.org changed: What|Removed |Added CC||palmer at gcc dot gnu.org

[Bug target/112531] [14] RISC-V: gcc.dg/unroll-8.c rtl-dump scan errors with --param=riscv-autovec-preference=scalable

2023-11-21 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112531 palmer at gcc dot gnu.org changed: What|Removed |Added Last reconfirmed||2023-11-21 Ever

[Bug target/112295] RISC-V: Short forward branch pessimisation for ALU operations

2023-10-30 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112295 palmer at gcc dot gnu.org changed: What|Removed |Added Last reconfirmed||2023-10-30 Ever

[Bug target/111600] [14 Regression] RISC-V bootstrap time regression

2023-09-27 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111600 palmer at gcc dot gnu.org changed: What|Removed |Added CC||palmer at gcc dot gnu.org

[Bug target/104831] RISCV libatomic LR.aq/SC.rl pair insufficient for SEQ_CST

2023-09-25 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104831 palmer at gcc dot gnu.org changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |patrick at rivosinc

[Bug c/111518] relro protection not working in riscv

2023-09-21 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111518 palmer at gcc dot gnu.org changed: What|Removed |Added CC||palmer at gcc dot gnu.org

[Bug target/111501] RISC-V: non-optimal casting when shifting

2023-09-20 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111501 palmer at gcc dot gnu.org changed: What|Removed |Added Last reconfirmed||2023-09-20

[Bug target/111139] RISC-V: improve scalar constants cost model

2023-08-24 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=39 palmer at gcc dot gnu.org changed: What|Removed |Added Last reconfirmed||2023-08-24 Ever

[Bug target/111065] [RISCV] t-linux-multilib specifies incorrect multilib reuse patterns

2023-08-18 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111065 palmer at gcc dot gnu.org changed: What|Removed |Added CC||palmer at gcc dot gnu.org

[Bug target/111020] RFE: RISC-V: ability to cherry-pick additional instructions

2023-08-14 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111020 palmer at gcc dot gnu.org changed: What|Removed |Added CC||palmer at gcc dot gnu.org

[Bug target/110748] RISC-V: optimize store of DF 0.0

2023-07-20 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110748 --- Comment #7 from palmer at gcc dot gnu.org --- (In reply to palmer from comment #6) > (In reply to Jeffrey A. Law from comment #5) > > I'd bet it's const_0_operand not allowing CONST_DOUBLE. > > > > The q

[Bug target/110748] RISC-V: optimize store of DF 0.0

2023-07-20 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110748 palmer at gcc dot gnu.org changed: What|Removed |Added CC||palmer at gcc dot gnu.org

[Bug target/110722] New: FP is Saved/Restored around inline assembly

2023-07-18 Thread palmer at gcc dot gnu.org via Gcc-bugs
: target Assignee: unassigned at gcc dot gnu.org Reporter: palmer at gcc dot gnu.org Target Milestone: --- I'm not sure if this is some ABI-related requirement that I've managed to forget about, but it looks like we're saving/restoring FP around inline assembly. l

[Bug target/110478] RISC-V multilib gcc zicsr in the -march causing incorrect libgcc to be used

2023-06-29 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110478 palmer at gcc dot gnu.org changed: What|Removed |Added CC||palmer at gcc dot gnu.org

[Bug target/109989] RISC-V: Missing sign extension with int to float conversion with 64bit soft floats

2023-06-21 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109989 --- Comment #4 from palmer at gcc dot gnu.org --- I left some cruft in that reproducer, it should have been volatile float f[2]; int x[2]; void func() { x[0] = -1; x[1] = 2; for (int i = 0; i < 1; ++i) f[i] = x[i]; } Not s

[Bug target/109989] RISC-V: Missing sign extension with int to float conversion with 64bit soft floats

2023-06-21 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109989 palmer at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed

[Bug target/110201] RISC-V: __builtin_riscv_sm4ks and __builtin_riscv_sm4ed produce invalid assembly

2023-06-19 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110201 --- Comment #6 from palmer at gcc dot gnu.org --- (In reply to Craig Topper from comment #3) > I don't have a testsuite. I saw that gcc had crypto builtins and I happened > to noticed the tests in gcc weren't passing constant ar

[Bug target/110201] RISC-V: __builtin_riscv_sm4ks and __builtin_riscv_sm4ed produce invalid assembly

2023-06-19 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110201 --- Comment #5 from palmer at gcc dot gnu.org --- (In reply to Jeffrey A. Law from comment #4) > Yea, the tests aren't great. They'll be better shortly. They'll test > non-constant arguments and out-of-range constants,

[Bug target/110201] RISC-V: __builtin_riscv_sm4ks and __builtin_riscv_sm4ed produce invalid assembly

2023-06-19 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110201 --- Comment #2 from palmer at gcc dot gnu.org --- Do you guys have a test suite for these, or did you just happen to run into it? The intrinsic testing has been a bit of a blind spot in GCC land.

[Bug target/110146] New: ICE in riscv_vector::function_builder::add_unique_function()

2023-06-06 Thread palmer at gcc dot gnu.org via Gcc-bugs
Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: palmer at gcc dot gnu.org Target Milestone: --- A few of us were talking about this in the patchwork sync today, I think Juzhe might have a fix already. I'm getting a few tho

[Bug target/109972] RISC-V: Could use umodsi3/udivsi3/divsi3 libcalls for 32-bit division/remainder on RV64 without M extension

2023-06-01 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109972 palmer at gcc dot gnu.org changed: What|Removed |Added Ever confirmed|0 |1 CC

[Bug target/109933] __atomic_test_and_set is broken for BIG ENDIAN riscv targets

2023-05-23 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109933 palmer at gcc dot gnu.org changed: What|Removed |Added CC||palmer at gcc dot gnu.org

[Bug target/104338] RISC-V: Subword atomics result in library calls

2023-05-16 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104338 --- Comment #20 from palmer at gcc dot gnu.org --- (In reply to rvalue from comment #19) > (In reply to Aurelien Jarno from comment #18) > > I wonder if the following patch should also be backported, as it > > doesn't mak

[Bug target/109547] New: RISC-V: Multiple vsetvli for load/store loop

2023-04-18 Thread palmer at gcc dot gnu.org via Gcc-bugs
: target Assignee: unassigned at gcc dot gnu.org Reporter: palmer at gcc dot gnu.org Target Milestone: --- I was just poking around with a simple loop using the vector intrinsics and found some odd generated code. This is on the gcc-13 branch, but that's pretty close to tru

[Bug rtl-optimization/108826] Inefficient address generation on POWER and RISC-V

2023-02-16 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108826 --- Comment #5 from palmer at gcc dot gnu.org --- We've run into a handful of things that look like this before, I'm not sure if it's a backend issue or something more general. There's two patterns here that are freq

[Bug target/104338] RISC-V: Subword atomics result in library calls

2023-01-26 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104338 --- Comment #12 from palmer at gcc dot gnu.org --- I've got a somewhat recently rebased version of Patrick's patch floating around, it passed testing but I got hung up on the futex_time64 thing and forgot about it. Not sure if folks

[Bug target/106585] RISC-V: Mis-optimized code gen for zbs

2022-12-08 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106585 --- Comment #10 from palmer at gcc dot gnu.org --- (In reply to Andrew Waterman from comment #9) > On Wed, Dec 7, 2022 at 7:02 PM palmer at gcc dot gnu.org via Gcc-bugs > wrote: > > > > https://gcc.gnu.org/bugzilla/show

[Bug target/106585] RISC-V: Mis-optimized code gen for zbs

2022-12-07 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106585 palmer at gcc dot gnu.org changed: What|Removed |Added CC||palmer at gcc dot gnu.org

[Bug target/106602] riscv: suboptimal codegen for zero_extendsidi2_shifted w/o bitmanip

2022-11-01 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106602 palmer at gcc dot gnu.org changed: What|Removed |Added CC||palmer at gcc dot gnu.org

[Bug target/106815] [13 Regression] ICE: in riscv_excess_precision, at config/riscv/riscv.cc:5967 with -fexcess-precision=16 on any input

2022-09-02 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106815 palmer at gcc dot gnu.org changed: What|Removed |Added CC||palmer at gcc dot gnu.org

[Bug middle-end/106818] code is genereated differently with or without 'extern'

2022-09-02 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106818 --- Comment #8 from palmer at gcc dot gnu.org --- (In reply to Andrew Pinski from comment #7) > (In reply to baoshan from comment #6) > > > really of unknown alignment then sharing the lui might not work. > > Can you elaborat

[Bug middle-end/106818] code is genereated differently with or without 'extern'

2022-09-02 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106818 palmer at gcc dot gnu.org changed: What|Removed |Added CC||palmer at gcc dot gnu.org

[Bug target/106807] RISC-V: libatomic routines are infinate loops

2022-09-01 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106807 --- Comment #3 from palmer at gcc dot gnu.org --- (In reply to Andreas Schwab from comment #1) > That happens if you use a modified compiler that automatically adds > -latomic, so that configure in libatomic thinks that the builti

[Bug target/106807] New: RISC-V: libatomic routines are infinate loops

2022-09-01 Thread palmer at gcc dot gnu.org via Gcc-bugs
: target Assignee: unassigned at gcc dot gnu.org Reporter: palmer at gcc dot gnu.org Target Milestone: --- We've started compiling some libatomic routines to infinite loops, for example testsuite/gcc.dg/atomic/stdatomic-load-1.c ends up with 000

[Bug target/106544] riscv_print_operand does not check to see if the operands are valid to do INTVAL on them

2022-08-06 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106544 palmer at gcc dot gnu.org changed: What|Removed |Added CC||palmer at gcc dot gnu.org

[Bug target/106517] New: RISC-V: Inefficient Generated Code for Floating Point to Integer Rounds

2022-08-03 Thread palmer at gcc dot gnu.org via Gcc-bugs
: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: palmer at gcc dot gnu.org Target Milestone: --- RISC-V has a handful of floating-point conversion instructions that we don't appear to be taking advantage of. For ex

[Bug target/105355] -msmall-data-limit= unexpectedly accepts a separate argument

2022-05-11 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105355 palmer at gcc dot gnu.org changed: What|Removed |Added CC||palmer at gcc dot gnu.org

[Bug tree-optimization/102892] [12/13 Regression] Dead Code Elimination Regression at -O3 (trunk vs 11.2.0)

2022-05-03 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102892 --- Comment #13 from palmer at gcc dot gnu.org --- I just posted a patch <https://gcc.gnu.org/pipermail/gcc-patches/2022-May/593995.html> that removes the undefined behavior from this test case, with that it links on RISC-V.

[Bug tree-optimization/102892] [12/13 Regression] Dead Code Elimination Regression at -O3 (trunk vs 11.2.0)

2022-05-03 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102892 palmer at gcc dot gnu.org changed: What|Removed |Added CC||palmer at gcc dot gnu.org

[Bug target/104338] RISC-V: Subword atomics result in library calls

2022-04-07 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104338 palmer at gcc dot gnu.org changed: What|Removed |Added CC||kito.cheng at gmail dot com

[Bug target/104338] RISC-V: Subword atomics result in library calls

2022-04-07 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104338 --- Comment #5 from palmer at gcc dot gnu.org --- (In reply to rvalue from comment #4) > In short term, maybe we can change the spec to link against libatomic by > default (implemented in > https://github.com/riscv-collab/riscv-g

[Bug target/104831] RISCV libatomic LR.aq/SC.rl pair insufficient for SEQ_CST

2022-03-07 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104831 --- Comment #1 from palmer at gcc dot gnu.org --- I'm not quite sure what the rules on targeting 12 for this one: it's not technically a regression, as it's always been broken, but it is a bug. I'd err on the side of taking

[Bug libstdc++/84568] libstdc++-v3 configure checks for atomic operations fail on riscv

2022-02-08 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84568 --- Comment #10 from palmer at gcc dot gnu.org --- (In reply to Jonathan Wakely from comment #7) > (In reply to Jonathan Wakely from comment #6) > > (In reply to Jonathan Wakely from comment #5) > > > (In reply to palm

[Bug libstdc++/84568] libstdc++-v3 configure checks for atomic operations fail on riscv

2022-02-07 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84568 palmer at gcc dot gnu.org changed: What|Removed |Added CC||palmer at gcc dot gnu.org

[Bug target/104338] New: RISC-V: Subword atomics result in library calls

2022-02-01 Thread palmer at gcc dot gnu.org via Gcc-bugs
Component: target Assignee: unassigned at gcc dot gnu.org Reporter: palmer at gcc dot gnu.org Target Milestone: --- There's a handful of bugs sort of related to this one, but nothing specific. This has been a long-standing issue and I think folks are generally familiar with it

[Bug target/94136] GCC doc for built-in function __builtin___clear_cache() not 100% correct

2021-04-29 Thread palmer at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94136 palmer at gcc dot gnu.org changed: What|Removed |Added CC||palmer at gcc dot gnu.org

[Bug target/85492] riscv64: endless loop when throwing an exception from a constructor

2018-04-27 Thread palmer at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85492 --- Comment #5 from palmer at gcc dot gnu.org --- Thanks Jim. This looks good to me, are you comfortable submitting glibc patches? If so then I'll commit it, otherwise I can send it out myself.

[Bug target/85492] riscv64: endless loop when throwing an exception from a constructor

2018-04-26 Thread palmer at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85492 palmer at gcc dot gnu.org changed: What|Removed |Added CC||palmer at gcc dot gnu.org

[Bug target/82717] [RISCV] Default value of the -mabi option doesn't match documentation

2017-10-27 Thread palmer at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82717 palmer at gcc dot gnu.org changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution

[Bug target/82717] [RISCV] Default value of the -mabi option doesn't match documentation

2017-10-27 Thread palmer at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82717 --- Comment #6 from palmer at gcc dot gnu.org --- Author: palmer Date: Fri Oct 27 15:22:43 2017 New Revision: 254153 URL: https://gcc.gnu.org/viewcvs?rev=254153&root=gcc&view=rev Log: RISC-V: Correct and improve the "-mabi"

[Bug target/82717] [RISCV] Default value of the -mabi option doesn't match documentation

2017-10-25 Thread palmer at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82717 --- Comment #4 from palmer at gcc dot gnu.org --- (In reply to Alex Bradbury from comment #2) > (In reply to palmer from comment #1) > > Thanks Alex -- you're correct that this is a documentation/code mismatch. I > > just tal

[Bug target/82717] [RISCV] Default value of the -mabi option doesn't match documentation

2017-10-25 Thread palmer at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82717 palmer at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |ASSIGNED Last reconfirmed

[Bug target/79912] [7 regression] LRA unable to generate reloads after r245655

2017-03-20 Thread palmer at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79912 --- Comment #18 from palmer at gcc dot gnu.org --- Author: palmer Date: Mon Mar 20 16:43:21 2017 New Revision: 246283 URL: https://gcc.gnu.org/viewcvs?rev=246283&root=gcc&view=rev Log: RISC-V: Don't prefer FP_REGS for integers