[Bug target/62275] ARM should use vcvta instructions when possible for float -> int rounding

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=62275 --- Comment #5 from Joshua Conner --- Thanks!

[Bug target/62275] New: ARM should use vcvta instructions when possible for float -> int rounding

ity: enhancement Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: josh.m.conner at gmail dot com Instead of generating a library call for lround/lroundf, the ARM backend should use vcvta.s32.f64 and vcvta.s32.f32 instructions instead

[Bug middle-end/56924] Folding of checks into a range check should check upper boundary

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=56924 --- Comment #3 from Joshua Conner --- It appears that gcc has a different approach now, which has its own advantages and disadvantages. Specifically, when I compile this same example I'm now seeing an initial tree of: if ((SAVE_EXPR & 240>)

[Bug target/56315] ARM: Improve use of 64-bit constants in logical operations

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56315 --- Comment #4 from Joshua Conner --- Excellent - thanks!

[Bug rtl-optimization/57462] ira-costs considers only a single register at a time

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57462 --- Comment #2 from Joshua Conner --- No problem - I appreciate you taking the time to respond. This has a noticeable impact on codegen for ARM because of the redundancy in the CPU/FPU functionality and cost of transferring data between integer/F

[Bug rtl-optimization/57462] New: ira-costs considers only a single register at a time

Component: rtl-optimization Assignee: unassigned at gcc dot gnu.org Reporter: josh.m.conner at gmail dot com In this code: int PopCnt(unsigned long long a, unsigned long long b) { register int c=0; while(a) { c++; a &= a + b; } return(c); } B

[Bug rtl-optimization/57231] Hoist zero-extend operations when possible

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57231 --- Comment #3 from Joshua Conner --- Exactly - there's no need to truncate every iteration, we should be able to safely do it when the loop is complete.

[Bug rtl-optimization/57231] New: Hoist zero-extend operations when possible

: rtl-optimization Assignee: unassigned at gcc dot gnu.org Reporter: josh.m.conner at gmail dot com Compiling this code at -O2: unsigned char *value; unsigned short foobar (int iters) { unsigned short total; unsigned int i; for (i = 0; i < iters

[Bug tree-optimization/56925] New: SRA should take into account likelihood of statements being executed

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56925 Bug #: 56925 Summary: SRA should take into account likelihood of statements being executed Classification: Unclassified Product: gcc Version: 4.9.0 Status:

[Bug c/56924] New: Folding of checks into a range check should check upper boundary

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56924 Bug #: 56924 Summary: Folding of checks into a range check should check upper boundary Classification: Unclassified Product: gcc Version: 4.9.0 Status: UNCO

[Bug tree-optimization/56352] New: Simplify testing of related conditions in for loop

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56352 Bug #: 56352 Summary: Simplify testing of related conditions in for loop Classification: Unclassified Product: gcc Version: 4.8.0 Status: UNCONFIRMED Severity: normal

[Bug target/56315] New: ARM: Improve use of 64-bit constants in logical operations

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56315 Bug #: 56315 Summary: ARM: Improve use of 64-bit constants in logical operations Classification: Unclassified Product: gcc Version: 4.8.0 Status: UNCONFIRME

[Bug target/56313] aarch64 backend not using fmls instruction

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56313 --- Comment #1 from Joshua Conner 2013-02-14 01:39:55 UTC --- In case it helps, the pattern for aarch64_vmls is written as: (set (op0) (minus (op1) (mult (op2) (op3 Restructuring this to: (set (op0)

[Bug target/56313] New: aarch64 backend not using fmls instruction

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56313 Bug #: 56313 Summary: aarch64 backend not using fmls instruction Classification: Unclassified Product: gcc Version: 4.8.0 Status: UNCONFIRMED Severity: enhancement

[Bug tree-optimization/56094] Invalid line number info generated with tree-level ivopts

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56094 --- Comment #2 from Joshua Conner 2013-01-24 04:05:09 UTC --- Sorry, I should have been more specific -- the function I'm describing in the previous comments is "test_main".

[Bug tree-optimization/56094] Invalid line number info generated with tree-level ivopts

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56094 --- Comment #1 from Joshua Conner 2013-01-24 04:03:44 UTC --- Created attachment 29263 --> http://gcc.gnu.org/bugzilla/attachment.cgi?id=29263 Reduced test case

[Bug tree-optimization/56094] New: Invalid line number info generated with tree-level ivopts

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56094 Bug #: 56094 Summary: Invalid line number info generated with tree-level ivopts Classification: Unclassified Product: gcc Version: 4.8.0 Status: UNCONFIRMED

[Bug rtl-optimization/55747] New: Extra registers are saved in functions that only call noreturn functions

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55747 Bug #: 55747 Summary: Extra registers are saved in functions that only call noreturn functions Classification: Unclassified Product: gcc Version: 4.8.0 Stat

[Bug target/55701] New: Inline some instances of memset for ARM

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55701 Bug #: 55701 Summary: Inline some instances of memset for ARM Classification: Unclassified Product: gcc Version: 4.8.0 Status: UNCONFIRMED Severity: enhancement

[Bug c/55681] New: Qualifiers on asm statements are order-dependent

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55681 Bug #: 55681 Summary: Qualifiers on asm statements are order-dependent Classification: Unclassified Product: gcc Version: 4.8.0 Status: UNCONFIRMED Severity: normal

[Bug middle-end/55653] New: Unnecessary initialization of vector register

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55653 Bug #: 55653 Summary: Unnecessary initialization of vector register Classification: Unclassified Product: gcc Version: 4.8.0 Status: UNCONFIRMED Severity: enhancement

[Bug tree-optimization/55213] vectorizer ignores __restrict__

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55213 --- Comment #4 from Joshua Conner 2012-11-29 22:17:50 UTC --- I'm also seeing this same issue in libgfortran's matmul_r8.c, where the inner loop has an aliasing check even though all of the pointer dereferences are via restricted pointers.

[Bug tree-optimization/55213] vectorizer ignores __restrict__

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55213 Joshua Conner changed: What|Removed |Added CC||josh.m.conner at gmail dot

[Bug tree-optimization/55216] New: Infinite loop generated on non-infinite code

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55216 Bug #: 55216 Summary: Infinite loop generated on non-infinite code Classification: Unclassified Product: gcc Version: 4.8.0 Status: UNCONFIRMED Severity: normal

[Bug lto/48508] ICE in output_die, at dwarf2out.c:11409

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48508 Joshua Conner changed: What|Removed |Added CC||josh.m.conner at gmail dot