[Bug target/117928] New: z14 builtin for VLBR instruction missing

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117928 Bug ID: 117928 Summary: z14 builtin for VLBR instruction missing Product: gcc Version: 14.2.1 Status: UNCONFIRMED Severity: normal Priority: P3 Component: targe

[Bug target/117568] New: z13: Use vector instructions for fixed length memcmp

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117568 Bug ID: 117568 Summary: z13: Use vector instructions for fixed length memcmp Product: gcc Version: 13.2.0 Status: UNCONFIRMED Severity: normal Priority: P3 Comp

[Bug target/117561] New: z13/z14 Please add a scalar_test_data_class builtin

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117561 Bug ID: 117561 Summary: z13/z14 Please add a scalar_test_data_class builtin Product: gcc Version: 13.2.0 Status: UNCONFIRMED Severity: normal Priority: P3 Compo

[Bug target/116649] New: PPC: Suboptimal code for __builtin_bcdadd_ovf on Power10

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116649 Bug ID: 116649 Summary: PPC: Suboptimal code for __builtin_bcdadd_ovf on Power10 Product: gcc Version: 14.1.0 Status: UNCONFIRMED Severity: normal Pr

[Bug target/115973] PPCLE: Inefficient code for __builtin_uaddll_overflow and __builtin_addcll

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115973 --- Comment #2 from Jens Seifert --- Assembly that better integrates: unsigned long long addc_opt(unsigned long long a, unsigned long long b, unsigned long long *res) { unsigned long long rc; __asm__("addc %0,%2,%3;\n\tsubfe %1,%1,%1":"=r

[Bug target/115973] New: PPCLE: Inefficient code for __builtin_uaddll_overflow and __builtin_addcll

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115973 Bug ID: 115973 Summary: PPCLE: Inefficient code for __builtin_uaddll_overflow and __builtin_addcll Product: gcc Version: 14.1.0 Status: UNCONFIRMED Severity: n

[Bug target/115355] [12/13/14/15 Regression] vectorization exposes wrong code on P9 LE starting from r12-4496

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115355 --- Comment #10 from Jens Seifert --- Does this affect loop vectorize and slp vectorize ? -fno-tree-loop-vectorize avoids loop vectorization to be performed and workarounds this issue. Does the same problems also affect SLP vectorization, which

[Bug target/115355] PPCLE: Auto-vectorization creates wrong code for Power9

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115355 --- Comment #1 from Jens Seifert --- Same issue with gcc 13.2.1

[Bug target/115355] New: PPCLE: Auto-vectorization creates wrong code for Power9

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115355 Bug ID: 115355 Summary: PPCLE: Auto-vectorization creates wrong code for Power9 Product: gcc Version: 12.2.1 Status: UNCONFIRMED Severity: normal Pri

[Bug target/114376] New: s390: Inefficient __builtin_bswap16

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114376 Bug ID: 114376 Summary: s390: Inefficient __builtin_bswap16 Product: gcc Version: 13.2.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target

[Bug target/93176] PPC: inefficient 64-bit constant consecutive ones

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93176 --- Comment #10 from Jens Seifert --- Looks like no patch in the area got delivered. I did a small test for unsigned long long c() { return 0xULL; } gcc 13.2.0: li 3,0 ori 3,3,0x

[Bug target/93176] PPC: inefficient 64-bit constant consecutive ones

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93176 --- Comment #7 from Jens Seifert --- What happened ? Still waiting for improvement.

[Bug target/106770] PPCLE: Unnecessary xxpermdi before mfvsrd

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106770 --- Comment #6 from Jens Seifert --- The left part of VSX registers overlaps with floating point registers, that is why no register xxpermdi is required and mfvsrd can access all (left) parts of VSX registers directly. The xxpermdi x,y,y,3 indic

[Bug target/106770] PPCLE: Unnecessary xxpermdi before mfvsrd

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106770 --- Comment #4 from Jens Seifert --- PPCLE with no special option means -mcpu=power8 -maltivec (altivecle to be mor precise). vec_promote(, 1) should be a noop on ppcle. But value gets splatted to both left and right part of vector register. =

[Bug c++/108560] New: builtin_va_arg_pack_len is documented to return size_t, but actually returns int

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108560 Bug ID: 108560 Summary: builtin_va_arg_pack_len is documented to return size_t, but actually returns int Product: gcc Version: 12.2.0 Status: UNCONFIRMED Sever

[Bug target/108396] New: PPCLE: vec_vsubcuq missing

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108396 Bug ID: 108396 Summary: PPCLE: vec_vsubcuq missing Product: gcc Version: 12.2.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target As

[Bug target/108049] s390: Compiler adds extra zero extend after xoring 2 zero extended values

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108049 --- Comment #1 from Jens Seifert --- Sample above got compiled with -march=z196

[Bug target/108049] New: s390: Compiler adds extra zero extend after xoring 2 zero extended values

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108049 Bug ID: 108049 Summary: s390: Compiler adds extra zero extend after xoring 2 zero extended values Product: gcc Version: 12.2.0 Status: UNCONFIRMED Severity: no

[Bug rtl-optimization/107949] PPC: Unnecessary rlwinm after lbzx

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107949 --- Comment #3 from Jens Seifert --- *** Bug 108048 has been marked as a duplicate of this bug. ***

[Bug target/108048] PPCLE: gcc does not recognize that lbzx does zero extend

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108048 Jens Seifert changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/108048] New: PPCLE: gcc does not recognize that lbzx does zero extend

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108048 Bug ID: 108048 Summary: PPCLE: gcc does not recognize that lbzx does zero extend Product: gcc Version: 12.2.0 Status: UNCONFIRMED Severity: normal Pr

[Bug target/107949] PPC: Unnecessary rlwinm after lbzx

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107949 --- Comment #1 from Jens Seifert --- hash2 is only provided to show how the code should look like (without rlwinm).

[Bug target/107949] New: PPC: Unnecessary rlwinm after lbzx

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107949 Bug ID: 107949 Summary: PPC: Unnecessary rlwinm after lbzx Product: gcc Version: 12.2.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target

[Bug target/107757] New: PPCLE: Inefficient vector constant creation

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107757 Bug ID: 107757 Summary: PPCLE: Inefficient vector constant creation Product: gcc Version: 12.2.1 Status: UNCONFIRMED Severity: normal Priority: P3 Component: ta

[Bug target/86160] Implement isinf on PowerPC

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86160 --- Comment #4 from Jens Seifert --- I am looking forward to get Power9 optimization using xststdcdp etc.

[Bug target/106770] PPCLE: Unnecessary xxpermdi before mfvsrd

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106770 --- Comment #2 from Jens Seifert --- vec_extract(vr, 1) should extract the left element. But xxpermdi x,x,x,3 extracts the right element. Looks like a bug in vec_extract for PPCLE and not a problem regarding unnecessary xxpermdi. Using assembly

[Bug target/106770] PPCLE: Unnecessary xxpermdi before mfvsrd

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106770 --- Comment #1 from Jens Seifert --- vec_extract(vr, 1) should extract the left element. But xxpermdi x,x,x,3 extracts the right element. Looks like a bug in vec_extract for PPCLE and not a problem regarding unnecessary xxpermdi.

[Bug target/106770] New: PPCLE: Unnecessary xxpermdi before mfvsrd

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106770 Bug ID: 106770 Summary: PPCLE: Unnecessary xxpermdi before mfvsrd Product: gcc Version: 11.2.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: targ

[Bug target/106769] New: PPCLE: vec_extract(vector unsigned int) unnecessary rldicl after mfvsrwz

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106769 Bug ID: 106769 Summary: PPCLE: vec_extract(vector unsigned int) unnecessary rldicl after mfvsrwz Product: gcc Version: 11.2.0 Status: UNCONFIRMED Severity: nor

[Bug target/106701] New: s390: Compiler does not take into account number range limitation to avoid subtract from immediate

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106701 Bug ID: 106701 Summary: s390: Compiler does not take into account number range limitation to avoid subtract from immediate Product: gcc Version: 11.2.0 Status: UNCONFIRM

[Bug target/106598] New: s390: Inefficient branchless conditionals for int

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106598 Bug ID: 106598 Summary: s390: Inefficient branchless conditionals for int Product: gcc Version: 11.2.0 Status: UNCONFIRMED Severity: normal Priority: P3 Compone

[Bug target/106592] New: s390: Inefficient branchless conditionals for long long

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106592 Bug ID: 106592 Summary: s390: Inefficient branchless conditionals for long long Product: gcc Version: 11.2.0 Status: UNCONFIRMED Severity: normal Pri

[Bug target/106536] New: P9: gcc does not detect setb pattern

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106536 Bug ID: 106536 Summary: P9: gcc does not detect setb pattern Product: gcc Version: 11.2.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target

[Bug target/106525] New: s390: Inefficient branchless conditionals for unsigned long long

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106525 Bug ID: 106525 Summary: s390: Inefficient branchless conditionals for unsigned long long Product: gcc Version: 11.2.0 Status: UNCONFIRMED Severity: normal

[Bug target/106043] Power10: lacking vec_blendv builtins

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106043 Jens Seifert changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/106043] Power10: lacking vec_blendv builtins

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106043 --- Comment #1 from Jens Seifert --- Found in documentation: https://gcc.gnu.org/onlinedocs/gcc-11.3.0/gcc/PowerPC-AltiVec-Built-in-Functions-Available-on-ISA-3_002e1.html#PowerPC-AltiVec-Built-in-Functions-Available-on-ISA-3_002e1

[Bug c/106043] New: Power10: lacking vec_blendv builtins

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106043 Bug ID: 106043 Summary: Power10: lacking vec_blendv builtins Product: gcc Version: 11.2.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: c

[Bug target/104268] New: 390: inefficient vec_popcnt for 16-bit for z13

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104268 Bug ID: 104268 Summary: 390: inefficient vec_popcnt for 16-bit for z13 Product: gcc Version: 10.2.1 Status: UNCONFIRMED Severity: normal Priority: P3 Component:

[Bug target/103743] New: PPC: Inefficient equality compare for large 64-bit constants having only 16-bit relevant bits in high part

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103743 Bug ID: 103743 Summary: PPC: Inefficient equality compare for large 64-bit constants having only 16-bit relevant bits in high part Product: gcc Version: 8.3.1

[Bug target/103731] New: 390: inefficient 64-bit constant generation

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103731 Bug ID: 103731 Summary: 390: inefficient 64-bit constant generation Product: gcc Version: 8.3.1 Status: UNCONFIRMED Severity: normal Priority: P3 Component: tar

[Bug target/103106] New: PPC: Missing builtin for P9 vmsumudm

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103106 Bug ID: 103106 Summary: PPC: Missing builtin for P9 vmsumudm Product: gcc Version: 8.3.1 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target

[Bug target/102265] New: s390: Inefficient code for __builtin_ctzll

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102265 Bug ID: 102265 Summary: s390: Inefficient code for __builtin_ctzll Product: gcc Version: 10.2.1 Status: UNCONFIRMED Severity: normal Priority: P3 Component: tar

[Bug target/102117] s390: Inefficient code for 64x64=128 signed multiply for <= z13

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102117 --- Comment #1 from Jens Seifert --- Sorry small bug in optimal sequence. __int128 imul128_opt(long long a, long long b) { unsigned __int128 x = (unsigned __int128)(unsigned long long)a; unsigned __int128 y = (unsigned __int128)(unsigned

[Bug target/102117] New: s390: Inefficient code for 64x64=128 signed multiply for <= z13

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102117 Bug ID: 102117 Summary: s390: Inefficient code for 64x64=128 signed multiply for <= z13 Product: gcc Version: 8.3.1 Status: UNCONFIRMED Severity: normal

[Bug target/100866] PPC: Inefficient code for vec_revb(vector unsigned short) < P9

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100866 --- Comment #9 from Jens Seifert --- I know that if I would use vec_perm builtin as an end user, that you then need to fulfill to the LE specification, but you can always optimize the code as you like as long as it creates correct results afterw

[Bug target/100866] PPC: Inefficient code for vec_revb(vector unsigned short) < P9

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100866 --- Comment #7 from Jens Seifert --- Regarding vec_revb for vector unsigned int. I agree that revb: .LFB0: .cfi_startproc vspltish %v1,8 vspltisw %v0,-16 vrlh %v2,%v2,%v1 vrlw %v2,%v2,%v0 blr work

[Bug target/101041] New: z13: Inefficient handling of vector register passed to function

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101041 Bug ID: 101041 Summary: z13: Inefficient handling of vector register passed to function Product: gcc Version: 8.3.1 Status: UNCONFIRMED Severity: normal

[Bug target/100930] New: PPC: Missing builtins for P9 vextsb2w, vextsb2w, vextsb2d, vextsh2d, vextsw2d

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100930 Bug ID: 100930 Summary: PPC: Missing builtins for P9 vextsb2w, vextsb2w, vextsb2d, vextsh2d, vextsw2d Product: gcc Version: 8.3.1 Status: UNCONFIRMED Severity:

[Bug target/100926] New: PPCLE: Inefficient code for vec_xl_be(unsigned short *) < P9

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100926 Bug ID: 100926 Summary: PPCLE: Inefficient code for vec_xl_be(unsigned short *) < P9 Product: gcc Version: 8.3.1 Status: UNCONFIRMED Severity: normal

[Bug target/100808] PPC: ISA 3.1 builtin documentation

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100808 --- Comment #3 from Jens Seifert --- - Avoid additional "int" unsigned long long int => unsigned long long Why? Those are exactly the same types! Yes, but the rest of the documentation uses unsigned long long. This is just for consistency wit

[Bug target/100871] New: z14: vec_doublee maps to wrong builtin in vecintrin.h

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100871 Bug ID: 100871 Summary: z14: vec_doublee maps to wrong builtin in vecintrin.h Product: gcc Version: 10.2.1 Status: UNCONFIRMED Severity: normal Priority: P3 Com

[Bug target/100869] New: z13: Inefficient code for vec_reve(vector double)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100869 Bug ID: 100869 Summary: z13: Inefficient code for vec_reve(vector double) Product: gcc Version: 10.2.1 Status: UNCONFIRMED Severity: normal Priority: P3 Compone

[Bug target/100868] New: PPC: Inefficient code for vec_reve(vector double)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100868 Bug ID: 100868 Summary: PPC: Inefficient code for vec_reve(vector double) Product: gcc Version: 8.3.1 Status: UNCONFIRMED Severity: normal Priority: P3 Componen

[Bug target/100867] New: z13: Inefficient code for vec_revb(vector unsigned short)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100867 Bug ID: 100867 Summary: z13: Inefficient code for vec_revb(vector unsigned short) Product: gcc Version: 10.2.1 Status: UNCONFIRMED Severity: normal P

[Bug target/100866] New: PPC: Inefficient code for vec_revb(vector unsigned short) < P9

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100866 Bug ID: 100866 Summary: PPC: Inefficient code for vec_revb(vector unsigned short) < P9 Product: gcc Version: 8.3.1 Status: UNCONFIRMED Severity: normal

[Bug c/100808] PPC: ISA 3.1 builtin documentation

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100808 --- Comment #1 from Jens Seifert --- https://gcc.gnu.org/onlinedocs/gcc/PowerPC-AltiVec-Built-in-Functions-Available-on-ISA-3_002e1.html vector unsigned long long int vec_gnb (vector unsigned __int128, const unsigned char) should be unsigned

[Bug c++/100809] PPC: __int128 divide/modulo does not use P10 instructions vdivsq/vdivuq

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100809 --- Comment #1 from Jens Seifert --- Same applies to modulo.

[Bug c++/100809] New: PPC: __int128 divide/modulo does not use P10 instructions vdivsq/vdivuq

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100809 Bug ID: 100809 Summary: PPC: __int128 divide/modulo does not use P10 instructions vdivsq/vdivuq Product: gcc Version: 10.2.1 Status: UNCONFIRMED Severity: norm

[Bug c/100808] New: PPC: ISA 3.1 builtin documentation

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100808 Bug ID: 100808 Summary: PPC: ISA 3.1 builtin documentation Product: gcc Version: 12.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: c A

[Bug target/100694] New: PPC: initialization of __int128 is very inefficient

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100694 Bug ID: 100694 Summary: PPC: initialization of __int128 is very inefficient Product: gcc Version: 8.3.1 Status: UNCONFIRMED Severity: normal Priority: P3 Compon

[Bug target/100693] New: PPC: missing 64-bit addg6s

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100693 Bug ID: 100693 Summary: PPC: missing 64-bit addg6s Product: gcc Version: 8.3.1 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target Ass

[Bug target/98020] PPC: mfvsrwz+extsw not merged to mtvsrwa

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98020 Jens Seifert changed: What|Removed |Added Status|WAITING |RESOLVED Resolution|---

[Bug target/98124] New: Z: Load and test LTDBR instruction gets not used for comparison against 0.0

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98124 Bug ID: 98124 Summary: Z: Load and test LTDBR instruction gets not used for comparison against 0.0 Product: gcc Version: 8.3.0 Status: UNCONFIRMED Severity: nor

[Bug target/98020] New: PPC: mfvsrwz+extsw not merge to mtvsrwa

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98020 Bug ID: 98020 Summary: PPC: mfvsrwz+extsw not merge to mtvsrwa Product: gcc Version: 8.3.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target

[Bug target/70928] Load simple float constants via VSX operations on PowerPC

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70928 Jens Seifert changed: What|Removed |Added CC||jens.seifert at de dot ibm.com --- Commen